KR100276564B1 - Method of manufacturing a flash EEPROM cell and methods of programming erasing and reading the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash EEPROM cell and a method for erasing and reading a program of the same are provided to form different values of saturation current by two floating gates. CONSTITUTION: A select gate(13) is formed by forming sequentially a select gate oxide layer(12), a polysilicon layer for select gate, and the dielectric layer(14) on a semiconductor substrate(11). The first dielectric layer spacer(15) is formed at a sidewall of the select gate(13). A threshold voltage control implantation process is performed at one side of the select gate(13). A tunnel oxide layer(17) is formed on an exposed portion of the semiconductor substrate(11). A polysilicon layer for floating gate is deposited on a whole structure. The first and the second floating gates(18a,18b) are formed by performing an etching process. A source region(19a) and a drain region(19b) are formed by implanting a dopant. A control gate(21) is formed by forming and patterning the second dielectric layer(20) and the polysilicon layer for control gate on the entire structure.

Description

Method of manufacturing a flash EEPROM cell and methods of programming erasing and reading the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash EEPROM cell and a method of driving the same, and in particular, by doubling the density in the same area using first and second floating gates having different threshold voltages. The present invention relates to a method for manufacturing a flash ypyrom cell and a program, an erase and a read method thereof, which achieve the same effect.

The biggest obstacle to the popularization of flash Y pyrom is the high cost per unit of information. In order to overcome this, high integration of cells is essential, and each manufacturer is making a lot of efforts to achieve this. However, since the flash Y pyrom has a relatively complicated structure compared to DRAM, there are many difficulties in high integration. Recently, Intel announced 32/64 M, which is manufactured by storing 2 bits in one cell, and multi-bit cells are becoming a subject of intense research and development among manufacturers. .

Accordingly, in the present invention, by forming floating gates having different threshold voltages on both sides of the select gate, the degree of integration can be improved by acquiring different saturation currents by a combination of program / erase of the two floating gates and a bias of the control gate. It is an object of the present invention to provide a method for manufacturing a flash ypyrom cell and a method for erasing and reading the same.

In order to achieve the above object, a method of manufacturing a flash y-pyrom cell according to the present invention is to sequentially form a select gate oxide film, a select gate polysilicon film, and a first dielectric film on a semiconductor substrate, and then pattern and form a select gate. Forming a dielectric film spacer on the sidewall of the select gate, performing a threshold voltage control ion implantation process on the semiconductor substrate on one side of the select gate, and a tunnel oxide film on an exposed portion of the semiconductor substrate. Forming first and second floating gates having different threshold voltages on both sides of the select gate by a process of depositing and etching a polysilicon film for the floating gate on the entire structure after forming the self-implantation process And a source on the semiconductor substrate After the forming the areas, forming a second dielectric film and a polysilicon film for the control gate to the entire upper structure by patterning, including the step of forming the control gate characterized in that formed.

1 (a) to 1 (d) are cross-sectional views of devices for explaining a method for manufacturing a flash ypyrom cell according to the present invention.

2 is a cross-sectional view of a device for explaining the operation of a flash ypyrom cell according to the present invention.

<Description of Signs of Major Parts of Drawings>

11 semiconductor substrate 12 select gate oxide film

13 select gate 14 first dielectric film

15 dielectric film spacer 16 photosensitive film pattern

17 tunnel oxide film 18 polysilicon spacer

18a: first floating gate 18b: second floating gate

19a: source region 19b: drain region

20: second dielectric film 21: control gate

In the present invention, as a cell capable of four states, the effect of greatly increasing the degree of integration is to be obtained. For example, four conventional cells are required to obtain 16 different states, but in the present invention, 16 different states can be obtained with two cells.

In a MOS transistor, the saturation current has a different value depending on its literary voltage. Therefore, different saturation currents can be obtained by adjusting the states of floating gates having different threshold voltages, which can be used in different states.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (d) are cross-sectional views of devices for explaining a method for manufacturing a flash ypyrom cell according to the present invention.

Referring to FIG. 1A, a select gate oxide film 12, a select gate polysilicon film 13, and a first dielectric film 14 are sequentially formed on the semiconductor substrate 11. The select gate 13 is formed by sequentially etching the first dielectric film 14, the select gate polysilicon film 13, and the select gate oxide film 12 by a photolithography process and an etching process using a select gate mask. . The dielectric film spacer 15 is formed on the sidewall of the select gate 13.

Referring to FIG. 1B, a photoresist film is coated on the entire structure and then patterned to form a photoresist pattern 16 exposing a portion of the semiconductor substrate 11 around the select gate 13. An ion implantation process for adjusting the threshold voltage is performed on the semiconductor substrate 11 having the photoresist pattern 16 exposed as a mask.

Referring to FIG. 1C, after the photoresist pattern 16 is removed, the tunnel oxide layer 17 is formed on the exposed semiconductor substrate 11 on both sides of the select gate 13. The polysilicon film for the floating gate is deposited on the entire structure, and an etching process is performed to form the polysilicon spacer 18 on the dielectric film spacers 15 on both sides of the select gate 13. The source / drain impurity ion implantation process is performed in a self-aligning manner to form source and drain regions 19a and 19b on the semiconductor substrate 11. The polysilicon spacer 18 serves as a floating gate, and threshold voltage adjusting ions are implanted on the semiconductor substrate 11 under different conditions to have different threshold voltages.

Referring to FIG. 1 (d), the second dielectric film 20 and the polysilicon film 21 for the control gate are sequentially formed on the entire structure. A photolithography process and an etching process using a mask for a control gate are performed to sequentially etch the control gate polysilicon film 21, the second dielectric film 20, and the polysilicon spacer 18. As a result, first and second floating gates 18a and 18b having spacers having different threshold voltages are formed on both sidewalls of the select gate 13, and the select gate 13, the first and second floating gates 18a and 18b) The control gate 21 is formed on the top. In the etching process using the mask for the control gate, the first dielectric layer 14 serves as an etch stop layer so that the select gate 13 is not etched.

The operation of the flash Y pyrom cell manufactured by the above-described process will be described with reference to FIG. 2 as follows.

Program operation of the flash Ipyrom cell is performed by emitting electrons from the floating gate using Fowler-Nordheim (F-N) tunneling.

In a state in which the semiconductor substrate 11 is floated, a voltage of about -10V is applied to the control gate 21, a voltage of about -5V is applied to the select gate 13, and the source 19a and the drain are applied. When a voltage of about 5V is applied to 19b, electrons are emitted from the first and second floating gates 18a and 18b, and the first and second floating gates 18a and 18b are programmed.

Under the above voltage application conditions, when a voltage of about -5V is applied to the drain 19b, electrons are emitted from the first floating gate 18a so that only the first floating gate 18a is in a program state, and the source 19a is sourced. When a voltage of about -5V is applied to the electrons, electrons are emitted from the second floating gate 18b so that only the second floating gate 18b is in a program state.

The Erase operation of the flash ypyrom cell is performed by injecting electrons into the floating gate using Fowler-Nordheim (F-N) tunneling.

In a state in which the semiconductor substrate 11 is floated, a voltage of about 10V is applied to the control gate 21, a voltage of about 5V is applied to the select gate 13, and the source 19a and the drain 19b are applied. When a voltage of about -5V is applied to each of the electrons, electrons are injected into the first and second floating gates 18a and 18b, and the first and second floating gates 18a and 18b are erased.

Under the above voltage application conditions, when a voltage of about 5 V is applied to the drain 19b, electrons are injected into the first floating gate 18a so that only the first floating gate 18a is erased, and the source 19a is applied. When a voltage of about 5V is applied to the electrons, electrons are injected into the second floating gate 18b so that only the second floating gate 18b is in an erased state.

The read operation of the flash Y pyrom cell applies a voltage of about 7V to the control gate 21, a voltage of about 5V to the select gate 13, and the source 19a and the semiconductor substrate 11 This is done by grounding and applying a voltage of about 1V to the drain 19b.

As described above, according to the present invention, by adjusting the threshold voltages of the floating gates formed on both sides of the select gate differently, different saturation currents can be obtained by a combination of programming and erasing of the two floating gates and a bias of the control gate. You can double the density.

Claims (9)

Forming a select gate by sequentially forming and patterning a select gate oxide film, a select gate polysilicon film, and a first dielectric film on the semiconductor substrate; Forming a dielectric film spacer on sidewalls of the select gate; Performing a threshold voltage adjusting ion implantation process on the semiconductor substrate on one side of the select gate; After the tunnel oxide film is formed on the exposed portion of the semiconductor substrate, first and second floating gates having different threshold voltages are formed on both sides of the select gate by a process of depositing and etching a polysilicon film for floating gate on the entire structure. To do that, Performing source impurity ion implantation in a self-aligned manner to form source and drain regions on the semiconductor substrate; And forming a control gate by forming a second dielectric film and a polysilicon film for control gate on the entire structure, and then patterning the control gate to form a control gate. A select gate formed in a predetermined region above the semiconductor substrate, first and second floating gates formed to have different threshold voltages on both sides of the select gate, a source formed in the semiconductor substrate toward the first floating gate, A method of programming a flash Y-pyrom cell comprising a drain formed on the semiconductor substrate toward a second floating gate and a control gate formed on the select gate, the first and second floating gates, Floating the semiconductor substrate, applying a first negative voltage to the control gate, and applying the second negative voltage to the select gate, the first and second floating according to voltage conditions applied to the source and drain. At least one of the first and second floating gates is programmed because electrons are emitted from at least one of the gates. The method of claim 2, The first negative voltage applied to the control gate is about -10V and the second negative voltage applied to the select gate is about -5V. The method of claim 2, When a voltage of about 5V is applied to the source and a drain, respectively, the first and second floating gates are in a program state, when a voltage of about 5V is applied to the source and a voltage of about -5V is applied to the drain. Only the first floating gate is in a programmed state, and when a voltage of about -5V is applied to the source and a voltage of about 5V is applied to the drain, only the second floating gate is in a program state. How to program a cell. A select gate formed in a predetermined region above the semiconductor substrate, first and second floating gates formed to have different threshold voltages on both sides of the select gate, a source formed in the semiconductor substrate toward the first floating gate, A method for erasing a flash Y-pyrom cell comprising a drain formed on the semiconductor substrate toward a second floating gate and a control gate formed on the select gate, the first and second floating gates, Floating the semiconductor substrate, applying a first positive voltage to the control gate, and applying the second positive voltage to the select gate, the first and second floating according to voltage conditions applied to the source and drain. At least one of the first and second floating gates is erased because electrons are injected into at least one of the gates. The method of claim 5, The first positive voltage applied to the control gate is about 10V, the second positive voltage applied to the select gate is about 5V. The method of claim 5, When a voltage of about -5V is applied to the source and drain, respectively, the first and second floating gates are in an erased state, a voltage of about -5V is applied to the source, and a voltage of about 5V is applied to the drain. In this case, only the first floating gate is in an erased state, and when a voltage of about 5V is applied to the source and a voltage of about -5V is applied to the drain, only the second floating gate is in an erased state. Method of erasing pyrom cells. A select gate formed in a predetermined region above the semiconductor substrate, first and second floating gates formed to have different threshold voltages on both sides of the select gate, a source formed in the semiconductor substrate toward the first floating gate, A method for reading a flash Y pyrom cell comprising a drain formed on the semiconductor substrate toward a second floating gate and a control gate formed on the select gate, the first and the second floating gate, A first positive voltage applied to the control gate, a second positive voltage smaller than the control gate to the select gate, and a third positive voltage smaller than the select gate to the drain, with the source and substrate grounded A read method of a flash Y pyrom cell, characterized in that to perform a read operation by applying a. The method of claim 8, The first positive voltage applied to the control gate is about 7V, the second positive voltage applied to the select gate is about 5V, and the third positive voltage applied to the drain is about 1V. How to Read Cells.