KR100275124B1 - Operational amplifier using differential structure - Google Patents

Abstract

The present invention relates to an operational amplifier of a fully differential structure, wherein the operational amplifier of the fully differential structure includes a common mode region expansion means comprising a pair of an input and an N-type transistor for gate inputting an input signal, and the common mode. A pair of current compensation means connected to a region expansion means and additionally supplying current to the common mode region expansion means in response to an input of a control voltage, and an N-type transistor pair of the common mode region expansion means formed between the first power supply and the output node. A load means for supplying a load to an output node in response to an output of the output and a second control voltage, and formed between the output node and the second power supply and operating in response to the output of the common mode region expansion means. With the current mirror means to increase, the common mode area of the input stage is wide and the noise removal performance is good, so An analog-to-digital converter that requires a category, a digital-to-analog converter, the applicability is greatly etc. SCF.

Description

Operational Amplifier of Fully Differential Structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to amplifiers used in logic circuits and the like, and more particularly to operational amplifiers (OP-Amps) having a fully differencial structure.

As is well known, op amps called op amps have an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a switched capacitor filter, and a continuous time filter. It is a basic component used for Continuous Time Filter, etc., and its application field is wide. These op amps have a large gain-bandwidth and have noise rejection and a wide dynamic range for on-chip conversion with digital blocks. Is needed.

In this regard, an operational amplifier of a conventional fully differential structure is disclosed in FIG. The configuration of FIG. 1 includes input transistors N1 and N2 for inputting first and second input signals VINP and VINN, and first to fourth bias voltages VBIAS1, VBIAS2, VBIAS3, and VBIAS4 in response to an input. It consists of switching circuits. In the circuit of FIG. 1, transistor pairs having a symmetrical structure in which the transistors commonly control input the same bias voltages are connected in series between the power supply voltage Vcc and the ground voltage GND.

However, since the operational amplifier of FIG. 1 is largely composed of an N-type or P-type differential pair, when the power supply Vcc decreases, the threshold voltages of the input transistors N1 and N2 and Since the minimum voltage occupies a large portion of the saturation region, the input common-mode range is limited. In addition, PSRR (Power Supply Rejection Ratio) and CMRR (Common Mode Rejection Ratio), which are parameters of the circuit characteristics, are not so large, which has a disadvantage in that the dynamic range is small.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an operational amplifier of a fully differential structure in which the input stage has a wide common mode region.

Another object of the present invention is to provide an operational amplifier of a fully differential structure having a wide common mode region of the input stage and excellent noise removal performance.

It is still another object of the present invention to provide an operational amplifier of a fully differential structure having excellent applicability to a circuit requiring a wide dynamic range.

1 is an operational amplifier circuit diagram of a fully differential structure according to the prior art;

2 is an operational amplifier circuit diagram of a fully differential structure according to the present invention;

* Explanation of the main symbols in the drawings

10: common mode area extension part

20: current compensator

30, 40: load part

50A, 50B: Current Mirror

The operational amplifier of the fully-differential structure according to the present invention for achieving the above object is connected to and controlled by a common mode region expansion unit configured to include an input and an N-type transistor pair for gate input of an input signal, and the common mode region expansion unit. A current compensator for additionally supplying current to the common mode region extension part in response to the input of a voltage, and an output of the N-type transistor pair and a second control voltage input formed between the first power supply and the output node; And a load unit configured to supply a load to an output node in response to the load, and a current mirror unit formed between the output node and the second power supply and operating in response to the output of the common mode region expansion unit to increase the gain. .

The common mode region expansion unit may include a pull-up transistor having one end connected to a first power supply and switching in response to an input of a first bias voltage, and one end connected to the pull-up transistor connected to one end of the channel, respectively. A channel is formed between a pair of a pair of transistors correspondingly inputting a signal, an n-type transistor pair correspondingly inputting the first and second input signals, a channel between the n-type transistor pair and the second power supply, and a second bias. And a pull-down transistor for switching in response to the input of the voltage. The pull-up transistor is characterized in that consisting of the morph transistor. The pull-down transistor is characterized in that the configuration of the en-mo transistor.

The current compensator may be connected to a first PMOS transistor having a channel connected between a first power supply and a pull-up transistor of the common mode region expansion unit, a source and a gate connected to the first power source, and a gate of the first PMOS transistor. A first NMOS transistor, the channel being formed between the second PMOS transistor comprising a drain, the drain of the second PMOS transistor, and the pull-down transistor of the common mode region extension, and gate-input a second bias voltage; A third PMOS transistor having a gate input of one bias voltage and a source connected to a pull-up transistor of the common mode region extension unit, a channel connected between a drain of the third PMOS transistor and a second power supply, and the third PMOS transistor A second NMOS transistor, the first NMOS transistor and a second power source A channel is connected to the third NMOS transistor, and the gate is connected to the drain of the third PMOS transistor.

The load unit includes a PMOS transistor in which each source is connected in parallel to a first power supply, the gate inputs to the first bias voltage in common, and a drain thereof is correspondingly connected to a channel of an enmos transistor pair of the common mode region extension unit. And a second load part including a first load part configured as a pair, and a pair of morph transistors having a channel correspondingly formed between the first load part and the first and second output nodes and commonly gate-connected to a third bias voltage. Characterized in that configured.

The current mirror unit includes a first current mirror and a second output node formed with a channel between the first output node and the second power supply and operating in response to the output of the first transistor of the PMOS transistor pair of the common mode region extension unit. And a second current mirror having a channel formed between the second power supply and the second power source, the second current mirror operating in response to the output of the second transistor of the PMOS transistor pair of the common mode region extension unit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Fig. 2 discloses an operational amplifier circuit of a fully differential structure according to the present invention. The configuration of Fig. 2 is as follows. That is, the common mode region expansion unit 10 and the common mode region expansion unit 10 including the paired and n-type transistor pairs for gate-input of the input signals VINP and VINN, and the control voltages VBIAS1 and VBIAS2 are connected. A current compensator 20 for additionally supplying current to the common mode region extender 10 in response to an input, and is formed between a first power supply Vcc and an output node OUTP and OUTN, and the common mode region extender 10 Load portions 30 and 40 for supplying loads to the output nodes OUTP and OUTN in response to the output of the pair of N-type transistors of VBIAS1 and VBIAS3, and between the output nodes OUTP and OUTN and the second power supply GND. In response to the output of the common mode region expansion section 10 is configured to include the current mirror portion (50A, 50B) to increase the gain.

The common mode range extension unit 10 is a PMOS as a pull-up transistor, in which one end of a channel is connected to a first power supply Vcc and switching in response to an input of a bias voltage of VBIAS1. (PMOS) transistors P3 and PMOS transistors P1 and P2 having one end of a channel connected to the PMOS transistor P3 and correspondingly inputting first and second input signals VINP and VINN respectively; And a channel is formed between NMOS transistors N1 and N2 corresponding to gate inputs of the VINP and VINN, a common source of the NMOS transistors N1 and N2, and a second power supply GND. It consists of NMOS transistor N3 as a pull-down transistor that switches in response to an input.

The current compensation unit 20 may include a PMOS transistor P5 having a channel connected between the power supply Vcc and the PMOS transistor P3 of the common mode region expansion unit 10, a source and a gate connected to the power supply Vcc, and the A channel is formed between the PMOS transistor P6 including a drain commonly connected to the gate of the PMOS transistor P5, the drain of the PMOS transistor P6, and the NMOS transistor N3 of the common mode region expansion unit 10, and a VBIAS2 voltage. NMOS transistor N4 for gate input, PMO transistor P4 having a gate input to VBIAS voltage, and a source connected to PMOS transistor P3 of the common mode region expansion unit 10, and a drain and power supply GND of the PMOS transistor P4. A channel connected between the NMOS transistor N5 and a gate connected to the drain of the PMOS transistor P4, and the NMOS transistor A channel is connected between N4 and the power supply GND, and is configured as an enMOS transistor N6 gated to the drain of the PMOS transistor P4.

The load units 30 and 40 have respective sources connected in parallel to the power supply Vcc, gate input the VBIAS1 voltage in common, and drains correspondingly to the NMOS transistors N1 and N2 of the common mode region expansion unit 10. A first load part 30 composed of PMOS transistors P7 and P8 connected to the channel, and the first load part 30 and the first and second output nodes OUTP and OUTN (which may also mean output signals). A second load portion 40 composed of PMOS transistors P9 and P10 having a channel formed therein and commonly gate-connected to the VBIAS3 voltage.

The current mirror units 50A and 50B include a first channel formed between an output node OUTP and a power supply GND and operating in response to an output of the PMOS transistor P1 of the common mode region expansion unit 10. A channel is formed between the current mirror 50A, the output node OUTN, and the power supply GND, and includes a second current mirror 50B that operates in response to the output of the PMOS transistor P2 of the common mode region expansion unit 10. .

The first current mirror 50A includes an NMOS transistor N7 having a drain connected to an output node OUTP and a gate connected to a drain of the PMOS transistor P1 of the common mode region expansion unit 10, and the common mode region expansion unit ( An NMOS transistor N8 in which a gate and a drain are commonly connected to a drain of the PMOS transistor P1 of FIG. 10, a channel is formed between the NMOS transistor N7 and the power supply GND, and an N gate in which a gate is connected to a source of the NMOS transistor N8. A channel is formed between the MOS transistor N9 and the NMOS transistor N8 and the power supply GND, and includes an MOS transistor N10 in which a gate and a drain are commonly connected.

The second current mirror 50B includes an NMOS transistor N12 having a drain connected to the output node OUTN and a gate connected to the drain of the PMOS transistor P2 of the common mode region expansion unit 10, and the common mode region expansion unit 10. NMOS transistor N11 having a gate and a drain commonly connected to the drain of PMOS transistor P2, and an NMOS transistor whose gate is connected to the NMOS transistor N811 source with a channel formed between the NMOS transistor N12 and the power supply GND. A channel is formed between N14 and the NMOS transistor N11 and the power supply GND, and the NMOS transistor N14 has a gate and a drain connected in common.

Referring to the operation according to the configuration of Figure 2 as follows.

In FIG. 2, the common mode region expansion unit is an N-type differential pair, which is composed of NMOS transistors N1 and N2, a P-type differential pair, and PMOS transistors P1 and P2, and the differential differential pair is a PMOS transistor. A bias current is supplied to P3, and the N-type differential pair supplies a bias current to NMOS transistor N3.

Meanwhile, PMOS transistors P5 and P6 constituting a current mirror in the current compensator 20 have a transconductance when the differential pair of the n-type is switched off and the differential pair of the to-be-shaped is switched on. ) If we supply 4 times the current to make gm equal to gm when both differential pairs are on (because gm is proportional to [IDS0]), it will be equal. To do this, if the width / length ratio of the PMOS transistors P5 and P6 is set to 1: 3, the gm of the differential pair of the type is the same as when both differential pairs are switched on. NMOS transistors N5 and N6 conversely supply a bias current to the N-type differential pair when the differential pair is switched on and the differential pair is switched off to make gm constant. The PMOS transistor P4 supplies a bias current from the PMOS transistor P3 when the differential pair is switched off and the N-type differential pair is switched on. When the P4 is switched on, N4 is switched off. NMOS transistor N4 is a transistor that connects bias current to the differential pair when the n-type differential pair is switched off and the differential pair is switched on. When the switching is on, the PMOS transistor P4 is off.

PMOS transistors P7, P8, P9, and P10 constituting the first and second load parts 30 and 40 are transistors for supplying loads to the output nodes OUTP and OUTN in response to inputs of the bias voltages VBIAS1 and VBIAS3. .

NMOS transistors N7, N9, N12 and N14 in the first and second current mirrors 50A and 50B are transistors that sink the output. NMOS transistors N8, N10, N11, and N13 form current mirrors with N7, N9, N11, and N13 to increase output resistance, increase gain, and eliminate in-phase noise. Let's do it.

According to the present invention, unlike the operational amplifier of the conventional differential structure, the input terminal is composed of two differential pairs of N-type and type, so that when the operating region is switched on only “1. Y-type differential pair, 2. 2. only the differential differential pair is switched on. 3) and the common mode area becomes wider. In addition, the gm value when both differential pairs are switched on is about twice as large as when only one of the N-type and the differential pairs are switched on, so that gm is not constant in the operating region, but is compensated by the current compensation unit 20 to compensate for this. If one differential pair (en or fig) is switched on, it supplies more current, resulting in a constant gm. In the output stage, the symmetrical structure of the first current mirror 50A and the second current mirror 50B removes in-phase noise when passing through the current mirror, so that the common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are removed. Can improve.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has a large common mode region of the input stage and good noise removal performance, so that the present invention is applicable to an analog-digital converter, a digital analog converter, and an SCF that require a wide dynamic range.

Claims (6)

In the operational amplifier of the fully differential structure, Common mode region expansion means configured to include an input-type and en-type transistor pair for gate inputting an input signal; Current compensating means connected to said common mode region extending means and additionally supplying current to said common mode region extending means in response to input of a control voltage; Load means formed between a first power supply and an output node and supplying a load to an output node in response to an output of an N-type transistor pair of the common mode region expansion means and an input of a second control voltage; And A current mirror means formed between the output node and a second power supply and operating in response to the output of the common mode region expansion means to increase the gain Operational amplifier of a fully differential structure, including. The method of claim 1, The common mode region expansion means may include a pull-up transistor connected to one end of a channel to a first power supply and switching in response to an input of a first bias voltage, and one end of a channel connected to the pull-up transistor, respectively. A channel is formed between the pair of transistors for inputting an input signal correspondingly, the pair of n-type transistors correspondingly inputting the first and second input signals, and the channel between the pair of n-type transistors and the second power supply. An operational amplifier with a fully differential structure including a pull-down transistor that switches in response to an input of a bias voltage. The method of claim 2, The pull-up transistor is a PMOS transistor, the pull-down transistor is an operational amplifier of a fully differential structure consisting of the enmo transistor. The method of claim 2, The current compensation means is common to a first PMOS transistor having a channel connected between a first power supply and a pull-up transistor of the common mode region expansion means, a source and a gate connected to the first power source, and a gate of the first PMOS transistor. A first NMOS transistor, the channel being formed between the second PMOS transistor comprising a drain connected to the drain, the drain of the second PMOS transistor and the pull-down transistor of the common mode region expansion means, and a gate inputting a second bias voltage; And a third PMOS transistor having a gate input of a first bias voltage and a source connected to a pull-up transistor of the common mode region extending means, and a channel connected between the drain and the second power supply of the third PMOS transistor. A second NMOS transistor gate-connected to the drain of the 3 PMOS transistor, and the first NMOS transistor Second channel is connected between the power supply and the third operand of the fully differential amplifier structure including a gate of the third MOS transistor en connection to the drain of the MOS transistor. The method of claim 4, wherein The load means may include a source connected in parallel to a first power source, a gate input of the first bias voltage in common, and a drain correspondingly connected to a channel of an enMOS transistor pair of the common mode region expansion means. A second load means comprising a first load means composed of a MOS transistor pair, and a PMOS transistor pair having a channel correspondingly formed between the first load means and the first and second output nodes and commonly connected to a third bias voltage. Operational amplifier of fully differential structure including load means. The method of claim 5, The current mirror means includes: a first current mirror configured to form a channel between the first output node and the second power supply and operate in response to the output of the first transistor of the PMOS transistor pair of the common mode region expansion means; And a second current mirror having a channel formed between the output node and the second power supply and operating in response to the output of the second transistor of the PMOS transistor pair of the common mode region expansion means.