CN116455335B - Programmable gain amplifier, analog-to-digital converter and chip - Google Patents
Programmable gain amplifier, analog-to-digital converter and chip Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The application provides a programmable gain amplifier, an analog-to-digital converter and a chip, comprising: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, an operational amplifier and a current compensation module; wherein; the input end of the current compensation module is connected with the reverse input end of the operational amplifier, the output end of the current compensation module is connected with the reverse output end of the operational amplifier, the reverse input voltage of the operational amplifier is converted into compensation current, and the currents of the forward output end and the reverse output end of the operational amplifier are balanced. The application connects a compensation current with input voltage information to the reverse output end of the operational amplifier, thus balancing the output voltage of the reverse output end and the voltage of the forward output end, reducing the output distortion and improving the linearity of the programmable gain amplifier.
Description
Technical Field
The present application relates to the field of analog-to-digital conversion, and in particular, to a programmable gain amplifier, an analog-to-digital converter, and a chip.
Background
With computer applications, programmable gain amplifiers (Programmable Gain Amplifier, PGA) may be used to amplify input voltages in order to drive differential ADC operation in data acquisition systems, power line monitoring and protection systems, etc. applications in order to reduce hardware devices as much as possible. As an amplifier with extremely high universality, the amplification factor of the programmable amplifier can be regulated and controlled by a program according to the requirement. With such an amplifier, it is possible to uniformize the full-scale signal of the a/D converter, thereby improving the detection accuracy.
The bipolar single-ended input and differential output programmable gain amplifier has the advantages that the output distortion and nonlinearity of the programmable gain amplifier are increased due to large input common mode variation and unbalanced output current.
Based on the above, the application provides a programmable gain amplifier, an analog-to-digital converter and a chip, which are used for solving the problems of output distortion and linearity reduction of the programmable gain amplifier with single-ended input and differential output.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a programmable gain amplifier, an analog-to-digital converter and a chip for solving the problems of distortion and reduced linearity of the single-ended input and differential output programmable gain amplifier in the prior art.
To achieve the above and other related objects, the present application provides a programmable gain amplifier comprising: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, an operational amplifier and a current compensation module;
wherein the resistance of the first resistor is equal to the resistance of the third resistor; the resistance value of the second resistor is equal to the resistance value of the fourth resistor;
the first end of the first resistor is connected with an input voltage, and the second end of the first resistor is connected with the positive input end of the operational amplifier;
the second resistor is connected between the positive input end and the negative output end of the operational amplifier;
the first end of the third resistor is grounded, and the second end of the third resistor is connected with the reverse input end of the operational amplifier;
the fourth resistor is connected between the reverse input end and the forward output end of the operational amplifier;
the input end of the current compensation module is connected with the reverse input end of the operational amplifier, the output end of the current compensation module is connected with the reverse output end of the operational amplifier, and the reverse input voltage of the operational amplifier is converted into compensation current, so that the currents of the forward output end and the reverse output end of the operational amplifier are balanced.
Alternatively, the process may be carried out in a single-stage,the method comprises the steps of carrying out a first treatment on the surface of the Wherein I is the compensation current, vxn is the reverse input voltage of the operational amplifier, R1 is the first resistor, R2 is the second resistor, and Vocm is the common mode output voltage of the operational amplifier.
Optionally, the current compensation module comprises a first voltage-current conversion unit, a second voltage-current conversion unit, a first current mirror, a second current mirror and an output unit; the input end of the first voltage-current conversion unit is connected with the common mode output voltage of the operational amplifier and used for converting the common mode output voltage into first current; the input end of the first current mirror is connected with the output end of the first voltage-current conversion unit and outputs a first current mirror image; the input end of the second voltage-current conversion unit is connected with the reverse input voltage of the operational amplifier and used for converting the reverse input voltage into second current; the input end of the second current mirror is connected with the output end of the second voltage-current conversion unit and outputs a second current mirror image; the first input end of the output unit is connected with the output end of the first current mirror, the second input end of the output unit is connected with the output end of the second current mirror, and the compensation current is obtained and output based on the output current of the first current mirror and the output current of the second current mirror.
Optionally, the first voltage-current conversion unit includes a first operational amplifier, a fifth resistor and a first NMOS transistor;
the positive input end of the first operational amplifier is connected with the common mode output voltage, the negative input end of the first operational amplifier is connected with the source electrode of the first NMOS tube, and the output end of the first operational amplifier is connected with the grid electrode of the first NMOS tube; the first end of the fifth resistor is connected with the source electrode of the first NMOS tube, the second end of the fifth resistor is grounded, and the common mode output voltage is converted into the first current based on the fifth resistor; and the drain electrode of the first NMOS tube is connected with the input end of the first current mirror.
Optionally, the first current mirror includes a first PMOS tube and a second PMOS tube; the source electrode of the first PMOS tube is connected with the working voltage, the drain electrode of the first PMOS tube is connected with the output end of the first voltage-current conversion unit, and the grid electrode of the first PMOS tube is connected with the drain electrode; and the source electrode of the second PMOS tube is connected with the working voltage, the drain electrode of the second PMOS tube is connected with the output unit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube.
Optionally, the mirror factor of the first current mirror satisfies:the method comprises the steps of carrying out a first treatment on the surface of the Wherein K1 is the mirror factor of the first current mirror; r5 is the resistance value of the fifth resistor.
Optionally, the second voltage-current conversion unit includes a second operational amplifier, a sixth resistor and a second NMOS transistor; the positive input end of the second operational amplifier is connected with the reverse input voltage of the operational amplifier, the reverse input end of the second operational amplifier is connected with the source electrode of the second NMOS tube, and the output end of the second operational amplifier is connected with the grid electrode of the second NMOS tube; the first end of the sixth resistor is connected with the source electrode of the second NMOS tube, the second end of the sixth resistor is grounded, and the reverse input voltage is converted into the second current based on the sixth resistor; and the drain electrode of the second NMOS tube is connected with the input end of the second current mirror.
Optionally, the second current mirror includes a third PMOS transistor and a fourth PMOS transistor; the source electrode of the third PMOS tube is connected with the working voltage, the drain electrode of the third PMOS tube is connected with the output end of the second voltage-current conversion unit, and the grid electrode of the third PMOS tube is connected with the drain electrode; and the source electrode of the fourth PMOS tube is connected with the working voltage, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the output unit.
Optionally, the mirror factor of the second current mirror satisfies:
wherein K2 is the mirror factor of the second current mirror; r6 is the resistance value of the sixth resistor.
Optionally, the output unit includes a third NMOS tube and a fourth NMOS tube; the drain electrode of the third NMOS tube is connected with the output end of the second current mirror, the source electrode is grounded, and the grid electrode is connected with the source electrode; the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the output end of the first current mirror and outputs the compensation current.
To achieve the above and other related objects, the present application provides an analog-to-digital converter comprising: the programmable gain amplifier described above.
To achieve the above and other related objects, the present application provides a chip comprising: the programmable gain amplifier described above.
As described above, the programmable gain amplifier, the analog-to-digital converter and the chip of the application have the following beneficial effects:
1. the programmable gain amplifier, the analog-to-digital converter and the chip of the application lead the voltage of the reverse output end and the voltage of the forward output end to be balanced by connecting the compensation current with the input voltage information to the reverse output end of the operational amplification module, thereby reducing the output distortion and improving the linearity of the programmable gain amplifier.
2. The programmable gain amplifier, the analog-to-digital converter and the chip have simple structures and can be well applied to the field of analog-to-digital conversion.
Drawings
Fig. 1 is a schematic diagram of a programmable gain amplifying circuit.
Fig. 2 is a graph showing the relationship between the input voltage and the common mode output voltage of the programmable gain amplifying circuit of fig. 1.
Fig. 3 is a graph showing the relationship between the input voltage and the output current of the programmable gain amplifying circuit of fig. 1.
Fig. 4 shows a schematic diagram of the programmable gain amplifier according to the present application.
Fig. 5 is a schematic diagram of a current compensation module according to the present application.
Description of element reference numerals
1-a programmable gain amplification circuit; a 2-programmable gain amplifier; 21-a current compensation module; 211-a first voltage-current conversion unit; 212-a first current mirror; 213-a second voltage-current conversion unit; 214-a second current mirror; 215-an output unit.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Comparative example one
As shown in fig. 1, a single-ended input, differential output programmable gain amplification circuit 1 includes: first input resistor R IN1 A second input resistor R IN2 A first radio frequency resistor R F1 A second radio frequency resistor R F2 And an operational amplifier OPA.
Specifically, in this comparative example, the first input resistor R IN1 Is equal to the resistance of the second input resistor R IN2 Resistance value of (2); the first radio-frequency resistor R F1 Is equal to the resistance of the second radio-frequency resistor R F2 Resistance value of (2)The method comprises the steps of carrying out a first treatment on the surface of the The first input resistor R IN1 Is connected with the input voltage V IN The second end is connected with the positive input end of the operational amplifier OPA; the first radio-frequency resistor R F1 The first end of the first filter is connected with the positive input end of the operational amplifier OPA, and the second end of the first filter is connected with the negative output end of the operational amplifier OPA; the second input resistor R IN2 The second end is connected with the reverse input end of the operational amplifier OPA; the second radio-frequency resistor R F2 The first end of the filter is connected with the reverse input end of the operational amplifier OPA, and the second end of the filter is connected with the forward output end of the operational amplifier OPA.
The input voltage is amplified and output based on the programmable gain amplification circuit 1. Fig. 2 shows the relationship between the input voltage VIN of the programmable gain amplifying circuit 1 and the common-mode input voltage, and fig. 3 shows the relationship between the input voltage VIN of the programmable gain amplifying circuit 1 and the forward output current Iop and the reverse output current Ion, respectively. As can be seen from fig. 2 and 3, when the input voltage VIN is constant, the common-mode input voltage is constant, but the output current is not equal to the forward output current Iop and the reverse output current Ion, that is, there is output distortion, which results in the reduced linearity performance of the programmable gain amplification circuit 1, and the reason for the unbalanced output current of the programmable gain amplification circuit 1 is further analyzed below.
The forward output current Iop of the programmable gain amplification circuit 1 satisfies:
（1）
wherein, the liquid crystal display device comprises a liquid crystal display device,a forward output current of the programmable gain amplifying circuit 1;is a second input resistor;is a common mode input voltage.
The reverse output terminal current Ion of the programmable gain amplification circuit 1 satisfies:
(2)
wherein, the liquid crystal display device comprises a liquid crystal display device,an inverted output current of the programmable gain amplifying circuit 1;is the input voltage;is the first input resistor.
Due to the first input resistance R IN1 Is equal to the resistance of the second input resistor R IN2 Thus comparing equation (1) with equation (2), the reverse output current of the programmable gain amplification circuit 1Positive output current of the phase contrast programmable gain amplifying circuit 1Reduced current and input voltage V IN Related to the following. Based on this, for letting the reverse output current of the programmable gain amplifying circuit 1Equal to the forward output current of the programmable gain amplification circuit 1It is necessary to compensate for a certain current value, which has a certain relation to the magnitude of the input voltage VIN.
The specific value of the compensation current I is further calculated.Is a common mode input voltage and satisfies:
（3）
wherein, the liquid crystal display device comprises a liquid crystal display device,for the value of the voltage at the positive input of the programmable gain amplification circuit 1,is the voltage value of the reverse input end of the programmable gain amplifying circuit 1; due to the first input resistance R IN1 The resistance value of (2) is equal to the second input resistor R IN2 Is used for the resistance value of the (a),r is the input resistance value of each input end in the programmable gain amplifying circuit 1 IN = R IN1= R IN2 The method comprises the steps of carrying out a first treatment on the surface of the Due to the first radio-frequency resistance R F1 The resistance value of (2) is equal to the second radio frequency resistor R F2 Is used for the resistance value of the (a),the input ports of the programmable gain amplifying circuit 1 are connected with the radio frequency resistance value of the output port, R F = R F1= R F2 ；The common mode output voltage of the programmable gain amplifying circuit 1.
Therefore, the forward output voltage of the programmable gain amplification circuit 1Can further satisfy the following conditions:
（4）
wherein, the liquid crystal display device comprises a liquid crystal display device,a positive output terminal voltage of the programmable gain amplifying circuit 1;is an overdrive voltage.
Reverse output voltage of programmable gain amplifying circuit 1Can further satisfy the following conditions:
（5）
wherein, the liquid crystal display device comprises a liquid crystal display device,is the reverse output voltage of the programmable gain amplification circuit 1.
Overdrive voltageThe method meets the following conditions:
（6）
therefore, the voltage at the positive input terminal of the programmable gain amplification circuit 1The method meets the following conditions:
（7）
reverse input voltage of programmable gain amplifying circuit 1The method meets the following conditions:
（8）
to be based on input voltage V IN Obtaining a compensation current of the reverse output terminal by using the voltage of the reverse input terminal of the programmable gain amplifying circuit 1As voltage input without directly using input voltageThereby avoiding the occurrence of off-rail voltages.
Thus, the inverting input terminal voltage of the programmable gain amplification circuit 1 is calculated according to the formula (8)The relationship with the input voltage is further written as:
（9）
the voltage at the inverting input of the programmable gain amplifier circuit 1 is further obtained according to equation (9)The relation with the compensation current I satisfies:
（10）
according to equation (10), it is shown that the compensation current I andandis proportional to the difference between the given scores of (c).
Example 1
In order to obtain a compensation current I based on Vxn at the inverting output of the programmable gain amplifier circuit 1, the present embodiment provides a programmable gain amplifier 2.
As shown in fig. 4, the present embodiment provides a programmable gain amplifier 2 including: the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the operational amplifier OPA, and the current compensation module 21.
As shown in FIG. 4, the first resistorThe resistance value of R1 is equal to the resistance value of the third resistor R3; the resistance value of the second resistor R2 is equal to the resistance value of the fourth resistor R4; the first end of the first resistor R1 is connected with the input voltage VIN, and the second end of the first resistor R1 is connected with the positive input end Vxp of the operational amplifier OPA; a first end of the second resistor R2 is connected with a second end of the first resistor R1, and a second end of the second resistor R2 is connected with the reverse output end V of the operational amplifier OPA OUTN The method comprises the steps of carrying out a first treatment on the surface of the The first end of the third resistor R3 is grounded, and the second end is connected with the reverse input end V of the operational amplifier OPA XN The method comprises the steps of carrying out a first treatment on the surface of the The first end of the fourth resistor R4 is connected with the reverse input end of the operational amplifier OPA, and the second end of the fourth resistor R is connected with the forward output end of the operational amplifier OPA.
As shown in fig. 4, the input terminal of the current compensation module 21 is connected to the inverting input terminal VXN of the operational amplifier OPA, and the output terminal is connected to the inverting output terminal VOUTN of the operational amplifier OPA, so as to convert the inverting input voltage of the operational amplifier OPA into the compensation current I, thereby balancing the forward output terminal current Iop and the inverting output terminal current Ion of the operational amplifier.
Specifically, the compensation current I satisfies:
（11）
wherein I is the compensation current, vxn is the reverse input voltage of the operational amplifier, R1 is the first resistor, R2 is the second resistor, and Vocm is the common mode output voltage of the operational amplifier.
That is, the current required for obtaining the formula (10) in the present comparative example by the formula (11) is outputted as the compensation current I to the inverting output terminal V OUTN。
More specifically, in the present embodiment, as shown in fig. 5, the current compensation module 21 includes a first voltage-current conversion unit 211, a second voltage-current conversion unit 213, a first current mirror 212, a second current mirror 214, and an output unit 215. By constructing a circuit containing Vxn and containing Vocm satisfying the formula (11), the compensation current I is obtained.
Further, the input end of the first voltage-current conversion unit 211 is connected to the common-mode output voltage Vocm of the operational amplifier OPA, so as to convert the common-mode output voltage Vocm into the first current I1.
As an example, the first voltage-current conversion unit 211 includes a first operational amplifier AMP-1, a fifth resistor R5, and a first NMOS transistor NM1; the positive input end of the first operational amplifier AMP-1 is connected with the common mode output voltage Vocm, the negative input end is connected with the source electrode of the first NMOS tube NM1, and the output end is connected with the grid electrode of the first NMOS tube NM 1. The current of the branch where the first NMOS tube NM1 is located is controlled based on the output voltage of the first operational amplifier AMP-1, so that the first current I1 meets I1=. The input voltage across the fifth resistor R5 is copied by the first operational amplifier AMP-1 and the voltage signal is converted into a current signal by the first NMOS transistor NM 1. The first end of the fifth resistor R5 is connected to the source of the first NMOS transistor NM1, and the second end thereof is grounded, so that the common-mode output voltage Vocm is converted into the first current I1 based on the fifth resistor R5. The drain electrode of the first NMOS transistor NM1 is connected to the input end of the first current mirror 212, and inputs the first current to the first current mirror 212.
Further, in the present embodiment, the input end of the first current mirror 212 is connected to the output end of the first voltage-current conversion unit 211, and outputs the first current I1 in a mirror image. The current including the information of the common mode output voltage Vocm is multiplied by a preset scaling factor by setting the first current mirror 212 and output. In this embodiment, if the mirror factor of the first current mirror 212 is set to K1, the current output by the first current mirror 212 is k1×i1.
As an example, the first current mirror 212 includes a first PMOS tube PM1 and a second PMOS tube PM2; the source electrode of the first PMOS PM1 is connected to the working voltage VDD, the drain electrode is connected to the first voltage-current conversion unit 211 (in this embodiment, the drain electrode of the first PMOS PM1 is connected to the drain electrode of the first NMOS NM 1), and the gate electrode is connected to the drain electrode; the source electrode of the second PMOS PM2 is connected to the working voltage VDD, the drain electrode is connected to the output unit 215, and the gate electrode is connected to the gate electrode of the first PMOS PM 1. It should be noted that, the specific structure of the first current mirror 212 is not limited to the embodiment, and any structure capable of multiplying the first current I1 of the branch where the first NMOS transistor NM1 is located by the preset scaling factor is the protection scope of the embodiment.
In this embodiment, the mirror factor K1 of the first current mirror satisfies:
；
wherein K1 is the mirror factor of the first current mirror; r5 is the resistance value of the fifth resistor.
Further, an input terminal of the second voltage-to-current conversion unit 213 is connected to an inverted input voltage Vxn of the operational amplifier OPA, so as to convert the inverted input voltage Vxn into a second current I2.
As an example, the second voltage-current conversion unit 213 includes a second operational amplifier AMP-2, a sixth resistor R6, and a second NMOS transistor NM2; the positive input end of the second operational amplifier AMP-2 is connected with the reverse input voltage Vxn of the operational amplifier OPA, the reverse input end is connected with the source electrode of the second NMOS tube NM2, and the output end is connected with the grid electrode of the second NMOS tube NM 2. The current of the branch where the second NMOS tube NM2 is located is controlled based on the output voltage of the second operational amplifier AMP-2, so that the second current I2 meets I2=. The voltage across the sixth resistor R6 is duplicated by the second operational amplifier AMP-2 and the voltage signal is converted into a current signal (i.e., the second current I2) by the second NMOS transistor NM 2. The first end of the sixth resistor R6 is connected to the source of the second NMOS transistor NM2, and the second end is grounded, so that the reverse input voltage Vxn is converted into the second current I2 based on the sixth resistor R6. The drain electrode of the second NMOS transistor NM2 is connected to the second current mirror 214, and inputs a second current I2 to the second current mirror 214.
More specifically, an input terminal of the second current mirror 214 is connected to an output terminal of the second voltage-to-current conversion unit 213, and outputs a second current I2 in mirror image. The current including the information of the reverse input voltage Vxn is multiplied by a preset scaling factor by setting the second current mirror 214 and output. In this embodiment, if the mirror factor of the second current mirror 214 is set to K2, the current output by the second current mirror is k2×i2.
As an example, the second current mirror 214 includes a third PMOS tube PM3 and a fourth PMOS tube PM4; the source electrode of the third PMOS PM3 is connected to the working voltage VDD, the drain electrode is connected to the output end of the second voltage-current conversion unit 213 (in this embodiment, the drain electrode of the third PMOS PM3 is connected to the drain electrode of the second NMOS NM 2), and the gate electrode is connected to the drain electrode; the source electrode of the fourth PMOS PM4 is connected to the working voltage VDD, the gate electrode is connected to the gate electrode of the third PMOS PM3, and the drain electrode is connected to the input end of the output unit 215. It should be noted that, the specific structure of the second current mirror 214 is not limited to the embodiment, and any structure capable of multiplying the first current I2 of the branch where the second NMOS transistor NM2 is located by the preset scaling factor is the protection scope of the embodiment.
In this embodiment, the mirror factor K2 of the second current mirror 214 satisfies:
；
wherein K2 is the mirror factor of the second current mirror 214; r1 is the resistance value of the first resistor; r6 is the resistance value of the sixth resistor. For ease of setting the circuit and ease of calculation, in another example, the first resistor R1 may be further set equal to the second resistor R2, and the mirror factor K2 of the second current mirror 214 may be further expressed as k2=。
More specifically, the output unit 215 has a first input terminal connected to the output terminal of the first current mirror 212, a second input terminal connected to the output terminal of the second current mirror 214, and a compensation current I is obtained based on the difference between the output current (k1×i1) of the first current mirror 212 and the output current (k2×i2) of the second current mirror and is output.
As an example, the output unit 215 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4; the drain electrode of the third NMOS transistor NM3 is connected to the output end of the second current mirror (in this embodiment, the drain electrode of the third NMOS transistor NM3 is connected to the drain electrode of the fourth PMOS transistor PM 4), the source electrode is grounded, and the gate electrode is connected to the source electrode; the source electrode of the fourth NMOS transistor NM4 is grounded, the gate electrode is connected to the gate electrode of the third NMOS transistor NM3, and the drain electrode is connected to the output end of the first current mirror (in this embodiment, the drain electrode of the fourth NMOS transistor NM4 is connected to the drain electrode of the second PMOS transistor PM 2). In the present embodiment, the current (k1×i1) output by the first current mirror 212 is different from the current (k2×i2) output by the second current mirror to obtain the compensation current I. In the present embodiment, the fourth NMOS transistor NM4 and the third NMOS transistor NM3 are arranged to form a current mirror, the output current (K2×I2) of the second current mirror 214 is mirrored to the circuit where the fourth NMOS transistor NM4 is located, and then at the output terminal V OUTN A compensation circuit I is obtained. The mirror factor between the fourth NMOS transistor NM4 and the third NMOS transistor NM3 together form a current mirror is 1:1, and does not further amplify the output current of the second current mirror 214. It should be noted that, in practice, the mirror factor of the current mirror formed by the fourth NMOS transistor NM4 and the third NMOS transistor NM3 may be set to other values as required, so long as the compensation current can be finally obtained based on the first current mirror 212, the second current mirror 214, and the output unit 215Is the protection scope of the present embodiment.
In the present embodiment, the first operational amplifier AMP-1 converts the voltage of the fifth resistor into a first current and multiplies the first current by a first mirror factor K1The second operational amplifier AMP-2 converts the voltage of the sixth resistor into a second current and multiplies the second current by a second mirror factor K2The method comprises the steps of carrying out a first treatment on the surface of the Thus finally obtainedThe compensation current is i=i2-i1== The method comprises the following steps: the current compensation module 21 of the present embodiment realizes the compensation current I required by the formula (11).
The present embodiment also provides an analog-to-digital converter, including: the sampling module, the analog-to-digital conversion module and the programmable gain amplifier 2 are arranged in the circuit; the programmable gain amplifier 2 is disposed between the sampling module and the analog-to-digital conversion module, amplifies the received input voltage signal of the sampling module, and outputs the amplified input voltage signal to the analog-to-digital conversion module of the rear stage so as to increase the dynamic range of the analog-to-digital conversion module of the rear stage, thereby improving the accuracy of the analog-to-digital converter.
The embodiment also provides a chip, including: the programmable gain amplifier 2 described above. The chip is used for improving the gain range by directly packaging a programmable gain amplifier 2, so that the chip is applied to the fields of precision measurement and signal amplification. In actual use, the range of gain can be further enlarged by cascading a plurality of chips, so that the chips are applied to occasions with higher signal precision, such as medical equipment, communication equipment and the like.
In summary, the present application provides a programmable gain amplifier, an analog-to-digital converter and a chip, comprising: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, an operational amplifier and a current compensation module; wherein; the input end of the current compensation module is connected with the reverse input end of the operational amplifier, the output end of the current compensation module is connected with the reverse output end of the operational amplifier, the reverse input voltage of the operational amplifier is converted into compensation current, and the currents of the forward output end and the reverse output end of the operational amplifier are balanced. The application connects a compensation current with input voltage information to the reverse output end of the operational amplifier, thus balancing the output voltage of the reverse output end and the voltage of the forward output end, reducing the output distortion and improving the linearity of the programmable gain amplifier. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. A programmable gain amplifier, the programmable gain amplifier comprising at least: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, an operational amplifier and a current compensation module;
wherein the resistance of the first resistor is equal to the resistance of the third resistor; the resistance value of the second resistor is equal to the resistance value of the fourth resistor;
the first end of the first resistor is connected with an input voltage, and the second end of the first resistor is connected with the positive input end of the operational amplifier;
the second resistor is connected between the positive input end and the negative output end of the operational amplifier;
the first end of the third resistor is grounded, and the second end of the third resistor is connected with the reverse input end of the operational amplifier;
the fourth resistor is connected between the reverse input end and the forward output end of the operational amplifier;
the first input end of the current compensation module is connected with the reverse input end of the operational amplifier, the second input end of the current compensation module is connected with the common mode output voltage of the operational amplifier, the output end of the current compensation module is connected with the reverse output end of the operational amplifier, and the reverse input voltage of the operational amplifier is converted into compensation current, so that the currents of the forward output end and the reverse output end of the operational amplifier are balanced;
the current compensation module comprises a first voltage-current conversion unit, a second voltage-current conversion unit, a first current mirror, a second current mirror and an output unit;
the input end of the first voltage-current conversion unit is connected with the common mode output voltage of the operational amplifier and used for converting the common mode output voltage into first current;
the input end of the first current mirror is connected with the output end of the first voltage-current conversion unit and outputs a first current mirror image;
the input end of the second voltage-current conversion unit is connected with the reverse input voltage of the operational amplifier and used for converting the reverse input voltage into second current;
the input end of the second current mirror is connected with the output end of the second voltage-current conversion unit and outputs a second current mirror image;
the first input end of the output unit is connected with the output end of the first current mirror, the second input end of the output unit is connected with the output end of the second current mirror, and the compensation current is obtained and output based on the output current of the first current mirror and the output current of the second current mirror.
2. A programmable gain amplifier according to claim 1, characterized in that: the compensation current satisfies:
；
wherein I is the compensation current, vxn is the reverse input voltage of the operational amplifier, R1 is the first resistor, R2 is the second resistor, and Vocm is the common mode output voltage of the operational amplifier.
3. A programmable gain amplifier according to claim 2, characterized in that: the first voltage-current conversion unit comprises a first operational amplifier, a fifth resistor and a first NMOS tube;
the positive input end of the first operational amplifier is connected with the common mode output voltage, the negative input end of the first operational amplifier is connected with the source electrode of the first NMOS tube, and the output end of the first operational amplifier is connected with the grid electrode of the first NMOS tube;
the first end of the fifth resistor is connected with the source electrode of the first NMOS tube, the second end of the fifth resistor is grounded, and the common mode output voltage is converted into the first current based on the fifth resistor;
and the drain electrode of the first NMOS tube is connected with the input end of the first current mirror.
4. A programmable gain amplifier according to claim 3, characterized in that: the first current mirror comprises a first PMOS tube and a second PMOS tube;
the source electrode of the first PMOS tube is connected with the working voltage, the drain electrode of the first PMOS tube is connected with the output end of the first voltage-current conversion unit, and the grid electrode of the first PMOS tube is connected with the drain electrode;
and the source electrode of the second PMOS tube is connected with the working voltage, the drain electrode of the second PMOS tube is connected with the output unit, and the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube.
5. The programmable gain amplifier of claim 4, wherein: the mirror factor of the first current mirror satisfies:
；
wherein K1 is the mirror factor of the first current mirror; r5 is the resistance value of the fifth resistor.
6. A programmable gain amplifier according to claim 2, characterized in that: the second voltage-current conversion unit comprises a second operational amplifier, a sixth resistor and a second NMOS tube;
the positive input end of the second operational amplifier is connected with the reverse input voltage of the operational amplifier, the reverse input end of the second operational amplifier is connected with the source electrode of the second NMOS tube, and the output end of the second operational amplifier is connected with the grid electrode of the second NMOS tube;
the first end of the sixth resistor is connected with the source electrode of the second NMOS tube, the second end of the sixth resistor is grounded, and the reverse input voltage is converted into the second current based on the sixth resistor;
and the drain electrode of the second NMOS tube is connected with the input end of the second current mirror.
7. The programmable gain amplifier of claim 6, wherein: the second current mirror comprises a third PMOS tube and a fourth PMOS tube;
the source electrode of the third PMOS tube is connected with the working voltage, the drain electrode of the third PMOS tube is connected with the output end of the second voltage-current conversion unit, and the grid electrode of the third PMOS tube is connected with the drain electrode;
and the source electrode of the fourth PMOS tube is connected with the working voltage, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the output unit.
8. The programmable gain amplifier of claim 7, wherein: the mirror factor of the second current mirror satisfies:
；
wherein K2 is the mirror factor of the second current mirror; r6 is the resistance value of the sixth resistor.
9. A programmable gain amplifier according to claim 2, characterized in that: the output unit comprises a third NMOS tube and a fourth NMOS tube;
the drain electrode of the third NMOS tube is connected with the output end of the second current mirror, the source electrode is grounded, and the grid electrode is connected with the source electrode;
the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the output end of the first current mirror and outputs the compensation current.
10. An analog-to-digital converter, the analog-to-digital converter comprising: a programmable gain amplifier as claimed in any one of claims 1 to 9.
11. A chip, the chip comprising: a programmable gain amplifier as claimed in any one of claims 1 to 9.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000001336A (en) * | 1998-06-10 | 2000-01-15 | 김영환 | Operation amplifier of fully differential structure |
| WO2005086957A2 (en) * | 2004-03-11 | 2005-09-22 | Gct Semiconductor, Inc. | Highly linear variable gain amplifier |
| WO2006127855A2 (en) * | 2005-05-24 | 2006-11-30 | Texas Instruments Incorporated | Fast setting, low noise, low offset operational amplifier and method |
| CN101373956A (en) * | 2008-09-17 | 2009-02-25 | 清华大学 | Method for compensating common mode feedback circuit frequency of two-stage amplifier |
| US7994865B1 (en) * | 2007-06-27 | 2011-08-09 | Marvell International Ltd. | Even order distortion cancellation in single-ended input, differential output amplifiers using feedback |
| CN104584425A (en) * | 2012-05-10 | 2015-04-29 | 塔特公司 | Programmable-gain amplifier |
| CN106100598A (en) * | 2016-05-31 | 2016-11-09 | 深圳市海思半导体有限公司 | A kind of variable gain amplifier |
| EP3627700A1 (en) * | 2018-09-24 | 2020-03-25 | Harman International Industries, Incorporated | Fully-differential programmable gain amplifier |
| CN113258896A (en) * | 2021-07-08 | 2021-08-13 | 芯海科技（深圳）股份有限公司 | Programmable gain amplifier, integrated circuit, electronic device and frequency correction method |
| CN115940852A (en) * | 2021-09-22 | 2023-04-07 | 深圳市中兴微电子技术有限公司 | Low-phase-shift variable gain amplifier and radio frequency signal processing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000003476A1 (en) * | 1998-07-13 | 2000-01-20 | Steensgaard Madsen Jesper | Wide-bandwidth operational amplifier |
| WO2009105696A1 (en) * | 2008-02-22 | 2009-08-27 | Keyeye Communications, Inc. | Feedback technique and filter and method |
-
2023
- 2023-06-16 CN CN202310713635.5A patent/CN116455335B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000001336A (en) * | 1998-06-10 | 2000-01-15 | 김영환 | Operation amplifier of fully differential structure |
| WO2005086957A2 (en) * | 2004-03-11 | 2005-09-22 | Gct Semiconductor, Inc. | Highly linear variable gain amplifier |
| WO2006127855A2 (en) * | 2005-05-24 | 2006-11-30 | Texas Instruments Incorporated | Fast setting, low noise, low offset operational amplifier and method |
| US7994865B1 (en) * | 2007-06-27 | 2011-08-09 | Marvell International Ltd. | Even order distortion cancellation in single-ended input, differential output amplifiers using feedback |
| CN101373956A (en) * | 2008-09-17 | 2009-02-25 | 清华大学 | Method for compensating common mode feedback circuit frequency of two-stage amplifier |
| CN104584425A (en) * | 2012-05-10 | 2015-04-29 | 塔特公司 | Programmable-gain amplifier |
| CN106100598A (en) * | 2016-05-31 | 2016-11-09 | 深圳市海思半导体有限公司 | A kind of variable gain amplifier |
| EP3627700A1 (en) * | 2018-09-24 | 2020-03-25 | Harman International Industries, Incorporated | Fully-differential programmable gain amplifier |
| CN113258896A (en) * | 2021-07-08 | 2021-08-13 | 芯海科技（深圳）股份有限公司 | Programmable gain amplifier, integrated circuit, electronic device and frequency correction method |
| CN115940852A (en) * | 2021-09-22 | 2023-04-07 | 深圳市中兴微电子技术有限公司 | Low-phase-shift variable gain amplifier and radio frequency signal processing method |
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