KR100275066B1 - Apparatus for processing digital data by using g.703 - Google Patents

Abstract

PURPOSE: A digital data processor according to G.703 is provided to extracting data from a G.703 bipolar input signal to a digital signal and vice versa according to the Recommendation G.703. CONSTITUTION: A clock generator(12) generates a clock for detecting data from a bipolar signal from an A/D(analog to digital) converter(11). A G.703 decoder(13) detects the bipolar signal according to the Recommendation G.073. A transmission FIFO(first-in, first-out)(60) temporarily stores and transmits the data. A clock smoothing filter(24) detects a generation clock from the digital data input. A reception FIFO(50) temporarily stores and transmits the digital data. A G.703 encoder(30) converts the data from the reception FIFO(50) to a bipolar signal and sends it to the A/D converter(11). A stuffing request signal generator(20) resolves disagreement of the clock of the clock generator(12) and a system clock.

Description

Digital data processing apparatus according to rat. 703. {APPARATUS FOR PROCESSING DIGITAL DATA BY USING G.703}

The present invention relates to a transmission apparatus using ITU-T Recommendation G.703, in particular extracting data from a received G.703 bipolar signal and converting it into a digital signal and conversely converting the digital signal according to the G.703 rule. A digital data processing apparatus for converting a bipolar signal.

Communication networks have steadily developed with digitalization. However, digital transmission has a disadvantage in that it takes more bandwidth per channel than analog transmission, and analog transmission is more economical even for long distance transmission. Despite these shortcomings, digital transmission has continued to evolve because it has many advantages.

The digital transmission signal is mainly TTL or CMOS. However, it is sometimes difficult to transmit at the digital level where the signal flow is between RACK and RACK, or TTL or CMOS. At this time, a method of converting a digital signal such as TTL or CMOS into a bipolar signal and converting the analog signal is transmitted. The same method is used for G.703 64Kb / s and 2.048Mb / s data transmission used in microwave (M / W) equipment.

Accordingly, an object of the present invention is to provide a digital data processing apparatus which extracts data from a received G.703 bipolar signal and converts the data into a digital signal and conversely converts the digital signal into a bipolar signal according to the G.703 rule.

In order to achieve the above object, the present invention receives a bipolar signal from the analog / digital conversion unit, digitally converted and transmitted, and receives the digital data converted into a bipolar signal to transmit through the digital / analog converter. A digital data processing apparatus according to 703, comprising: a clock reproducing unit for reproducing a clock for detecting data from the bipolar signal and a data reproduced from the bipolar signal by a rat.703 rule by using a clock reproduced by the clock reproducing unit. And a sender first-in, first-out unit for temporarily storing the data detected by the mouse.703 decoder and then reading the stored data to the system under the control of the system. A clock smoothing filter for detecting a reproduction clock from digital data, a reception first-in first unit for storing the digital data under the control of the system, and then reading the data using the reproduction clock; The data is converted into a bipolar signal using the reproduction clock and according to the mouse 703 rule. Sending parts of the rat D / A conversion. 703 encoder.

1 is a block diagram of a digital data processing apparatus according to an embodiment of the present invention.

2 is a transmission timing diagram based on the configuration of FIG. 1;

3 is a reception timing diagram based on the configuration of FIG. 1;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Although G.703 is used in various places, the present invention will be described by taking an example where it is applied to M / W equipment. Here, the M / W equipment has a hierarchical structure including a transceiver, an intermediate frequency unit, a modem unit, and a monitoring switching unit, and the digital data processing apparatus according to the present invention mainly uses 64Kb / s PCM (eg, telephone, FAX) standard. Applied to the supervisory switching section connected to an analog signal line (eg DS3 line).

1 is a block diagram of a digital data processing apparatus according to an embodiment of the present invention.

Referring to the drawings, reference numeral 11 is an analog / digital (hereinafter, referred to as "A / D") conversion unit, which is connected to an analog signal line, and receives the received analog signal by polarity by G.703. The branches are converted into digital signals TD + and TD- and output. 12 is a clock reproducing unit, and a clock for detecting data through the digital phase locked loop (D-PLL) from the digital signals TD + and TD- output from the A / D converter 11. Play it. 13 is a G.703 decoder, which uses the clock output from the clock reproducing section 12 to convert the digital signals TD + and TD- output from the A / D converter 11 according to the G.703 rule. Restore and send. In this case, the G.703 decoder 13 regards "1" when the digital signals TD + and TD- are "1100" and "0" when "1010" and transmits normal data. . If the detected data violates the G.703 rule, it is regarded as a line error bit, and counts this error bit to declare a line failure if it is over the threshold, and if the received signals are all "1", AIS is declared and sent to the control interface unit 14. 60 is a transmission first-in / first-out unit that latches transmission data synchronized with the transmission reproduction clock and reads and transmits the latched data with the system clock. The transmission first-in, first-out unit 60 will be described in more detail as follows. 15 is a transmission S / P (Serial / Parallel) conversion unit, which receives the serial data restored by the G.703 decoder 13, converts them in parallel, and sends them to the dual port S-RAM 19. 16 is a write write pointer, which receives the clock CLK generated from the clock reproducing unit 12 and outputs parallel data output from the transmitting S / P converter 15 to the dual port S-RAM 19. Save it. 18 is a transmission lead pointer, which receives a control signal from the multiplexer 21 and outputs parallel data stored in the dual port S-RAM 19 in parallel. 17 denotes a transmission P / S (Parallel / Serial) converter which converts parallel data output from the dual port S-RAM 19 into serial data STD and outputs the serial data.

20 is a STUFFING request signal generation unit. Since the clock of the transmission write pointer 16 and the clock of the transmission lead pointer 18 are mismatched in the transmission first-in first-out unit 19, stuffing is performed to solve this problem. The stuffing request signal generator 20 generates a positive stuffing request signal when the transmission read clock is slower than the transmission write clock, and conversely, a negative stuffing request signal when the transmission read clock is faster than the transmission write clock. Create Therefore, the multiplexer 21 receives the signal of the stuffing request signal generator to generate a signal for controlling the transmission lead pointer 18, and outputs the synchronized transmission data STD output from the first-in, first-out unit 60. Transfer to the next step.

50 is a reception first-in first-out unit, similarly to the transmission first-in first-out unit 60, receives and latches received data SRD synchronized with the system from the demultiplexer 23, and reads and transmits the latched data through the reproduction clock. . And the first-in, first-out unit 50 will be described in more detail as follows. Reference numeral 27 denotes a reception S / P converter which receives received data SRD, which is serial data, from the demultiplexer 23, converts it in parallel, and sends it to the dual port S-RAM 29. 25 denotes a receive write pointer, which receives a control signal from the demultiplexer 23 and stores the parallel received data SRD in the dual port S-RAM 29. 26 denotes a read lead pointer, receives a reproduction clock from a clock smoothing filter 24, reads data stored in the dual port S-RAM 29, and 28 denotes a receive P / S converter. The read parallel data is converted into serial and output.

In addition, the clock smearing filter 24 is designed using the D-PLL technique and generates clocks for reproducing the DS0 (DS1) signal. The clocks reproduced here are sent to the G.703 encoder 30. Then, the G.703 encoder 30 receives the reproduction clock from the clock smoothing filter 24, receives the data output from the reception first-in-first-out unit 50, encodes the data into a bipolar signal according to the G.703 rule, and then outputs the data. do. Then, the D / A converter 31 receives the received signal from the G.703 encoder 30, converts it into an analog signal, and sends the same to an analog signal line. In the G.703 encoder 30, a "1" signal is converted into a "1100" signal and a "0" signal is converted into a "1010" signal according to the G.703 rule. The signals are bipolar signals for D / A conversion. Is converted into the (RD +, RD-) form. In the coding rule, 1-7 bits apply AMI (Alternative Mark Inversion), and 8th bit uses a method of giving a vibration. This vibration is used to detect the frame in the G.703 decoder.

And 14 is a control interface, receives a control signal from the control unit 22 of the system, collects all the state information therein and transmits to the control unit 22. The control interface 14 includes the mouse .703 decoder 13, the mouse .703 encoder 30, the clock reproducing unit 12, the transmission first-in first-out unit 60, and the reception first-in first-out unit ( 50) and the clock smoothing filter 24. In this case, the control interface 14 receives a control signal by demultiplexing internally by receiving a multiplexed control signal with a data clock (DCLK), a byte clock (BCLK), and receiving a control signal. Multiplexing is performed using BCLK and then transmitted to the control unit 22. When the system is equipped with a monitor, the controller 22 receives the status information and displays it on the monitor. Administrators can then view this and check the status of the digital data processing unit.

FIG. 2 shows a transmission timing diagram based on the configuration of FIG. 1. SLOT Tx DATA in the figure shows the form of data in which one frame is composed of eight slots, and TD + and TD- are bipolar signals, which distinguish the frames through violation. The TCLK (Transmit Clock), the STDS (Tx Byte Time Slot), and the STBS (Tx Data Time Slot) are control signals input from the multiplexer 21. In particular, here, a frame of STD (Tx Data) data Control to lead.

3 illustrates a reception timing diagram based on the configuration of FIG. 1. Rx Data Time Slot (SRDS), Rx Byte Time Slot (SRBS), and RCLK (Receive Clock) are received from the demultiplexer 23, and the first-in-first-out unit 50 processes SRD (Rx Data). The signal is sent to the 703 encoder 30 to be converted into a bipolar signal composed of RD + and RD- and output.

As described above, the present invention can be used for data transmission according to the G.703 rule in all transmission devices including synchronous (SDH) and Plesio_chronous Digital Hierarchy (PDH). Off-line monitoring allows self-testing.

Claims (10)

A mouse that receives a bipolar signal from an analog / digital converter and converts it digitally and transmits it. In the digital data processing apparatus according to 703, A clock reproducing unit reproducing a clock for detecting data from the bipolar signal; A mouse.703 decoder which detects data from the bipolar signal according to a mouse.703 rule using a clock reproduced by the clock reproducing unit; A first-in, first-out unit that temporarily stores data detected by the mouse 703 decoder and reads the stored data to the system under the control of the system; A clock smoothing filter for detecting a reproduction clock from the digital data input from the system; A reception first-in, first-out unit for storing the digital data under the control of the system and reading the digital data using the reproduction clock; A mouse converting the data read out from the reception first-in-first-out part into the bipolar signal using the reproduction clock, and sending the data to the digital / analog converter in accordance with the .703 rule. 703 encoder, And a stuffing request signal generator configured to perform stuffing to solve a mismatch between a clock of the clock regenerator and a clock of the system. A mouse that receives a bipolar signal from an analog / digital converter and digitally converts it and transmits it, and receives digital data and converts it into a bipolar signal to transmit it through a digital / analog converter. In the digital data processing apparatus according to 703, A clock reproducing unit reproducing a clock for detecting data from the bipolar signal; A mouse.703 decoder which detects data from the bipolar signal according to a mouse.703 rule using a clock reproduced by the clock reproducing unit; A first-in, first-out unit that temporarily stores data detected by the mouse 703 decoder and reads the stored data to the system under the control of the system; A clock smoothing filter for detecting a reproduction clock from the digital data input from the system; A reception first-in, first-out unit for storing the digital data under the control of the system and reading the digital data using the reproduction clock; A mouse. 703 encoder, which converts the data read out from the reception first-in, first-out part into a bipolar signal according to the mouse .703 rule and sends the data to the digital / analog converter; The mouse.703 decoder, the mouse.703 encoder and the clock reproducing unit, the first-in first-out unit, the first-in first-out unit and the clock smoothing filter interface to perform a state information in the digital data processing apparatus. And a control interface unit configured to transmit the collected state information to a system control unit connected to the digital data processing unit. The transmission first-in first-out part according to claim 1 or 3, Storage means, A transmission serial / parallel converter configured to receive serial data from the mouse 703 decoder and convert the serial data into parallel data; A transmission write pointer for storing the parallel data in the storage means using a clock of the clock reproducing unit; A transmission lead pointer for reading data stored in the storage means under control of the system; And a transmission parallel / serial conversion unit converting the parallel data read from the storage unit into serial data and sending the same to the system. 4. The apparatus of claim 3, wherein said storage means is a dual port S-RAM. 5. Device according to claim 4, characterized in that the storage means is external. 5. An apparatus according to claim 4, wherein said storage means is incorporated. The first-in, first-out part according to claim 1 or 3, Storage means, A reception serial / parallel converter for receiving serial data from the system and converting the serial data into parallel data; A reception write pointer for storing the parallel data in the storage means under control of the system; A reception read pointer for reading data stored in the storage means using a reproduction clock of the clock smoothing filter; And a reception parallel / serial conversion unit for converting the parallel data read from the storage unit into serial data and sending the parallel data to the digital / analog conversion unit. 8. The apparatus of claim 7, wherein said storage means is a dual port S-RAM. 9. An apparatus according to claim 8, wherein said storage means is external. 9. An apparatus according to claim 8, wherein said storage means is incorporated.

Images