KR100273833B1 - A semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to be capable of improving the productivity of a crystal silicon thin film. CONSTITUTION: A semiconductor device includes a plurality of thin film transistors. At this time, the thin film transistor is provided with a glass substrate, a channel region having a crystal semiconductor layer formed on the glass substrate, and a source/drain region(212,213) formed at both sides of the channel region. At this time, the crystal semiconductor layer has a parallel axis for the surface of the glass substrate. The thin film transistor further includes a gate isolating layer near to the channel region, and a gate electrode(210) formed on the gate isolating layer. Preferably, a hydrogenation is carried out on the crystal semiconductor layer.

Description

Semiconductor device {A SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device having a crystalline semiconductor and a method of manufacturing the same. The present invention also relates to an electro-optical device such as an active matrix liquid crystal device using a semiconductor device.

Thin film transistors (hereinafter referred to as 'TFTs') are well known and widely used in various types of integrated circuits or electro-optical devices, and are particularly provided for each pixel of an active matrix (addressed to an active matrix) liquid crystal display device. It is not only used to switch devices but also to drive devices in its peripheral circuits.

An amorphous silicon film can be most easily used as a thin film semiconductor for TFTs. However, the electrical properties of the amorphous silicon film are disadvantageously not good. The problem can be solved by using a thin film of polysilicon (polycrystalline silicon) which is crystalline silicon. Crystalline silicon includes, for example, polycrystalline silicon, polysilicon and microcrystalline silicon. The crystalline silicon film can be produced by first forming an amorphous silicon film and then heat-treating to crystallize the resulting film.

The heat treatment for crystallizing the amorphous silicon film requires heating the film at a temperature of 600 ° C. or higher for at least 10 hours. This heat treatment adversely affects the glass substrate. CORNING, which is often used for substrates of active matrix liquid crystal display devices, for example. 7059 glass has a distortion point of 593 ° C and is not suitable for large area substrates that are heated above 600 ° C.

According to the inventor's study, the crystallization of the amorphous silicon film was found by heating the film at 550 ° C. for about 4 hours. This can be accomplished by depositing trace amounts of other elements such as nickel or palladium or lead on the surface of the amorphous silicon film.

The elements (hereinafter, 'catalytic elements' that can accelerate the crystallization of amorphous silicon films, also simply referred to as 'catalytic elements') are deposited by depositing elements by plasma treatment or deposition or by incorporating elements by ion implantation. It can be introduced to the surface of the qualitative silicon film. Plasma treatment is specifically a catalyst for an amorphous silicon film by generating a plasma in an atmosphere such as gas hydrogen or nitrogen using an electrode containing a catalyst element therein in a parallel plate or positive columnar plasma CVD apparatus. Consists of adding elements. However, it is undesirable to have a large amount of catalytic elements in the semiconductor. This is because using such a semiconductor greatly impairs the reliability and electrical stability of the device in which the semiconductor is used.

That is, the catalytic element is required for crystallization of the amorphous silicon film but is not preferably incorporated into the crystallized silicon. These conflicting requirements can be met by selecting elements which tend to be inert as catalytic elements in crystalline silicon and by incorporating the catalyst elements in a minimum amount that enables crystallization of the film. Therefore, the amount of catalytic element incorporated into the membrane must be controlled with high precision. The crystallization method using nickel etc. was studied in detail.

As a result, the following contents were found.

(1) When nickel was incorporated into the amorphous silicon film by the plasma treatment, it was found that nickel entered to a considerable depth of the amorphous silicon film before the film was heat treated.

(2) Initial nucleation occurs from the surface where nickel is incorporated.

(3) When the nickel layer is deposited on the amorphous silicon film The crystallization of the amorphous silicon film occurs in the same manner as in the case of performing a plasma treatment.

In view of the above, it can be assumed that not all nickel introduced into the plasma treatment acts to promote crystallization of silicon. In other words, when a large amount of nickel is introduced there is an excess of nickel that does not work effectively. For this reason, the inventors believe that it is the point or surface at which nickel contacts silicon, which serves to promote the crystallization of silicon at low temperatures. Furthermore, it is assumed that nickel must be dispersed in silicon in atomic form. That is, it is assumed that nickel needs to be dispersed in the atomic form near the surface of the amorphous silicon film and the concentration of nickel should be as small as possible but in a range high enough to promote low temperature crystallization. Trace amounts of nickel, i.e. catalytic elements capable of promoting the crystallization of amorphous silicon, may be incorporated near the surface of the amorphous silicon, for example by deposition. However, deposition is disadvantageous in terms of controllability of the film, and therefore is not suitable for precisely controlling the amount of catalytic element incorporated in the amorphous silicon film.

In view of the above situation, the present invention aims to produce a crystalline silicon semiconductor thin film with high productivity by heat treatment at a relatively low temperature using the catalyst element under conditions in which the amount of the catalyst element is precisely controlled and incorporated.

According to an aspect of the present invention, the above object is to provide to the amorphous silicon film a compound comprising a catalytic element for promoting crystallization of the amorphous silicon film or a catalytic element in contact with the amorphous silicon film, wherein the catalytic element or amorphous It can be achieved by heat treating the compound in contact with the silicon film to crystallize the silicon film.

Specifically, a solution containing a catalytic element in contact with an amorphous silicon film for introducing a catalytic element into the amorphous silicon film is provided.

Another feature of the present invention is to contact the silicon film with a solution containing a material selected from the group consisting of Ni, Pd, Pt, Cu, Ag, Au, In, Sn, Pd, Sn, P, As and Sb Is added to the silicon semiconductor film in a small amount, and then the silicon semiconductor film is crystallized by heating at a relatively low temperature. Using the silicon film thus formed, it is possible to form an active region including at least one electrical junction therein at the PN, PI or NI junction. Examples of semiconductor devices include thin film transistors (TFTs), diodes, and optical sensors.

1A to 1D are cross-sectional views for forming a crystalline silicon film according to the present invention.

2A to 2C are cross-sectional views showing the formation of a crystalline silicon film according to the present invention.

3 is a graph showing the relationship of the side growth length of a crystal to the concentration of nickel in a solution.

4 is a graph showing SIMS data for nickel in the silicon region where nickel is added directly.

FIG. 5 is a graph showing SIMS data for nickel in a silicon region in which crystal grows laterally from a region where nickel is directly added. FIG.

6A to 6E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

7 shows Ni concentration in a silicon film subjected to plasma treatment.

8 is a Raman spectral diagram of the region where nickel is added directly.

9 is a Raman spectral diagram of a region in which crystals grow laterally.

10A to 10F are cross-sectional views showing a method for manufacturing the electro-optical device according to the fourth embodiment of the present invention.

11A to 11D are sectional views showing the TFT manufacturing method according to the fifth embodiment of the present invention.

Fig. 12 is a schematic diagram of an active matrix type electro-optical device according to Embodiment 6 of the present invention.

13A and 13B are sectional views showing the formation of a crystalline silicon film according to Example 7 of the present invention.

14A to 14E are sectional views showing the manufacturing method of the TFT according to the eighth embodiment of the present invention.

15A and 15B are schematic diagrams showing an arrangement of an active layer of a TFT according to Embodiment 8 of the present invention.

Explanation of symbols on the main parts of the drawings

11 substrate 19 crystal grain

25 side growth area 61 substrate

2: driving area 63: pixel area

201: substrate 210: gate electrode

212 and 213 impurity regions 214 and 215 an intermediate layer insulating film

216: pixel electrode 217, 218: electrode / wiring

The above objects and features of the present invention will be described in detail with reference to the accompanying drawings.

The use of a solution to add nickel or the like according to the invention is advantageous in the following points:

(a) The concentration of the catalytic element (eg nickel) in the solution can be accurately adjusted in advance;

(b) the amount of catalytic element incorporated into the amorphous silicon film can be determined by the concentration of the catalytic element in the solution as long as the surface of the amorphous silicon film comes into contact with the solution;

(c) The catalytic element can be incorporated into amorphous silicon at the minimum concentration required for crystallization, since the catalytic element adsorbed on the surface of the amorphous silicon film mainly contributes to the crystallization of the film.

The words "comprising" or "containing" as used herein may be understood as (a) the catalyst element is simply dispersed in the solution or (b) the catalyst element is contained in the solution in the form of a compound. As the solution, various aqueous solutions and organic solvent solutions can be used. Solvents can be roughly classified into polar solvents and nonpolar solvents.

Water, alcohols, acids or ammonium can be used as polar solvents. Examples of suitable nickel compounds for polar solvents include nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, nickel formate, nickel acetyl acetonate, 4-cyclohexyl butyric acid, nickel oxide and Nickel hydroxide and the like.

In addition, benzene, toluene, xylene, carbon tetrachloride, chloroform, or ether may be used as the nonpolar solvent. Examples of suitable nickel compounds for nonpolar solvents are nickel acetyl acetonate and nickel 2-ethyl hexanoate.

Moreover, it is also possible to add surfactant to the solution containing the catalytic element. By doing so, the solution can stick and adsorb to the surface with higher efficiency. The surfactant may be coated on the surface to be coated prior to coating the solution.

In addition, when using elemental nickel (metal), it is necessary to dissolve it with an acid.

In the above example, nickel can be completely dissolved in a solvent. However, it is possible to use materials such as emulsions in which elemental nickel or nickel compounds are uniformly dispersed in the dispersion medium even if nickel is not completely dissolved. If a polar solvent such as water is used to dissolve nickel, the amorphous silicon film can repel such a solution. In such a case, it is preferable to form an oxide thin film on the amorphous silicon film so that the solution can be uniformly provided on the film. The thickness of the oxide film is preferably 100 Pa or less. In addition, surfactants may be added to the solution to increase the wetting properties.

In addition, rubbing treatment may be performed on the surface of the oxide thin film in order to impart irregularities having a uniform gap, width and direction to the surface. Such irregularities help the permeation of the solvent and increase the uniformity of the size and direction of the crystal grains. In addition, crystalline semiconductor films in which crystals are oriented in a particular direction are advantageously used in semiconductor devices to increase the uniformity of device characteristics.

In addition, when a nonpolar solvent such as toluene is used to prepare a 2-ethyl hexanoic acid nickel solution, the solution may be formed directly on the surface of the amorphous film. However, the amorphous silicon film and the solution contain a material for increasing the adsorption property between the amorphous silicon film and the solution, such as OAP (which contains hexamethyl disilazane as a main component of Tokyo Ogyo Co., Ltd.) used to increase the adsorption of the resist. You can also intervene.

The concentration of the catalytic element in the solution depends on the kind of the solution, but roughly speaking, the concentration of the catalytic element such as nickel in the solution is 1 ppm to 200 ppm by weight, preferably 1 ppm to 50 ppm, more preferably 10 ppm or less. The concentration is determined based on the nickel concentration in the silicon film or the resistance of the film to hydrofluoric acid upon completion of crystallization.

Crystal growth can be controlled by adding a solution containing catalytic elements to selected portions of the amorphous silicon film. In particular, crystals can be grown by heating the silicon film in a direction substantially parallel to the surface of the silicon film from the area where the solution is directly applied to the area where the solution is not applied.

It was confirmed that the side growth region contained a catalyst element at a low concentration. Although it is useful to use a crystalline silicon film as an active layer region for a semiconductor device, it is generally desirable that the concentration of impurities in the active region be as low as possible. Thus, the use of side growth regions for the active layer region is useful for device fabrication.

The use of nickel as catalytic element is particularly effective in the process according to the invention. However, other useful catalytic elements include nickel (Ni), palladium (pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), indium (In), tin (Sn), phosphorus ( P), arsenic (As) and antimony (Sb). Otherwise the catalytic element may be at least one selected from elements belonging to groups VIII, IIIb, IVb and Vb of the periodic table.

Example 1

This embodiment relates to a method of forming a crystalline silicon film on a glass substrate surface. 1A to 1D, a method of incorporating a catalytic element (nickel in this case) into an amorphous silicon film will be described later. CORNING 100mm x 100mm 7059 glass substrates are used.

An amorphous silicon film of 100 to 1500 mm thick is deposited by plasma CVD or LPCVD. Specifically, in this case, the amorphous silicon film 12 is deposited to a thickness of 1,000 mW by plasma CVD (FIG. 1A).

The amorphous silicon film is then treated with hydrofluoric acid if necessary to remove impurities and natural oxides formed thereon. After this treatment, an oxide film 13 is deposited on the amorphous silicon film to a thickness of 10 to 50 microns. Natural oxide film may be used as the oxide film. Since the film is extremely thin, the precise thickness of the oxide film 13 cannot be obtained. However, the natural oxide film can be estimated to have a thickness of about 20 kPa. The oxide film 13 is deposited by irradiating ultraviolet (UV) light for 5 minutes in an oxygen atmosphere. The oxide film 13 can also be formed by thermal oxidation. The oxide film may also be formed by treatment with aqueous hydrogen peroxide. The oxide film 13 is provided for the purpose of sufficiently spreading the acetate solution containing nickel to be added in the subsequent step to the entire surface of the amorphous silicon film. In short, the oxide film 13 is provided to improve the wettability of the amorphous silicon film. For example, when an aqueous solution of acetate is added directly, the amorphous silicon film repels the aqueous solution of acetate, preventing the uniform incorporation of nickel into the surface of the amorphous silicon film.

An aqueous solution of acetate containing nickel added thereto is then produced. Specifically, an aqueous solution of acetate containing nickel is prepared at a concentration of 10 to 200 ppm such as 100 ppm. Two milliliters of the acetate solution 14 is dropped onto the surface of the oxide film 13 on the amorphous silicon film 12 and held there for a predetermined time, preferably 0.5 minutes or more, for example 5 minutes. The spinner is then spin dried at 2,000 rpm for 60 minutes to remove unnecessary solution (Figures 1C and 1D).

The concentration of nickel in the acetate solution is actually at least 1 ppm, preferably at least 10 ppm. The solution need not be just an acetate solution and other available solutions include hydrochloride solution, nitrate solution and sulfate solution. Solutions of organic octylate and toluene can likewise be used. When the organic solution is used, the oxide film 13 does not need to be mixed because the solution can be directly added to the amorphous silicon film to introduce the catalytic element into the film.

Coating of the solution can be performed or repeated at one time so that a nickel-containing film can be uniformly formed on the surface of the amorphous silicon film 12 to a thickness of several angstroms to several hundred angstroms after spin drying. Nickel contained in this film will diffuse into the amorphous silicon film during the heating process carried out later and will serve to promote crystallization of the amorphous silicon film. However, it is the intention of the inventors that the film containing nickel or other material is not necessarily in the form of a completely continuous film, ie it may be discontinuous in the form of several clusters, for example.

The amorphous silicon film coated with one of the solutions is then held there for 5 minutes. The concentration of the nickel catalyst element in the crystallized silicon film 12 can be controlled by varying this holding time, but the most influential factor in controlling the final concentration of the nickel catalyst element in the crystallized silicon film 12 is that of the nickel catalyst element in solution. Concentration.

The silicon film coated with the nickel-containing solution thus obtained is heat-treated at a temperature of 550 ° C. for 4 hours in a nitrogen atmosphere in a heating furnace. In this way, a thin film of crystalline silicon 12 is formed on the substrate 11. The heat treatment may be performed at any temperature of 450 ° C. or higher. However, if the low temperature is selected, the heat treatment takes a lot of time and the production efficiency is reduced. On the other hand, the heat resistance of the glass substrate should be considered when selecting a heat treatment temperature of 550 ℃ or more.

Example 2

This embodiment relates to a method similar to that described in Example 1, except that a silicon oxide film of 1200 Å thickness is selectively provided for incorporating nickel into selected regions of the amorphous silicon film using the silicon oxide film as a mask.

2A to 2C, a method of manufacturing a semiconductor according to the present embodiment will be described below. The silicon oxide film is deposited on the amorphous silicon film 12 to a thickness of 1,000 mW or more, for example, 1,200 mW as a mask. However, if the film is sufficiently dense as a mask, the silicon oxide film 21 may be thinner than 1000 GPa, for example, 500 GPa. It is then patterned in a predetermined pattern using conventional photolithography techniques. The silicon oxide thin film 20 is formed by irradiating UV for 5 minutes in an oxygen atmosphere. The thickness of the silicon oxide film 20 is probably about 20 to 50 kPa (FIG. 2A). The action of the thus formed silicon oxide film to improve the wettability of the amorphous silicon film may sometimes be provided by the hydrophilicity of the silicon oxide film formed as a mask when the solution matches the size of the mask pattern. However, this is a special case and generally the silicon oxide film 20 is used stably.

Then, as in the method described in Example 1, an acetate solution 14 containing 100 ppm of nickel of 5 milliliters (for a 10 cm × 10 cm sized substrate) is dropped on the resulting structure surface. Spinner was used to spin coat at 50 rpm for 10 seconds to form a uniform aqueous film on the entire surface of the substrate. The state is then held for 5 minutes and the resulting structure is spin dried using a spinner at 2,000 rpm for 60 seconds. During the holding time, the substrate may be rotated on the spinner at a speed of 100 rpm or less (FIG. 2B).

Then, the amorphous silicon film 12 is crystallized by heat treatment at 550 ° C. for 4 hours in gaseous nitrogen. It can be seen that crystal growth proceeds laterally from the region 22 where nickel is introduced, to the region 25 where nickel is not introduced, as indicated by arrow 23.

In Fig. 2C, reference numeral 24 denotes a region where nickel is directly introduced to cause crystallization, and 25 denotes a region where crystallization proceeds laterally from the region 24. Transmission electron microscopy (TEM) and electron diffraction confirmed the following:

(a) Lateral grown crystals are cylindrical or needle-shaped single crystals of uniform width;

(b) the direction of growth of the crystal is almost parallel to the substrate surface although it depends on the film thickness;

(c) The direction of growth of the crystal is substantially in line with the [111] axis of the crystal.

From the above fact, the surface of the side growth region 25 has planes represented by {hk l} (h + k = l) (l is a lowercase letter l), such as {110}, {123}, {134 }, {235}, {145}, {156}, {257} or {167} or one of its neighboring planes.

It should be noted that since crystalline silicon has a diamond structure whose space group is Fd 3m, forbidden reflection occurs when the index hkl is even-odd mixture and it cannot be observed by electron diffraction.

FIG. 3 shows the relationship between the crystal growth distance (mu m) to the region 23 along the transverse (lateral) direction and the nickel concentration (ppm) in the aqueous acetate solution. 3 shows that crystal growth of a distance of 25 μm or more cannot be achieved by preparing a solution containing nickel at a concentration of 100 ppm or more. It can also be seen from Fig. 3 that crystal growth along the lateral direction of about 10 μm can be obtained using an aqueous acetate solution containing nickel at a concentration of 10 ppm.

The data shown in Figure 3 corresponds to the case where the structure was maintained for 5 minutes after the addition of an aqueous solution containing nickel. However, crystal growth along the lateral direction changes with retention time. For example, when using an aqueous solution of acetate containing nickel at a concentration of 100 ppm, longer crystal growth length can be obtained by increasing the holding time to 1 minute. However, if the holding time is specified to be more than 1 minute, further increase becomes meaningless.

When using an aqueous acetate solution containing nickel at a concentration of 50 ppm, the holding time increases in proportion to the distance of crystal growth along the transverse direction. However, as the holding time increases above 5 minutes, the increase becomes saturated.

It should also be noted that temperature greatly influences the time required for the reaction to equilibrate. Therefore, the holding time also depends on the temperature and strict control of the temperature is essential. Thus, the crystal growth distance can be collectively increased by raising the heat treatment temperature and extending the heat treatment duration.

4 and 5 show the nickel concentration in the silicon film obtained by introducing nickel using an aqueous solution of acetate containing 100 ppm of nickel and then heat treating the silicon film at 550 ° C. for 4 hours. Nickel concentrations are obtained by secondary ion mass spectroscopy (SIMS).

4 shows the nickel concentration in the region 24 shown in FIG. 2C, that is, the region in which nickel is directly mixed. FIG. 5 shows the nickel concentration of the region 25 shown in FIG. 2C, that is, the region in which crystal growth occurs laterally from the region 22.

Comparing the data of FIG. 4 with the data of FIG. 5, it can be seen that the nickel concentration in the region where crystal growth occurs along the lateral direction is about 1 digit lower than that in the region where nickel is directly introduced. .

It can be seen that the nickel concentration in the silicon film crystallized in the region where nickel is directly introduced can be lowered to the level of 10 ¹⁸ cm ^-3 by using an aqueous acetate solution containing nickel at a concentration of 10 ppm.

In conclusion, the nickel concentration in the crystalline silicon region where crystal growth occurs along the lateral direction is 10 ¹⁷ cm ^- by using an aqueous acetate solution containing nickel at a concentration of 10 ppm and heat-treating for a duration of 4 hours or more at 550 ° C or more. ^It can be seen that it can be lowered to ³ or less.

As a result, by adjusting the concentration and retention time of the solution, the nickel concentration in the region 24 of the silicon film to which nickel is directly added can be adjusted from 1 x 10 ¹⁶ atoms / cm ³ to 1 x 10 ¹⁹ atoms / cm ³ and more. Furthermore, it is also possible to keep the nickel concentration in the side growth region 25 below.

For comparison, instead of using a solution containing nickel, an amorphous silicon film is exposed (called plasma treatment) to the resulting plasma using an electrode containing a certain amount of nickel to add nickel to silicon (this is called plasma treatment). Samples are prepared by a method of crystallizing the silicon film by heat annealing at 550 ° C. for 4 hours. Plasma treatment conditions are selected so that the same degree of crystal growth can be obtained as when acetic acid containing 100 ppm of nickel is used. SIMS data for this sample is shown in FIG. As can be seen here, when plasma treatment is used, the nickel concentration in the side growth region is higher than 5 x 10 ¹⁸ atoms / cm ³ . Therefore, it can be seen that it is advantageous to use a solution in order to minimize the nickel concentration in the side growth region. FIG. 8 shows the results of using a Raman spectrometer for the region corresponding to FIG. 4, ie, the region into which nickel is directly introduced. 8 shows that the crystallinity in this region is very high. 9 also shows the results of the use of Raman spectroscopy for regions where crystals grow laterally. As can be seen, the Raman spectral intensity in the side growth region is more than 1/3 of that of single crystal silicon. Therefore, it can be said that the crystallinity in the side growth region is also high.

As such, the crystalline silicon film prepared by the method according to the present invention is characterized by excellent resistance to hydrofluoric acid. It is known to the inventors that the resistance of crystallized silicon to hydrofluoric acid is lowered when nickel is introduced by plasma treatment. Hydrofluoric acid is usually used as a caustic solution when it is necessary to pattern the silicon oxide film formed on the crystalline silicon film to form a contact hole therethrough. When the crystalline silicon film is sufficiently resistant to hydrofluoric acid, a large selection ratio (difference in etching rate between the silicon oxide film and the crystalline silicon film) may not be necessary to remove only the silicon oxide film. Therefore, the crystalline silicon film having high resistance to the attack of hydrofluoric acid is very advantageous in the semiconductor device manufacturing method.

Example 3

This embodiment relates to a method of manufacturing a TFT provided to each pixel of an active matrix liquid crystal display device using a crystalline silicon film produced by the method according to the present invention. The TFT thus obtained can be used for a wide range of fields commonly referred to as thin film integrated circuits (ICs) as well as liquid crystal display devices.

The TFT manufacturing method according to the present embodiment will be described below with reference to FIGS. 6A to 6E. A silicon oxide film (not shown) is deposited to a thickness of 2000 kPa as a base coating on a glass substrate. This silicon oxide film is provided to prevent the diffusion of impurities from the glass substrate into the device structure.

An amorphous silicon film is then deposited to a thickness of 1000 ns in a manner similar to that used in Example 1. After removing the native oxide film using hydrofluoric acid, an oxide film of the thin film is formed to a thickness of about 20 kPa by UV radiation under a gaseous oxygen atmosphere.

An amorphous silicon film having an oxide film thereon is coated with an aqueous acetate solution containing nickel at a concentration of 10 ppm.

As a result, the structure is maintained for 5 minutes and then spin-dried using a spinner. The silicon oxide film is then removed using dilute hydrofluoric acid, and the silicon film is crystallized by heating the resulting structure at 550 ° C. for 4 hours. The process up to this step is the same as described in Example 1.

The silicon film crystallized as above is patterned to form an island-like region 104 as shown in FIG. 6A. The island region 104 provides an active layer for a TFT. The silicon oxide film 105 is then formed to a thickness of 200 to 1500 Pa, for example 1000 Pa. This silicon oxide film acts as a gate insulating film (Fig. 6A).

The silicon oxide film 105 is deposited by RF plasma CVD using TEOS (tetraethoxysilane). That is, TEOS is deposited followed by oxygen at a substrate temperature in the range of 150 to 600 ° C., preferably 300 to 450 ° C. RF power of 100 to 250 W is applied while introducing TEOS and oxygen at a pressure ratio of 1: 1 to 1: 3 under a total pressure of 0.05 to 0.5 Torr. In addition, the silicon oxide film can be produced by low pressure CVD or normal pressure CVD using TEOS as a starting gas together with gaseous ozone while maintaining the substrate temperature in the range of 350 to 600 ° C, preferably 400 to 550 ° C. The film thus deposited is annealed for 30 to 60 minutes at a temperature of 400 to 600 ° C. in oxygen or under ozone.

Crystallization of the silicon region 104 can be accelerated by irradiating a laser beam or light of equivalent intensity with a KrF excimer laser (operating at a wavelength of 24 nm and a pulse width of 20 nsec). Application of RTA (Rapid Heat Annealing) using infrared rays is particularly effective because the silicon film can be selectively heated without heating the glass substrate. Moreover, RTA is very useful for the manufacture of insulated gate field effect semiconductor devices because it reduces the level of contact between the silicon layer and the silicon oxide film.

Next, an aluminum film is deposited to a thickness of 2000 k? To 1 [mu] m by electron beam evaporation to be patterned to form the gate electrode 106. The aluminum film may contain 0.15 to 0.2% by weight of scandium as a dopant. Subsequently, the substrate is immersed in an ethylene glycol solution containing a pH of about 7 and containing 1 to 3% of tartaric acid, and anodized using platinum as a cathode and an aluminum gate electrode as an anode. Anodic oxidation is achieved by first increasing the voltage to 220V at a constant rate and maintaining the voltage at 220V for 1 hour so that the oxidation is complete. When a constant current is applied as in the above case, the voltage is preferably increased at a rate of 2 to 5 v / min. The anodic oxide 109 is formed to a thickness of 1500 to 3500 kV, more specifically to 2000 kPa in the above manner (FIG. 6B).

An impurity (phosphorus in this case) is injected into the island-like silicon of the TFT in a self-aligning manner by ion doping (plasma doping) using the gate electrode portion as a mask. Phosphine (PH ₃ ) is used as the dopant gas to inject phosphorus at a dose of 1 × 10 ¹⁵ to 4 × 10 ¹⁵ cm ⁻² .

The crystallinity of the part having crystallinity damaged by the introduction of impurities is recovered by irradiating the laser beam using a KrF excimer laser operating at a wavelength of 248 nm and a pulse width of 20 nsec. The laser is operated at an energy density in the range of 150 to 400 mJ / cm 2, preferably 200 to 250 mJ / cm 2. Thus, an N-type impurity region (region doped with phosphorus) 108 is formed. It was found that the sheet resistance of this region was in the range of 200 to 800 Ω / square.

This step of laser annealing can be replaced by an RTA method using a flash lamp, i.e. a rapid thermal annealing method, which consists in rapidly raising the temperature of the silicon film in the range of 1000 to 1200 ° C (measured on a silicon monitor). have. The annealing method is also called RTP (Rapid Heat Treatment).

The silicon oxide film is then deposited to a thickness of 3000 kPa as the interlayer dielectric 110 by plasma CVD using TEOS with oxygen, or by low pressure CVD or normal pressure CVD using TEOS with ozone. The substrate temperature is maintained at, for example, 350 ° C. in the range of 250 to 450 ° C. The resultant silicon oxide film is then mechanically polished to obtain a smooth surface. The ITO coating is deposited thereon by sputtering and patterned to form the pixel electrode 111 (FIG. 6D).

The interlayer dielectric 110 is etched to form contact holes in the source / drain as shown in FIG. 6E, and the connections 112 and 113 are formed using chromium or titanium nitride to form the connection 113 as the pixel electrode 111. ).

In the process according to the invention, nickel is incorporated using an aqueous solution containing nickel at a low concentration of 10 ppm. Therefore, a silicon film having high resistance to hydrofluoric acid can be realized and the contact hole can be stably formed while having high replication property.

The silicon film is finally annealed in hydrogen in the temperature range of 300 to 400 ° C. for 0.1 to 2 hours to complete the hydrogen treatment of the silicon film to form a perfect TFT. A plurality of TFTs similar to those already described are manufactured at the same time and arranged in a matrix to form an active matrix liquid crystal display device.

According to this embodiment, the concentration of nickel contained in the active layer is 5 x 10 ¹⁶ to 3 x 10 ¹⁸ atoms / cm ³ .

As described above, the method according to the present embodiment includes crystallizing the portion where nickel is introduced. However, the method can be modified as in Example 2. That is, nickel can be incorporated into the selected portion through the mask and allow crystals to grow laterally from that portion. The region of crystal growth is used in the device. By lowering the active region nickel concentration of the device, it is possible to realize a better device in terms of electrical stability and reliability.

Example 4

This embodiment relates to TFT fabrication used to control the pixels of the active matrix. 10A to 10F are sectional views for explaining the manufacture of a TFT according to the present embodiment.

In Fig. 10A, a substrate 201, for example, a glass substrate, is cleaned and a silicon oxide film 202 is provided on the surface thereof. This silicon oxide film 202 is formed by plasma CVD with oxygen and tetraethoxy silane used as starting gas. The thickness of this film is, for example, 2000 mm 3. Next, an intrinsic amorphous silicon film 203 having a thickness of 500 to 1500 mW, such as 1000 mW, is formed on the silicon oxide film 202, and then 500 to 2000 mW of silicon oxide film 205 is continuously amorphous. It is formed on a silicon film.

Further, the silicon oxide film 205 is selectively etched to form an opening 206 to expose the amorphous silicon film. Next, the entire surface is coated in the same manner as described in Example 2 with a nickel-containing solution (acetate solution in this example). The nickel concentration in the acetate solution is 100 ppm. Other conditions are the same as in Example 2. In this way, the nickel-containing film 207 is formed.

The amorphous silicon film 203 provided in contact with the nickel containing film is crystallized by heat annealing at 500 to 620 ° C. for 4 hours in a nitrogen atmosphere. This crystallization starts in the region under the opening 206 where the silicon film is in direct contact with the nickel containing film and continues in a direction parallel to the substrate. In the figure, reference numeral 204 designates a portion of the silicon film in which nickel is directly added to the silicon film to crystallize, and 203 designates a portion in which the crystal grows laterally. Lateral grown crystals are about 25 μm. In addition, the direction of crystal growth is approximately parallel to the [111] axis.

After crystallization, the silicon oxide film 205 is removed. At this time, the oxide film formed on the silicon film in the opening 206 is simultaneously removed. In addition, the silicon film 204 is patterned by dry etching to form the active layer 208 in an island shape as shown in Fig. 10B. It should be noted that nickel is contained in the silicon film in a thicker concentration not only below the opening 206 to which nickel is directly added, but also in the portion where the top end of the crystal is present. The patterning of the silicon film should be performed such that the patterned silicon film 208 does not contain portions containing nickel at a higher concentration.

The patterned active layer 208 is then subjected to an atmosphere containing 100% water vapor of 10 atm at 500 to 600 ° C., typically 550 ° C., to oxidize its surface to form a 1000 Å silicon oxide film 209. Expose After oxidation, the substrate is maintained in an ammonium atmosphere (1 atm, 100%) at 400 ° C. In this state, the silicon oxide film 209 is irradiated with infrared rays having an intensity peak at a wavelength in the range of 0.6 to 4 mu m, for example, 0.8 to 1.4 mu m to nitride the silicon oxide film 209. HCl may be added 0.1 to 10% to the atmosphere. Halogen lamps are used as the source of infrared light. The intensity of infrared (IR) is adjusted so that the surface temperature of the single crystal silicon wafer being measured is set to 900 to 1200 ° C. More specifically, the temperature is measured by a thermocouple embedded in a single crystal silicon wafer and transferred to an infrared light source (feedback). In this embodiment, the rate of temperature rise is kept constant within the range of 50 to 200 ° C / sec and the substrate is naturally cooled to 20 to 100 ° C / sec. Infrared light can selectively heat the silicon film, thereby minimizing the heating of the glass substrate.

In Fig. 10C, the aluminum film is formed to a thickness of 3000 to 8000 Å, for example 6000 으로 by the sputtering method, and then patterned by the gate electrode 210. The aluminum film may preferably contain 0.01 to 0.2% of scandium.

In FIG. 10D, the surface of the aluminum electrode 210 is anodized in an ethylene glycol solution containing 1 to 5% tartaric acid to form an anodized film 211. The thickness of the oxide film 211 is 2000 GPa, and this thickness determines the size of the offset gate to be formed in a later step as described below.

In Fig. 10E, by using an ion doping method (also referred to as plasma doping method) such that an N-type conductive impurity (phosphorus in this embodiment) forms impurity regions 212 and 213 using a gate electrode and a peripheral anodization film as a mask. It is injected into the active layer in a self-aligning manner. Phosphine (pH ₃ ) is used as the dopant gas. The acceleration voltage is 60 to 90 kV, for example 80 kV. The dosage is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , such as 4 × 10 ¹⁵ cm ⁻² . As can be seen from the figure, the impurity regions 212 and 213 are separated by a distance 'X' from the gate electrode. This form is advantageous for reducing the leakage current (off current) that occurs when applying a reverse bias voltage (ie negative voltage in the case of NTFT). In particular, the offset state is particularly advantageous when the TFT is used to control the pixels of the active matrix as in the case of this embodiment, since it is desirable that the charge stored in the pixel electrode be kept without leakage to obtain a good display.

Then, annealing is performed by laser irradiation. KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) or other laser can be used as the laser. In the case of a KrF excimer laser, the conditions for laser irradiation are from 200 to 400 mJ / cm 2, such as 250 mJ / cm 2, and the number of spots is 2 to 10 spots, such as 2 spots, per place. The substrate is preferably heated to 200 to 450 ° C to improve the irradiation effect.

In Fig. 10F, an interlayer insulating film 214 of silicon oxide is formed to have a thickness of 6000 mV through plasma CVD. In addition, a transparent polyimide film 215 is formed by spin coating to obtain a slope. Next, a transparent conductive film made of, for example, indium tin oxide, is formed on the slope with a thickness of 800 kPa by sputtering and patterned with the pixel electrode 216.

Contact holes are provided in the interlayer insulating films 214 and 215, through which the electrodes / wiring 217 and 218 can reach the impurity region of the TFT. The electrodes / wirings 217 and 218 are formed of multiple layers of metal material, such as titanium nitride and aluminum.

Finally, annealing is carried out at 350 DEG C for 30 minutes in a hydrogen atmosphere of 1 atmosphere to complete the pixel circuit of the active matrix circuit having the TFTs.

Example 5

This embodiment relates to the fabrication of TFTs and will be described with reference to Figs. 11A to 11D. Elements that are the same as or similar to those of the preceding embodiments are given the same reference numerals for description.

In Fig. 11A, first, the base film 202 of silicon oxide is CORNING to 2000 mm thick by sputtering.^??7059 is formed on the substrate 201. The substrate is annealed at a temperature above the strain point of the substrate and then the glass is cooled to a temperature below the strain point at a rate of 0.1 to 1.0 ° C./min. This can reduce shrinkage of the substrate due to subsequent substrate heating (eg, thermal oxidation, open annealing), which will facilitate the mask alignment process. This step may be performed before or after the base film 201 or before and after the base film 201 is formed. CORNING In the case of using a 7059 substrate, the substrate can be heated at 620 to 660 ° C. for 1 to 4 hours, then cooled to 0.1 to 0.3 ° C./sec to furnace when the temperature is reduced to 400 to 500 ° C. Is taken out of.

Next, an intrinsic (I-type) amorphous silicon film is formed to a thickness of 500 to 1500 mW, for example 1000 mW through plasma CVD. The amorphous silicon film is crystallized in the same manner as in Example 1. Therefore, repetitive description is omitted. After crystallization, the silicon film is patterned into island shapes having a size of 10 to 1000 square microns. Thus, an island-shaped crystalline silicon film 208 is formed as an active layer of the TFT as shown in Fig. 11A.

In FIG. 11B, an oxide film 209 is formed by exposing and oxidizing the surface of the silicon film to an oxidation atmosphere. This oxidizing atmosphere contains 70 to 90% of water vapor. The pressure and temperature of this atmosphere are 1 atmosphere and 500-750 degreeC, typically 600 degreeC. This atmosphere is formed by an exothermic reaction from oxygen and hydrogen gas having a hydrogen / oxygen ratio of 1.5 to 1.9. The silicon film is exposed to the atmosphere thus formed for 3-5 hours. As a result, an oxide film 209 having a thickness of 500 to 1500 mV, for example 1000 mV, is formed. Since the surface of the silicon film is reduced (eroded) by 50 dB or more due to oxidation, the contamination effect of the top surface of the silicon film does not extend to the silicon-silicon oxide contact surface. In other words, a clean silicon-silicon oxide contact surface can be obtained by oxidation. In addition, since the thickness of the silicon oxide film is twice the thickness of the portion of the silicon film to be oxidized, when the silicon film is initially 1000 mm thick and the obtained silicon oxide film is 1000 mm, the thickness of the silicon film remaining after oxidation is 500 mm.

Usually, the thinner the silicon oxide film (gate insulating film) and the active layer, the higher the mobility and the smaller the off current. On the other hand, precrystallization of the amorphous silicon film is easier when the thickness thereof is thicker. Therefore, there was a contradiction in the electrical properties and the crystallization method with respect to the thickness of the active layer. This embodiment advantageously solves this problem. That is, an amorphous silicon film having a thicker thickness is formed first so that a good crystalline silicon film can be formed, and then the thickness of the silicon film is reduced by oxidation to improve the active layer characteristics of the TFT. Moreover, the amorphous components or grain boundaries contained in the crystalline silicon film tend to oxidize during thermal oxidation, reducing the recombination center contained in the active layer.

After the silicon oxide film 209 is formed through thermal oxidation, the substrate is annealed for 2 hours in a 100% monoside dinitrogen atmosphere at 1 atm.

In FIG. 11C, silicon containing 0.01-0.2% phosphorus is deposited to 3000-8000 microns, such as 6000 microns thick, via low pressure CVD and then patterned to form a gate electrode 210. Further, using this gate electrode 210 as a mask, N-type impurities are added into a portion of the active layer in a self-aligning manner by ion doping. Phosphine is used as the dopant gas. Doping conditions are substantially the same as in Example 4. Dosage is for example 5 × 10 ¹⁵ cm ⁻² . As a result, the N-type impurity regions 212 and 213 are formed.

Thereafter, annealing is performed with a KrF excimer laser in the same manner as in Example 4. Laser annealing may be replaced by lamp annealing with near infrared light. Near infrared rays are more effectively absorbed by crystalline silicon than amorphous silicon. Thus, annealing in the near infrared is comparable to thermal annealing at 1000 ° C or higher. On the other hand, it is possible to prevent the glass substrate from being heated so that the near infrared rays are not absorbed by the glass substrate. That is, although far infrared rays are absorbed by the glass substrate, visible or near infrared rays having a wavelength in the range of 0.5 to 5 mu m are not absorbed so much.

In Fig. 11D, an interlayer insulating film 214 of silicon oxide is formed to be 6000 탆 thick through plasma CVD. Polyimides may be used instead of silicon oxide. In addition, contact holes are formed through the insulating film. Electrodes / wiring 217 and 218 are formed through contact holes using multilayer titanium nitride and aluminum films. Finally, annealing in a hydrogen atmosphere is carried out at 350 ° C., 1 atmosphere for 30 minutes. This completes the TFT.

The mobility of the TFT thus formed is 110 to 150 cm 2 / Vs. S value is 0.2-0.5V / digit. In addition, when the P-channel type TFT is formed by doping boron into the source / drain region, the mobility is 90 to 120 cm 2 / Vs and the S value is 0.4 to 0.6 V / digit. Compared with the case where the gate insulating film is formed by conventional PVD or CVD, the mobility according to the present embodiment can be increased by 20% or more and the S value can be reduced by 20% or more.

In addition, the reliability of the TFT according to the present embodiment may be comparable to that of the TFT manufactured through thermal oxidation at a high temperature of about 1000 ° C.

Example 6

12 shows an example of an active matrix liquid crystal device according to the present embodiment.

In the figure, reference numeral 61 denotes a glass substrate, and 63 denotes a pixel region each having a plurality of pixels in the form of a matrix provided with TFTs as switching elements. Reference numeral 62 shows the peripheral drive region (s) in which the driving TFTs are provided to drive the TFTs of the pixel region. The pixel region 63 and the driving region 62 are integrated on the same substrate 61.

The TFTs installed in the drive region 62 need to have high mobility so that a large amount of current passes through them. In addition, the TFTs installed in the pixel region 63 need to have low leakage current characteristics to increase the charge holding capability of the pixel electrode. For example, TFTs manufactured according to Embodiment 3 are suitable as TFTs of the pixel region 63.

Example 7

This embodiment is a modified embodiment of the first embodiment. That is, before forming the nickel acetate aqueous solution, rubbing treatment is performed on the silicon oxide surface to form a large number of fine scratches, that is, scratch marks thereon.

13A, CORNING having a silicon oxide film as the base film 18 The 7059 substrate 11 is provided. This silicon oxide film is formed to a thickness of, for example, 2000 kPa by sputtering. On the silicon oxide film, an amorphous silicon film 12 is formed by plasma CVD to a thickness of 300 to 800 mW, for example, 500 mW. The surface of the amorphous silicon film is then treated with hydrofluoric acid to remove natural oxides or contaminants formed thereon. Thereafter, the surface of the substrate is exposed to ultraviolet light (not shown) in an oxygen atmosphere to form a silicon oxide film having a thickness of 10 to 100 Å. The oxidation may be carried out by hydrogen peroxide treatment or thermal oxidation.

Next, fine scratches as shown by reference numeral 17 are formed on the silicon oxide film by the polishing treatment. This polishing treatment is performed with diamond paste. However, cotton fabric or rubber may be used instead of diamond paste. The scratches preferably have a uniform direction, width and depth.

After the polishing treatment, a nickel acetate film was formed by spin coating in the same manner as in Example 1. The nickel acetate solution is uniformly adsorbed on the scratches.

Referring to FIG. 13B, the amorphous silicon film is annealed at 550 ° C. for 4 hours in a nitrogen atmosphere as in Example 1. As a result, a crystalline silicon film is formed. In the film thus formed, the size and orientation of the crystal grains 19 are more uniform than those obtained in Example 1. The crystal grains 19 extend in one direction and have a shape such as a substantially rectangular or elliptical shape.

The size or number of scratches can be adjusted by changing the density of the diamond paste. Since it is difficult to observe scratches under a microscope, the polishing conditions are determined so that the density or size of crystal grains of amorphous silicon remaining in the obtained crystalline silicon film can be maximized. In this embodiment, the conditions for polishing are selected so that the length of the amorphous region remaining after crystallization is 1 탆 or less, preferably 0.3 탆 or less.

In the case of Example 1 without performing the polishing treatment, there is a tendency that regions where nickel is not uniformly diffused and crystallized in a circle of 1 to 10 mu m are found. Therefore, the polishing treatment improves the uniformity of the crystal.

Example 8

This embodiment relates to a method of manufacturing a TFT for switching pixels of an active matrix according to the seventh embodiment. 14A to 14E are sectional views showing the manufacturing process.

In Fig. 14A, the silicon oxide film 202 is CORNING to a thickness of 3000 GPa by plasma CVD. It is formed on a substrate 201 (10 square cm) made of 7059 glass. Next, an amorphous silicon film 203 is formed on the silicon oxide film 202 to a thickness of 300 to 1000 mW, for example, 500 mW by plasma CVD.

The amorphous silicon film thus formed is crystallized by the method described in Example 7. After thermal crystallization, laser annealing is performed with a kr excimer laser (248 nm wavelength) having an energy density of 200 to 350 mJ / cm ² to improve crystallization. As a result, the amorphous component remaining in the crystalline silicon film was completely crystallized.

After crystallization, the silicon film 203 is patterned into an island-like silicon film 208 as shown in Fig. 14B. At this time, the position and orientation of the silicon islands with respect to the grain boundary may be selected in the manner shown in FIGS. 15A and 15B.

When the current of the TFT crosses the grain boundary, the grain boundary functions as a resistance. On the other hand, current easily flows along grain boundaries. Therefore, the electrical characteristics of the TFT are greatly influenced by the number and orientation of grains (grain boundaries) contained in the channel region. For example, if there are many TFTs there, the leakage current characteristic of each TFT changes depending on the number and orientation of crystal grains contained in the channel region.

This problem is severe when the grain size is approximately equal to or smaller than the size of the channel. When the channel is much larger than the grains, the dispersion is averaged and not found much.

For example, if there is no grain boundary in the channel, the TFT can be expected to have the same electrical properties as those of the single crystal TFT. On the other hand, if the grain boundary extends in the direction of the drain current through the island, the leakage current becomes larger. In contrast, if the grain boundary extends in the direction perpendicular to the direction of the drain current, the leak current becomes smaller.

When the TFTs are arranged so that the drain current flows in a direction parallel to the polishing direction, the number of grain boundaries contained in the channel becomes uneven because the crystals are increased in length along the polishing direction, and therefore the leakage current is likely to be dispersed. Moreover, the intensity of the leak current becomes larger because the grain boundary is aligned in the direction of the drain current as shown in Fig. 15A. On the other hand, as shown in Fig. 15B, if the drain current flows in the direction perpendicular to the polishing direction, the off current characteristic can be stabilized. This is because the width of the grains 19 is approximately uniform and the number of grains present in the channel region 26 can be constant. In conclusion, it is preferable to arrange the active region 208 such that the drain current of the TFT flows in the grain boundary direction, that is, the direction perpendicular to the polishing direction. Moreover, the polishing treatment makes the grain size uniform, so that the uncrystallized region can be crystallized epitaxially by the next laser irradiation.

As shown in Fig. 14B, a silicon oxide film having a thickness of 200-1500 Å, for example 1000 Å, is formed as the gate insulating film 209 through plasma CVD.

Next, aluminum containing 1% by weight of Si or 0.1 to 0.3% by weight of Sc is sputtered to 1000 m 3 to 3 m, for example 5000 m 3, and then patterned with the gate electrode 210. Next, an aluminum electrode is subjected to anodization using an ethylene glycol solution containing 1% to 3% tartaric acid. The pH of the electrolyte is about 7. The platinum electrode is used as the cathode while the aluminum electrode is used as the anode. The voltage is increased to a constant current until the voltage reaches 220V, and then maintained at this state for one hour. As a result, the anodic oxide film 211 is formed to a thickness of 1500 to 3500 mV, for example 2000 mV.

Referring to FIG. 14C, an impurity (boron) having one conductivity type is implanted into a silicon island by a self-aligning method using an ion doping method using the gate electrode 210 as a mask. Diborane (B ₂ H ₆ ) is used as the dopant gas. Dosage is 4-10 × 10 ¹⁵ cm ⁻² . The acceleration voltage is 65 kV. As a result, a pair of impurity regions (P-types) 212 and 213 were obtained.

Thereafter, the impurity regions 212 and 213 are activated by irradiating KrF excimer laser (wavelength 248 nm, pulse width 20 nsec). The energy density of this laser beam is 200 to 400 mJ / cm ² , preferably 250 to 300 mJ / cm ² .

Referring to FIG. 14D, an interlayer insulating film 214 made of silicon oxide is formed to have a thickness of 3000 μm through plasma CVD. Next, a contact hole is formed through the interlayer insulating film 214 and the gate insulating film 209 by etching on the impurity region 212 (source). Next, an aluminum film is formed by sputtering and then patterned to form a source electrode 217.

Referring to Fig. 14E, silicon nitride is deposited as a protective film 215 at 2000 to 6000 mV through plasma CVD. A contact hole is formed on the impurity region (drain) 213 through the protective film 215, the interlayer insulating film 214, and the gate insulating film 209 by etching. Finally, an indium tin oxide film ITO is formed as the pixel electrode 216. In this way, a pixel TFT was obtained.

Although the present invention has been disclosed in the preferred embodiments, it should be understood that the scope of the present invention is not limited to such specific embodiments, and various modifications may be made.

For example, a nickel containing film may be formed using anhydrous solutions, such as alcohol. When using alcohol, the solution can be formed directly on the amorphous silicon film without using an oxide film. In particular, nickel containing compounds such as nickel acetyl acetonate can be dissolved in ethanol. The material can decompose during heating for crystallization because its decomposition temperature is relatively low. The amount of nickel acetyl acetonate is selected so that the nickel concentration in the solution is 100 ppm. After coating the solution, the nickel-containing film can be obtained by drying by spin drying at 1500 rpm for 1 minute. In addition, since the contact angle of alcohol is smaller than that of water, the amount of solution used to form the membrane may be less than when an aqueous solution is used. In this case, 2 ml is appropriate for 100 square mm. The following processes for forming crystalline silicon may be entirely the same as those described in the above preferred embodiment.

In another embodiment, elemental nickel can be dissolved by acid. That is, 0.1 mol / l nitric acid is used as the acid. Nickel powder is dissolved in 50 ppm of the acid.

Claims (26)

A semiconductor device having one or more thin film transistors, The thin film transistor, Glass substrate, A channel region including a crystalline semiconductor layer having silicon formed on the glass substrate; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; And the crystal semiconductor layer has an axis parallel to the surface of the glass substrate. The method of claim 1, The crystalline semiconductor layer is hydrogenated. The method of claim 1, And the crystalline semiconductor layer comprises a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 3, wherein The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. A semiconductor device having one or more thin film transistors, The thin film transistor, Glass substrate, A channel region including a crystalline semiconductor layer having silicon formed on the glass substrate; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; The surface of the crystalline semiconductor layer has at least one of {110}, {123}, {134}, {235}, {145}, {156}, {257} and {167} planes, but the {111} plane It does not have a semiconductor device characterized by the above-mentioned. The method of claim 5, The crystalline semiconductor layer is hydrogenated. The method of claim 5, And the crystalline semiconductor layer comprises a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 7, wherein The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. A semiconductor device having one or more thin film transistors, The thin film transistor, Glass substrate, A channel region including a crystalline semiconductor layer having silicon formed on the glass substrate; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; A surface of the crystalline semiconductor layer has a {110} plane but no {111} plane. The method of claim 9, And the crystalline semiconductor layer comprises a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 9, The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. A semiconductor device having one or more thin film transistors, The thin film transistor, A channel region having a plurality of silicon crystals formed on the insulating surface; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; Wherein each silicon crystal has a [111] axis parallel to the insulating surface. The method of claim 12, And the channel region is hydrogenated. The method of claim 12, And the channel region includes a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 14, The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. The method of claim 12, And the channel region is formed on a glass substrate. A semiconductor device having one or more thin film transistors, The thin film transistor, A channel region having a plurality of silicon crystals formed on the insulating surface; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; Each of the silicon crystals has at least one of {110}, {123}, {134}, {235}, {145}, {156}, {257} and {167} faces but no {111} faces. Characterized in that the semiconductor device. The method of claim 17, The crystalline semiconductor layer is hydrogenated. The method of claim 17, And the channel region includes a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 19, The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. The method of claim 17, And the channel region is formed on a glass substrate. A semiconductor device having one or more thin film transistors, The thin film transistor, A channel region having a plurality of silicon crystals formed on the insulating surface; Source and drain regions having channel regions sandwiched between them, A gate insulating film adjacent to the channel region; A gate electrode adjacent the gate insulating film; Wherein each of the silicon crystals has a {110} plane but no {111} plane. The method of claim 22, And the channel region includes a catalytic element for promoting crystallization at a concentration of 1 × 10 ¹⁹ atoms / cm 3 or less. The method of claim 23, wherein The catalyst element is selected from the group consisting of nickel, palladium, platinum, copper, silver, gold, indium, tin, phosphorus, arsenic and antimony. The method of claim 22, And the channel region comprises hydrogen. The method of claim 22, And the channel region is formed on a glass substrate.