KR100271757B1 - Etching method - Google Patents
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- KR100271757B1 KR100271757B1 KR1019970017066A KR19970017066A KR100271757B1 KR 100271757 B1 KR100271757 B1 KR 100271757B1 KR 1019970017066 A KR1019970017066 A KR 1019970017066A KR 19970017066 A KR19970017066 A KR 19970017066A KR 100271757 B1 KR100271757 B1 KR 100271757B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Abstract
Description
본 발명은 반도체장치의 식각방법에 관한 것으로서, 보다 상세하게는 크롬막의 식각시 소정의 시간 동안 방치시킨 후, 식각공정을 수행함으로써 불량을 제거시키고, 또한 공정시간(EPD : End Point Detect)을 단축시킨 반도체장치의 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method of a semiconductor device, and more particularly, to allow defects to be removed by performing an etching process after being left for a predetermined time during etching of a chromium film, and further shortening an end point detect (EPD). The etching method of the semiconductor device.
일반적으로 반도체장치의 제조에서는 사진공정의 수행으로 패턴(Pattern) 영역을 형성시킨 후, 상기 패턴 영역의 임의의 박막(Thin Film)을 식각하는 식각공정을 수행하여 소자의 특성에 따른 패턴을 형성시킨다.In general, in the manufacture of a semiconductor device, after forming a pattern region by performing a photo process, an etching process of etching an arbitrary thin film of the pattern region is performed to form a pattern according to the characteristics of the device. .
그리고 상기 패턴을 형성시키기 위한 식각공정은 식각하고자 하는 임의의 박막의 종류에 따라 식각방법, 공정조건 등을 달리하여 공정을 수행한다.The etching process for forming the pattern may be performed by varying an etching method, process conditions, etc. according to any kind of thin film to be etched.
이러한 패턴의 형성을 위한 식각공정 중에서 반도체 기판 상에 크롬막(Cr Film) 및 그 상부에 알루미늄(Al)과 네오디뮴(Nd)이 혼합된 합금막이 순차적으로 형성된 영역을 게이트 패턴(Gate Pattern)으로 형성시키기 위하여 기존에는 먼저, 사진공정을 수행하여 패턴 영역을 형성시킨 후, 상기 패턴 영역의 상기 합금막 및 크롬막을 순차적으로 식각시키고, 상기 사진공정의 수행으로 반도체 기판 상에 잔류하는 포토레지스트(Photo Resist)를 제거하는 공정을 수행하여 게이트 패턴을 형성시켰으나, 최근에는 사진공정의 수행으로 패턴 영역을 형성시킨 후, 상기 패턴 영역의 상기 합금막을 식각시키고, 상기 사진공정의 수행으로 반도체 기판 상에 잔류하는 포토레지스트를 제거시켰다.In the etching process for forming the pattern, a region in which a chromium film and an alloy film in which aluminum (Al) and neodymium (Nd) are mixed are sequentially formed on a semiconductor substrate is formed as a gate pattern. Conventionally, first, a photo process is performed to form a pattern region, and then the alloy layer and the chromium layer of the pattern region are sequentially etched, and the photoresist remaining on the semiconductor substrate is performed by performing the photo process. ) To form a gate pattern, but recently, after forming a pattern region by performing a photo process, the alloy film of the pattern region is etched and remaining on the semiconductor substrate by performing the photo process. The photoresist was removed.
그리고 상기 패턴 영역, 즉 상기 합금막이 식각된 영역의 크롬막을 식각시켜 게이트 패턴을 형성시켰다.The chromium layer of the pattern region, that is, the region where the alloy layer is etched, was etched to form a gate pattern.
여기서 상기 크롬막의 식각은 25℃의 온도분위기로 습식각(Wetting) 및 식각액의 분무(Spray)를 순차적으로 수행한 후, 분당 10회 정도의 교반(Agitation)을 수행하였다.Here, the etching of the chromium film was performed by sequentially performing wet etching and spraying of the etchant at a temperature atmosphere of 25 ° C., and then agitation was performed about 10 times per minute.
그러나 상기 패턴 형성을 위한 최근의 공정에서는 포토레지스트의 제거시 유기물이 완전히 제거되지 않고 얇은 피막형태로 상기 크롬막 등에 잔류하여 상기 크롬막의 식각을 방해하였다.However, in the recent process for forming the pattern, the organic material is not completely removed when the photoresist is removed, but remains in the chromium film in the form of a thin film to prevent etching of the chromium film.
이에 따라 상기 크롬막을 식각시키는 크롬 식각액의 온도를 높이거나 또는 식각속도를 증가시켜 공정을 수행하였으나, 미세한 패턴 영역에서는 부분적으로 크롬막의 식각이 잘 되지 않았다.Accordingly, the process was performed by increasing the temperature or increasing the etching rate of the chromium etching solution for etching the chromium film, but the etching of the chromium film was not well performed in the fine pattern region.
또한 상기 크롬막을 식각시키는 공정시간이 300초 이상 소요됨으로 인하여 양산에 적용하기에는 어려운 실정이었다.In addition, since the process time of etching the chromium film takes 300 seconds or more, it is difficult to apply to mass production.
따라서 종래의 게이트 패턴을 형성시키기 위하여 수행되는 크롬막의 식각은 상기 크롬막이 식각되지 않아 불량이 발생하였고, 또한 공정이 오랜 시간으로 수행되는 등으로 인하여 생산성이 저하되는 문제점이 있었다.Therefore, the etching of the chromium film that is performed to form a conventional gate pattern has a problem that the chromium film is not etched, so that a defect occurs, and there is a problem that productivity is lowered due to the process being performed for a long time.
본 발명의 목적은, 크롬막의 식각시 불량을 제거하고, 또한 공정시간을 단축시켜 생산성을 향상시키기 위한 반도체장치의 식각방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an etching method of a semiconductor device for removing defects during etching of a chromium film and shortening the process time to improve productivity.
도1은 본 발명에 따른 반도체장치의 식각방법의 일 실시예를 나타내는 공정도이다.1 is a process diagram showing an embodiment of an etching method of a semiconductor device according to the present invention.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 식각방법은, 반도체 기판 상에 크롬막 및 합금막이 순차적으로 기 형성된 영역을 게이트 패턴으로 형성시키기 위한 반도체장치의 식각방법에 있어서, (1) 사진공정의 수행으로 상기 게이트 영역의 포토레지스트를 제거시키는 사진공정단계; (2) 상기 (1)의 사진공정단계의 수행으로 노출되는 상기 게이트 영역의 합금막을 식각시키는 제 1 식각단계; (3) 상기 (1)의 사진공정단계의 수행으로 상기 반도체 기판 상에 잔류하는 포토레지스트를 완전히 제거하는 제거단계; 및 (4) 상기 (3)의 제거단계의 수행으로 포토레지스트가 제거된 반도체 기판 상의 크롬막 영역에 크롬 식각액을 점적시켜 소정의 시간 동안 방치시킨 후, 상기 크롬막을 식각시키는 제 2 식각단계를 구비하여 이루어짐을 특징으로 한다.The etching method of the semiconductor device according to the present invention for achieving the above object, in the etching method of the semiconductor device for forming a region in which the chromium film and the alloy film is previously formed on the semiconductor substrate in sequence as a gate pattern, (1) photo Performing a process to remove the photoresist of the gate region; (2) a first etching step of etching the alloy film of the gate region exposed by performing the photo process step of (1); (3) a removal step of completely removing the photoresist remaining on the semiconductor substrate by performing the photoprocessing step of (1); And (4) a second etching step of dropping the chromium etchant into the chromium film region on the semiconductor substrate from which the photoresist has been removed by performing the removing step (3) and leaving it for a predetermined time and then etching the chromium film. Characterized in that made.
상기 합금막은 알루미늄 및 네오디뮴으로 이루어지는 것이 바람직하다.Preferably, the alloy film is made of aluminum and neodymium.
상기 소정의 시간 동안 방치된 반도체 기판의 상기 크롬막의 식각은 크롬 식각액을 상기 반도체 기판 상에 분무 또는 침적시키는 것이 바람직하다.In the etching of the chromium film of the semiconductor substrate left for the predetermined time, it is preferable to spray or deposit the chromium etchant on the semiconductor substrate.
상기 크롬 식각액을 점적시켜 방치시키는 소정의 시간은 30초 내지 70초 정도의 시간으로 이루어지는 것이 바람직히다.It is preferable that the predetermined time for allowing the chromium etchant to drip and leave is about 30 seconds to about 70 seconds.
상기 (4)의 제 2 식각단계는 25℃ 내지 35℃의 온도분위기로 45초 내지 55초 정도의 시간으로 수행하거나, 20℃ 내지 25℃의 온도분위기로 55초 내지 60초 정도의 시간으로 수행하거나 또는 15℃ 내지 20℃의 온도분위기로 60초 내지 70초 정도의 시간으로 수행하는 것이 바람직하다.The second etching step (4) is performed at a temperature of about 45 seconds to about 55 seconds at a temperature of 25 ° C to 35 ° C, or about 55 seconds to about 60 seconds at a temperature of 20 ° C to 25 ° C. Or at a temperature of about 15 ° C. to 20 ° C. for 60 seconds to 70 seconds.
상기 (1), (2), (3) 및 (4)의 수행으로 형성되는 게이트 패턴은 액정표시장치를 제조하는 소자에 포함되는 것이 바람직하다.It is preferable that the gate pattern formed by performing the above (1), (2), (3) and (4) is included in a device for manufacturing a liquid crystal display device.
이하, 본 발명의 구체적인 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도1은 본 발명에 따른 반도체장치의 식각방법의 일 실시예를 나타내는 공정도이다.1 is a process diagram showing an embodiment of an etching method of a semiconductor device according to the present invention.
먼저, 상기 게이트 패턴 영역을 형성시키는 사진공정단계, 상기 사진공정으로 형성되는 게이트 패턴 영역의 상기 합금막을 식각시키는 제 1 식각단계, 상기 사진공정의 수행으로 반도체 기판 상에 잔류하는 포토레지스트를 제거하는 제거단계 및 상기 합금막이 식각된 게이트 영역의 크롬막을 식각시키는 제 2 식각단계로 이루어진다.First, a photo process step of forming the gate pattern region, a first etching process of etching the alloy film of the gate pattern region formed by the photo process, removing the photoresist remaining on the semiconductor substrate by performing the photo process The removal step and the second etching step of etching the chromium film of the gate region where the alloy film is etched.
여기서 상기 제 2 식각단계에서는 포토레지스트가 완전히 제거된 상기 반도체 기판 상의 크롬막 영역에 크롬 식각액을 점적시켜 소정의 시간 동안 방치시킨 후, 상기 크롬막을 식각시키는 식각공정을 수행한다.In the second etching step, a chromium etchant is dropped in a chromium film region on the semiconductor substrate from which the photoresist is completely removed, and left for a predetermined time, followed by an etching process of etching the chromium film.
그리고 본 발명의 상기 제 2 식각단계인 크롬막의 식각은 크롬 식각액을 반도체 기판 상에 분무시키거나, 또는 침적(Dipping)시켜 공정을 수행할 수 있고, 실시예에서는 크롬 식각액의 분무를 이용한다.The etching of the chromium film, which is the second etching step of the present invention, may be performed by spraying or dipping the chromium etchant onto the semiconductor substrate, and in this embodiment, spraying of the chromium etchant is used.
또한 본 발명에서 크롬 식각액을 점적시켜 방치시키는 소정의 시간은 30초 내지 70초 정도의 시간으로 이루어질 수 있고, 실시예에서는 40초 동안 방치시킨다.In addition, in the present invention, a predetermined time for dripping the chromium etchant may be made to a time of about 30 seconds to about 70 seconds.
그리고 본 발명의 크롬막의 식각은 각각의 온도에 따라 그 공정시간을 달리하여 공정을 수행할 수 있는데, 25℃ 내지 35℃ 정도의 온도분위기로 45초 내지 55초의 정도의 시간, 20℃ 내지 25℃ 정도의 온도분위기로 55초 내지 60초 정도의 시간 또는 15℃ 내지 20℃의 온도분위기로 60초 내지 70초 정도의 시간으로 공정을 수행한다.And the etching of the chromium film of the present invention can be carried out by varying the process time according to each temperature, the temperature of 25 ℃ to 35 ℃ about 45 seconds to 55 seconds time, 20 ℃ to 25 ℃ The process is carried out at a temperature atmosphere of about 55 seconds to 60 seconds or at a temperature of 15 ° C. to 20 ° C. for about 60 seconds to 70 seconds.
여기서 실시예는 30℃의 온도분위기로 50초 동안 공정을 수행하여 상기 크롬막을 식각시킨다.In this embodiment, the chromium film is etched by performing the process for 50 seconds at a temperature of 30 ° C.
그리고 상기 합금막은 알루미늄 및 네오디뮴으로 이루어진다.The alloy film is made of aluminum and neodymium.
이러한 상기 공정의 수행으로 형성되는 게이트 패턴은 액정표시장치(LCD : Liquid Crystal Display)에 내재되는 소자에 포함된다.The gate pattern formed by performing the above process is included in a device inherent in a liquid crystal display (LCD).
전술한 구성으로 이루어지는 본 발명의 구체적인 실시예의 작용 및 효과에 대하여 설명한다.The operation and effect of the specific embodiment of the present invention having the above-described configuration will be described.
본 발명은 액정표시장치에 내재되는 반도체 기판 상에 크롬막 및 알루미늄과 네오디뮴이 혼합된 합금막이 순차적으로 형성된 영역을 게이트 패턴으로 형성시키기 위하여 먼저, 사진공정을 수행하여 소정의 영역 즉, 게이트 패턴 영역의 포토레지스트를 제거시킨다.According to the present invention, in order to form a gate pattern, a region in which a chromium film and an alloy film in which aluminum and neodymium are mixed are sequentially formed on a semiconductor substrate inherent to a liquid crystal display device is first performed by performing a photo process. Remove the photoresist.
그리고 상기 사진공정을 수행하여 포토레지스트의 제거로 노출되는 게이트 패턴 영역의 합금막을 식각시킨다.The alloying process of the gate pattern region exposed by removing the photoresist is etched by performing the photolithography process.
계속해서 상기 사진공정의 수행으로 반도체 기판 상에 잔류하는 포토레지스트를 제거시킨다.Subsequently, the photoresist remaining on the semiconductor substrate is removed by performing the photographing process.
그리고 상기 포토레지스트가 제거된 반도체 기판 상의 크롬막 영역 즉, 게이트 패턴이 형성되는 영역에 크롬 식각액을 점적시키고, 상기 크롬 식각액이 점적된 반도체 기판을 40초 동안 방치시킨 후, 식각공정을 수행한다.After the chromium etchant is dropped into the chromium film region, that is, the region where the gate pattern is formed, on the semiconductor substrate from which the photoresist is removed, the semiconductor substrate on which the chromium etchant is deposited is left for 40 seconds and then the etching process is performed.
여기서 상기 식각공정은 반도체 기판 상에 크롬 식각액을 분무시켜 수행된다.The etching process is performed by spraying a chromium etching solution on a semiconductor substrate.
그리고 본 발명의 상기 식각공정은 30℃의 온도분위기로 50초 동안 수행되고, 이에 따라 상기 크롬 식각액의 분무는 10초 동안 수행된다.And the etching process of the present invention is performed for 50 seconds at a temperature atmosphere of 30 ℃, accordingly, the spray of the chromium etchant is carried out for 10 seconds.
이러한 구성의 본 발명은 크롬 식각액을 점적시켜 소정의 시간 동안 방치시킨 후, 식각공정을 수행함으로써 포토레지스트의 유기물에 의한 영향을 받지 않아 미세한 패턴 영역에서도 용이하게 식각이 이루어지고, 또한 식각공정의 공정시간이 단축된다.In the present invention having such a configuration, the chromium etchant is dropped and left for a predetermined time, and then the etching process is performed so that the etching is easily performed even in a fine pattern region without being affected by the organic material of the photoresist. The time is shortened.
따라서, 본 발명에 의하면 크롬막 식각이 용이하게 수행되고, 공정시간이 단축되어 생산성이 향상되는 효과가 있다.Therefore, according to the present invention, the chromium film is easily etched and the process time is shortened, thereby improving productivity.
이상에서 본 발명은 기재된 구체예에 대해서만 상세히 설명되었지만 본 발명의 기술사상 범위 내에서 다양한 변형 및 수정이 가능함은 당업자에게 있어서 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허청구범위에 속함은 당연한 것이다.Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical scope of the present invention, and such modifications and modifications are within the scope of the appended claims.
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