KR100269295B1 - Data input/output buffer - Google Patents

Abstract

PURPOSE: A data input/output mask buffer is provided to reduce the power consumption by preventing unnecessary current from flowing in a standby mode. CONSTITUTION: A sensing unit(203) senses a level of an external input signal to response to the sensed level. A MOS transistor(205) controls the connection between a power source of the sensing unit(203) and an external power terminal, in response to a control signal. An adjusting unit(207) generates the control signal having two logic state in a standby mode, wherein one logic state represents that a CAS latency is "1" and the other logic state indicates that the CAS latency is "over2". The CAS latency of "1" enables a data input/output mask buffer while the CAS latency of "over2" disables the buffer.

Description

Data input / output mask (DQM) buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a buffer of a data input / output mask (DATA INPUT / OUTPUT MASK, hereinafter referred to as DQM) for reducing current consumption in a standby state.

Since the development of semiconductor memory devices, the goal of memory chip designers is to design semiconductor memory chips with high integration and high speed operation. Indeed, there have been significant advances in terms of density and speed of operation. Currently, the clock used by the computer controller is extended to not only the CPU but also the semiconductor memory device, thereby further improving the performance of the semiconductor memory device. The semiconductor memory device operating in synchronization with an external system clock as described above is referred to as a synchronous DRAM (hereinafter referred to as a synchronous DRAM).

In addition, the reduction of power consumption in the memory chip along with the high speed and high integration of the semiconductor memory device becomes an important factor in terms of improving the performance of the chip. In DRAM, the buffer using the differential amplifier (DIFFERENTIAL AMPLIFIER) takes up a large portion of the power consumption of the chip, so minimizing the power consumption of the buffer can greatly contribute to minimizing the power consumption of the memory chip.

1 is a view showing a DQM buffer of the prior art. Referring to this, the DQMC of FIG. 1 is a DQM control signal enabled to "high" when the refresh operation or the clock enable signal CKE is "low". The prior art DQM buffer only controls the operation of the DQMC, and there is no information indicating the standby state of the DQM buffer when the chip is in the standby state. Thus, prior art DQM buffers are intended to operate in both active and standby states. Therefore, the conventional DQM buffer has a problem that unnecessary DC current flows through the DQM buffer stage even in a standby state in which the operation of the DQM buffer is not required.

An object of the present invention for solving the above problems of the present invention is to provide a data input / output mask (DQM) buffer to reduce the power consumption by preventing unnecessary current flowing in the standby state.

1 is a view showing a DQM buffer of the prior art.

2 illustrates a DQM buffer according to an embodiment of the present invention.

3 is a timing diagram of a main signal when the CAS latency LATENCY is "1".

In order to achieve the above object, the data input / output mask buffer of the present invention is enabled in the synchronous semiconductor memory device when the CAS latency LATENCY is "1" and the CAS latency LATENCY is high. If "2 or more" is characterized in that it is disabled.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, the same reference numerals and numerals indicate the same circuit for each drawing.

2 illustrates a DQM buffer according to an embodiment of the present invention. In FIG. 2, the signal PRAL is a signal that is enabled "high" when any one of the banks of the memory cells is activated, and maintains a "low" level in the standby state. CL1 is a signal indicating that the CAS latency LATENCY is "1" and is in a "high" state when the CAS latency LATENCY is "1". The DQMC is a DQM control signal enabled to be "high" when the refresh (REFESH) operation or the clock enable signal CKE is "low". And VREF represents a predetermined reference voltage. And DQM is the external input voltage.

Referring to FIG. 2, the DQM buffer 201 of the present invention has a standby state, that is, a state in which PRAL is "low", and the CAS latency LATENCY is "1", that is, CL1. It operates when it is in the "high" state. However, when the STAND-BY state, that is, PRAL is "low", the CAS latency (LATENCY) is "2 or more", that is, when the CL1 is "low" state, it does not operate.

The DQM buffer 201 is described in detail as follows. The DQM buffer 201 includes a detector 203 and a MOS transistor 205. The detector 203 detects and responds to the level of the external input signal DQM. In the standby state STAND-BY, when the CAS latency LATENCY is “1”, the MOS transistor 205 connects the power terminal N206 of the sensing unit 203 and the external power terminal VCC. When CAS latency LATENCY is "2 or more", it is a PMOS transistor which short-circuits the power supply terminal N206 of the said detection part 203 and the external power supply terminal VCC.

The DQM buffer 201 further includes an adjusting unit 207. In the standby state, the controller 207 generates a control signal PBPV having a different logic state when the CAS latency LATENCY is “1” and when the CAS latency LATENCY is “2 or more”. The control signal PBPV is applied to the gate of the MOS transistor 205.

The adjusting unit 207 includes a logic unit 209 of CL1 which is a signal indicating that the standby signal PRAL indicating the standby state and the CAS latency LATENCY are "1".

Therefore, when the standby state, that is, when the signal PRAL is "low", the CAS latency (LATENCY) is "1", that is, when the signal CL1 is "high" state, the control signal (the output signal of the control unit 207) PBPV) goes into the "low" state. When the control signal PBPV is in the "low" state, the MOS transistor 205 is "turned on" and the detector 203 senses and amplifies the level of the external input signal DQM.

However, when the standby state, i.e., the signal PRAL is "low", and the CAS latency LATENCY is "2 or more", that is, when the signal CL1 is in the "low" state, the control signal that is the output signal of the control unit 207 ( PBPV) is in a "high" state. When the control signal PBPV becomes “high”, the MOS transistor 205 is “turned off” and the sensing unit 203 does not operate. Further, whenever the refresh operation or the CKE signal is "low", the signal DQMC becomes "high". Therefore, the control signal PBPV, which is an output signal of the controller 207, becomes "high", and the MOS transistor 205 is "turned off".

3 is a timing diagram of a main signal when the CAS latency LATENCY is "1". Referring to this, the reason why CL1, which is a signal for distinguishing the case where the CAS latency LATENCY is "1" and the case where the CAS latency LATENCY is "2 or more" in the standby state, is described as follows.

In FIG. 3, the signal CLK is an external clock signal. The signal CMD is a command for instructing the operation of the memory chip. The signal DQ is externally input data. The signal DQ (R) is data to be input into the memory chip. The signal DQM is a signal that enables the DQM buffer.

In general, an active command is input in the synchronous DRAM, and a write command is input after one clock. Data is input one clock after the write command is input.

The write DQM latency (LATENCY) is defined as two clocks. Therefore, when CAS LATENCY is "1", when masking the first data of the read burst data, the data mask signal DQM should be applied at the time when the active command is applied. .

However, if the DQM buffer is simply applied to the DQM buffer to block the operation of the DQM buffer in the standby state, the active related signal may not be transferred to the DQM buffer within the SET-UP TIME.

Therefore, the data of the first clock cannot be masked. Therefore, the DQM buffer must be enabled even in the standby state prior to the active command. However, if CAS LATENCY is " 2 or more ", there is more than 1 clock time for active related signals to be delivered to the DQM buffer. Therefore, when the CAS LATENCY is "2 or more", the DQM buffer may be enabled in the active mode even by using only active-related signals.

Therefore, in the present invention, the signal CL1 that distinguishes the case where the CAS latency LATENCY is "1" from the case where the CAS latency LATENCY is "2 or more" is used. With the signal CL1, the DQM buffer is enabled only when the CAS latency LATENCY is "1", and the operation of the DQM buffer is disabled when the CAS latency LATENCY is "2 or more". do.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

According to the present invention as described above, it is possible to prevent unnecessary current flowing in the standby state to reduce power consumption.

Claims (2)

In a synchronous semiconductor memory device, A detector for sensing and responding to a level of an external input signal; A MOS transistor for controlling a connection between a power supply terminal of the sensing unit and an external power supply terminal in response to a predetermined control signal; And In the standby state, the control unit is configured to generate the control signal having a different logic state when the CAS latency LATENCY is "1" and when the CAS latency LATENCY is "2 or more". And enable when the CAS latency LATENCY is "1" in the standby state, and disable when the CAS latency LATENCY is "2 or more". The method of claim 1, wherein the control unit And a logic means of CL1 which is a signal indicating that the standby state and the CAS latency LATENCY are " 1 ".

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