KR19990003650U - Semiconductor Devices with Differential Input Buffers - Google Patents

Abstract

The present invention relates to a semiconductor device having a differential input buffer, comprising two pairs of MOS transistors (MP1, MP2; MP3, MP4) connected in parallel to a power supply voltage terminal, and a gate connected to the clock enable pin. And a drain is connected to the gate of the MOS transistors MP2 and MP3 having their gates interconnected, the MOS transistor MN1 connected to the connection node N1 of the MOS transistors MP1 and MP2, and the gate to a reference voltage. A MOS transistor MN2 having a drain connected to a connection node N2 of the MOS transistors MP3 and MP4, a gate connected to a buffer enable signal terminal, and a drain and a source connected to the MOS transistor A first input comprising a MOS transistor MN3 connected between the connection node N3 of the MN1 and MN2 and the ground, and a plurality of inverters IV1 and IV2 connected in series with the connection node N2. A buffer 10; The two pairs of MOS transistors MP1 and MP2; MP3 and MP4, the plurality of MOS transistors MN1, MN2 and MN3 and one end N2 of the drain of the MOS transistor MN2. A second input buffer configured to include an inverter IV1, wherein a gate of the MOS transistor MN1 is connected to a reference voltage terminal, and a gate of the MOS transistor MN2 is connected to a pin other than the clock enable pin. 20) is made.

Description

Semiconductor Devices with Differential Input Buffers

The present invention relates to an input buffer employed in a synchronous memory device, and more particularly, a semiconductor device having a differential input buffer in which the enable state of a clock enable signal processing input buffer and another input buffer are different in the synchronous memory device. It is about.

In general, the pin connection state of a semiconductor device such as a synchronous DRAM takes the form as shown in FIG. 1.

That is, FIG. 1 is a diagram illustrating a pin connection state of a 16M × 4bit synchronous DRAM series, wherein pin 38 is a pin for receiving a system clock CLK, and pin 37 is a clock enable signal CKE. The pin is a receiving pin, and the pin 20 is a pin receiving a bank select address BA.

The pins 21 to 26 and 29 to 35 are pins for receiving row and column addresses, and the pins 19 are pins for receiving a chip select signal (/ CS). ) Is a pin that receives a low enable signal (/ RAS).

In addition, pin 17 is a pin that receives the column enable signal / CAS, pin 16 is a pin that receives the write enable signal / WE, and pin 39 is a data input / output mask. Is a pin.

In addition, pins 5, 11, 44, and 50 are pins used for data input / output, and pins 3, 9, 43, 49, 6, 12, 46, and 52 are power supplies required for data input / output operation. The pins 1 and 27 are pins for supplying power (for example, 3.3V ± 0.3V) to the entire circuit inside the synchronous DRAM to operate the circuit. On the other hand, the pins 28 and 54 are pins that serve to stably extract current generated therein.

As described above, since a plurality of pins are formed in the synchronous DRAM, and an input buffer for buffering a signal input through the pin is installed at the rear end of the pin (that is, inside the synchronous DRAM), an external signal input through the pin is Internally signaled after being buffered by the input buffer.

Typically, an input buffer employed in a conventional synchronous DRAM is a current mirror differential buffer as shown in FIG. 2 or 3.

That is, the current mirror differential buffer shown in FIG. 2 is enabled by the buffer enable signal EN. First, when the signal Vin input from the outside is low level, the NMOS transistor MN2 is turned off. The potential of the second node N2 becomes high compared to the potential of the first node N1, and a low level signal is output as an internal signal through the inverter IV1.

On the contrary, when the signal Vin input from the outside is at a high level, the NMOS transistor MN2 is turned on so that the second node N2 is in a low state in an instant, and the high level is generated through the inverter IV1. The signal is output as an internal signal.

Here, the current mirror differential buffer shown in FIG. 2 can quickly recognize a high / low state according to the potential of the input signal Vin, but the amount of current flowing through the NMOS transistor MN1 through the first node N1 is increased. Since it is constant by the reference voltage Vref irrespective of the input signal Vin, there is a drawback of consuming a constant current regardless of the high / low state of the input signal Vin.

Meanwhile, the current mirror differential buffer shown in FIG. 3 is also enabled by the buffer enable signal EN. When the signal Vin input from the outside is at a low level, the NMOS transistor MN1 is turned off. Therefore, the potential of the second node N1 becomes lower than the first node N1 (for example, low), and thus a low level signal is output as an internal signal through the inverters IV1 and IV2.

On the contrary, when the signal Vin input from the outside is at a high level, the NMOS transistor MN1 is turned on to lower the gate voltage of the PMOS transistor MP3 to 0 V, so that the PMOS transistor MP3 is turned on. Therefore, the power supply voltage VDD is applied to the second node N2, and the power supply voltage VDD of the second node N2 is internally signaled and output as a high level signal through the inverters IV1 and IV2.

Here, the current mirror differential buffer shown in FIG. 3 consumes very little current when the potential of the input signal Vin is low, but noise may be induced in the reference voltage Vref, thereby causing a malfunction. It is possible to reduce the noise margin between high and low.

The standby operation in the conventional synchronous DRAM employing the above input buffer has a special power down mode. Under the power down mode, the low enable signal (/ RAS) and the column enable signal (/ CAS) are high. In this case, the clock enable signal CKE is input in a low state. In this case, it is particularly required to reduce the current consumption. On the other hand, since the input buffers need to quickly recognize the high / low state during normal operation, the conventional synchronous DRAM employing only one of the current mirror differential buffers shown in Figs. It won't let you.

In other words, for example, when the buffer shown in FIG. 2 is used as all the input buffers of the synchronous DRAM, the high / low state of the input signal may be recognized at high speed in normal operation, but regardless of whether the input signal is high / low By dissipating a constant current, it does not meet the requirement of reducing the current consumption under power-down mode.

For example, when the buffer shown in FIG. 3 is used as all the input buffers of the synchronous DRAM, the input signal Vin is low in the power down mode, and the NMOS transistor MN1 and the PMOS transistor MP3 are turned off. (The PMOS transistor MP4 is turned off in advance.) Although the amount of current bypassed to ground will be very small, malfunction may occur due to noise in the reference voltage Vref, thereby satisfying the requirement for eliminating the malfunction. I can't give it.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems. The semiconductor device can reduce the amount of current consumed during standby or operation and at the same time reduce the occurrence of malfunctions by changing the enable state of the clock enable buffer and the other input buffer. The purpose is to provide a semiconductor device with a differential input buffer to improve the performance of the.

According to a preferred embodiment of the present invention for achieving the above object, there is provided a first input buffer connected to the clock enable pin, and a second input buffer connected to the low enable pin / column enable pin / write enable pin, etc. In a semiconductor device, the first input buffer comprises first and fourth MOS transistors whose gates are connected to a buffer enable signal stage and turned on / off according to the buffer enable signal, and the gates are interconnected and the first input buffers. Second and third MOS transistors connected in parallel to the first and fourth MOS transistors, respectively, a gate connected to the clock enable pin, and a drain connected to the first and second MOS transistors; A fifth MOS transistor connected to the gates of the second and third MOS transistors, a gate connected to a reference voltage terminal, and a drain of the third and fourth MOS transistors; A sixth MOS transistor connected to a connection node, a seventh MOS transistor connected at a gate thereof to the buffer enable signal terminal, and a drain and a source connected between a connection node of the fifth and sixth MOS transistors and a ground; And a plurality of inverters connected in series to a drain of the sixth MOS transistor, wherein the second input buffer has a gate connected to a buffer enable signal terminal and turned on / off in accordance with the buffer enable signal. The first and fourth MOS transistors, the second and third MOS transistors whose gates are interconnected and connected in parallel to the first and fourth MOS transistors, respectively, and the gate are connected to a reference voltage terminal and are drained. A fifth MOS transistor connected to a connection node of the first and second MOS transistors, a gate of the second and third MOS transistors, and a gate of the clock; A sixth MOS transistor connected to a pin other than an enable pin, a drain connected to a connection node of the third and fourth MOS transistors, a gate connected to the buffer enable signal terminal, and a drain and a source; A semiconductor device having a differential input buffer consisting of a seventh MOS transistor connected between a connection node of the fifth and sixth MOS transistors and a ground, and a single inverter connected in series with the drain of the sixth MOS transistor. Is provided.

According to the embodiment of the present invention configured as described above, when a low level clock enable signal is input to the first input buffer, a current value consumed while the corresponding clock enable signal is internally generated is reduced, and the second input is performed. The buffer operates at a high speed with respect to the input signal.

1 is a pin connection state diagram of a general semiconductor device;

2 is a circuit diagram illustrating an example of an input buffer generally employed in a semiconductor device;

3 is a circuit diagram illustrating another example of an input buffer generally employed in a semiconductor device;

4A is a diagram showing an example of a configuration of an input buffer connected to a clock enable pin according to an embodiment of the present invention;

4 is a diagram showing a configuration example of an input buffer connected to another enable pin according to an embodiment of the present invention;

* Description of the symbols for the main parts of the drawings *

10, 20: input buffer MP1 to MP4: PMOS transistor

MN1 to MN3: NMOS transistors IV1 and IV2: Inverter

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of an input buffer connected to a clock enable pin according to an embodiment of the present invention, in which an input buffer 10 connected to the clock enable pin 37 has a gate enabled buffer signal. First and fourth MOS transistors MP1 and MP4 connected to the terminal EN and connected to the power supply voltage terminal VDD and turned on / off in accordance with the buffer enable signal, and the first and the first Second and third MOS transistors MP2 and MP3 having their respective gates connected to each other in parallel with the four MOS transistors MP1 and MP4, respectively, and a gate connected to the clock enable pin 37 and drained. A fifth MOS transistor MN1 connected to the connection node N1 of the first and second MOS transistors MP1 and MP2 and a gate of the second and third MOS transistors MP2 and MP3; A gate is connected to the reference voltage terminal Vref and the drain is the third and fourth MOS transistors M The sixth MOS transistor MN2 connected to the connection node N2 of P3 and MP4, the gate is connected to the buffer enable signal terminal EN, and the drain and the source are the fifth and sixth MOS transistors. The seventh MOS transistor MN3 connected between the connection node N3 of the MN1 and MN2 and the ground and the connection node N2 of the drain of the sixth MOS transistor MN2 are connected in series. It consists of a plurality of inverters IV1 and IV2 which perform an inverting operation on the potential applied to the connection node N2.

On the other hand, Figure 4 is a diagram showing an example of the configuration of the input buffer connected to the other enable pin in accordance with an embodiment of the present invention, a pin (for example, a low enable signal 18 different from the clock enable pin 37) ), The column enable pin 17, the write enable pin 16, the chip select pin 19, etc.) has an input buffer 20 having a gate connected to the buffer enable signal terminal EN and the source First and fourth MOS transistors MP1 and MP4 connected to a power supply voltage terminal VDD and turned on / off in accordance with a buffer enable signal, and the first and fourth MOS transistors MP1 and MP4. Second and third MOS transistors MP2 and MP3 connected in parallel to each other and connected to each other in parallel with each other, and a gate is connected to a reference voltage terminal Vref and a drain is connected to the first and second MOS transistors ( A first node connected to the connection node N1 of the MP1 and MP2 and the gates of the second and third MOS transistors MP2 and MP3. 5 MOS transistor MN1 and a gate are connected to a pin other than the clock enable pin 37, and a drain is connected to a connection node N2 of the third and fourth MOS transistors MP3 and MP4. The sixth MOS transistor MN2 and a gate are connected to the buffer enable signal terminal EN, and a drain and a source are connected to a connection node N3 of the fifth and sixth MOS transistors MN1 and MN2. The single MOS transistor MN3 connected between the ground and the connection node N2 of the drain of the sixth MOS transistor MN2 is connected in series to invert a potential applied to the connection node N2. It consists of inverter IV1.

4A and 4B, the first to fourth MOS transistors MP1 to MP4 are all PMOS transistors, and the fifth to seventh MOS transistors MN1 to MN3 are all NMOS transistors. to be.

The configuration of FIG. 4A described above is substantially the same as that of FIG. 3, except that the input signal Vin input to the gate of the NMOS transistor MN1 is a clock enable signal CKE. It is different from the composition.

In addition, the configuration of FIG. 4B described above is substantially the same as that of FIG. 2, except that the input signal Vin input to the gate of the NMOS transistor MN2 is a low enable signal / RAS or a column enable. The signal / CAS or the write enable signal / WE or the chip select signal / CS is different from the configuration of FIG.

Next, the buffering operation of the semiconductor device having the differential input buffer according to the embodiment of the present invention configured as described above is as follows.

First, when the synchronous DRAM performs a normal operation, the input buffer 10 performs a buffering operation on the high level clock enable signal CKE input to the clock enable pin 37 to enable the internal clock. A signal CKE-INT is generated, and the input buffer 20 has a low level low enable pin 18 and a column enable pin 17, a write enable pin 16, and a chip select pin 19. Internal signal SIG-INT is generated by performing buffering operation on the signal input from

That is, in FIG. 4A, since the clock enable signal CKE is at a high level during normal operation, the fifth MOS transistor MN1 is turned on, and the third MOS transistor MP3 is turned on. Since the sixth MOS transistor MN2 is turned off, the power supply voltage VDD is applied to the connection node N2, and the power supply voltage VDD applied to the connection node N2 is divided into a plurality of inverters IV1 and IV2. ), It becomes a high level signal and is output as the internal clock enable signal (CKE-INT).

In addition, in FIG. 4B, signals such as a low enable signal (/ RAS), a column enable signal (/ CAS), a write enable signal (/ WE), and a chip select signal (/ CS) are not included in normal operation. Since both are low level, the potential of the connection node N2 becomes high compared to the connection node N1, and the low level signal is output as the internal signal SIG-INT through the inverter IV1.

On the contrary, since the clock enable signal CKE is low and the other enable signals are high during standby in the synchronous DRAM, the operation of the input buffer 10 shown in FIG. 4 will be described first. The transistor MN1 is turned off so that the potential of the connection node N1 becomes higher than the potential of the connection node N2. Therefore, the low level signal at the connection node N2 becomes a low level signal through the plurality of inverters IV1 and IV2 and is output as the internal clock enable signal CKE-INT. Since the 4 MOS transistors MP3 and MP4 are turned off, the amount of current consumed is extremely small.

As described above, when the above-described input buffer 10 operates while waiting in the synchronous DRAM, the input buffer 20 shown in FIG. 4B also operates. Referring to the operation of the input buffer 20, the high level will be described. The sixth MOS transistor MN2 is driven by signals such as a low enable signal (/ RAS) or a column enable signal (/ CAS) or a write enable signal (/ WE) or a chip select signal (/ CS). Since it is turned on, the potential of the connecting node N2 becomes low immediately, and therefore, a high level signal is output as the internal signal SIG-INT through the inverter IV1, and in this case, the potential of the input node N2 is correlated. Without noise, the reference voltage Vref is not generated, and the accurate signal is output at high speed.

According to the present invention as described above, it is possible to accommodate the advantages of both buffers by appropriately employing both buffers, as compared with the conventional buffering operation using only one buffer, the standby mode of the synchronous DRAM In addition to minimizing the amount of current consumption, it is possible to process the signal at high speed without generating noise to the reference voltage, thereby improving the performance of the semiconductor device.

Claims (1)

1. A semiconductor device having a first input buffer 10 connected to a clock enable pin and a second input buffer 20 connected to a row / column / right enable pin. The first input buffer 10 includes two pairs of MOS transistors MP1, MP2; MP3, and MP4 connected in parallel to a power supply voltage terminal, a gate of which is connected to the clock enable pin, and a gate of which drain is connected to each other. The gate of the connected MOS transistors MP2 and MP3 and the MOS transistor MN1 connected to the connection node N1 of the MOS transistors MP1 and MP2 and the gate are connected to a reference voltage terminal, The MOS transistor MN2 connected to the connection node N2 of the MOS transistors MP3 and MP4, the gate is connected to the buffer enable signal terminal, and the drain and the source are connected to the MOS transistors MN1 and MN2. MOS transistor MN3 connected between the connection node N3 and ground, and a plurality of inverters IV1 and IV2 connected in series with the connection node N2, The second input buffer 20 may include the pair of MOS transistors MP1, MP2; MP3, and MP4, the plurality of MOS transistors MN1, MN2, and MN3, and the MOS transistors MN2. Inverter IV1 connected to one end N2 of the drain, The gate of the MOS transistor MN1 of the second input buffer 20 is connected to a reference voltage terminal and the gate of the MOS transistor MN2 is connected to a pin other than the clock enable pin. Semiconductor device with an input buffer.