KR100267594B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a metal interconnection line of a semiconductor device is provided to reduce a chip size by removing a misalign margin, and to improve the reliability and the yield of the device by preventing a conductive region or an interconnection line on a lower part from being revealed or etched. CONSTITUTION: Metal interconnection lines(51) are buried in the first openings(45) and formed long. Also, the metal interconnection lines are contacted with junction parts(33) through the second openings(47) and thus are connected with other junction parts or other interconnection lines electrically. Both ends of the second openings in a width direction meet the first openings, and both ends in a length direction are narrower than the junction parts and thus are included in the first openings.

Description

METHOD FOR FABRICATING METALLINES ON A SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a semiconductor device capable of improving integration by minimizing an overlap margin of a self-aligned metal contact portion to reduce chip size. It relates to a method for forming metal wiring.

The degree of integration of the semiconductor device is improved as the size of the patterns becomes smaller. Therefore, the photolithography process requires a reduction in misalign margin along with a reduction in the size of the patterns. Misalignment margin means that the line width of the metal wiring is larger than the width of the metal contact to obtain the desired device characteristics and reproducibility.

1 is a plan view of a metal wiring of a semiconductor device formed according to the prior art, wherein the metal wirings 21 are formed to be elongated in the longitudinal direction on an upper portion of the oxide film 15 and at a predetermined portion through the openings 19 in the lower portion. ) And are electrically connected to other joints or leads. The metal wires 21 have a misalignment margin so that the portion in contact with the junctions 13 is larger than the openings 19 so as to overlap the oxide film 15.

2 (a) to 2 (c) are process diagrams showing a method for forming a metal wiring of a semiconductor device obtained by cutting FIG. 1 into lines (a) to (a).

Referring to FIG. 2A, the junction parts 13 are formed in a predetermined portion of a semiconductor substrate 11 such as silicon by diffusion or ion implantation. Next, the oxide film 15 and the photoresist 17 are formed on the entire surface of the semiconductor substrate 11, and then openings 19 are formed by a general photo process to form the junctions 13. Expose

Referring to FIG. 2B, the photoresist 17 is removed, and metal wires 21 contacting the junctions 13 through the openings 19 are formed in the longitudinal direction on the surface of the oxide film 15. In this case, the metal wires 21 are formed by depositing a metal such as aluminum on the oxide film 15 to be in contact with the junctions 13 and then using the photoresist 23 as an etching mask. The photoresists 23 are formed by a conventional photographic process, the portions corresponding to the openings 19 to reduce the exposure of the junctions 13 by misalignment when forming the metallizations 21 by etching. It is made larger than these openings 19. Therefore, the metal wires 21 have a misalignment filter because portions in contact with the junctions 13 overlap with the oxide film 15.

Referring to FIG. 2 (c), the photoresist 23 formed on the metal wires 21 is removed and a protective film 25 is formed of an oxide or the like. As described above, an opening is formed in the upper portion of the junction of the conventional semiconductor device, and metal is deposited, and metal wirings contacting the connecting portions are formed through the openings by etching using a photoresist larger than the opening as a mask. Therefore, even if the photoresist pattern is misaligned to less than the misalignment margin, the metal in the opening can be etched down, which prevents the semiconductor substrate from malfunctioning due to leakage current generated by etching, thereby improving the reliability of the device and reducing defects. .

However, the metal wiring has a problem that it is difficult to reduce the overall size of the chip because the portion in contact with the junction is widened by the misalignment margin. In addition, when the photoresist pattern is misaligned more than the misalignment margin, the metal in the opening and the semiconductor substrate are etched to cause defects such as leakage current, thereby degrading reliability of the device and increasing defects.

It is therefore an object of the present invention to provide a method for forming metal wirings in a semiconductor device that can reduce the size of a chip by removing misalignment margins.

Another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can improve the reliability and yield of a device by preventing the lower conductive region or lead from being exposed or etched.

In order to achieve the above-described objects, a metal wiring forming method of a semiconductor device according to an embodiment of the present invention includes: sequentially depositing a lower oxide film, a lower etching mask layer, an upper oxide film, and an upper etching mask layer on top of conductive regions, except for a predetermined portion. Forming a first photoresist on the upper etch mask layer, and using the first photoresist as a mask to etch the exposed upper etch mask layer and the upper oxide layer in a longitudinal direction to form first openings; Removing the first photoresist and forming a second photoresist layer on top of the lower and upper etch mask layers with a width of an exposed portion greater than the first openings and a length less than the conductive region; And using the second photoresist and the upper etching mask layer, the exposed lower etching mask layer and lower oxide. Removing the film to form second openings that are self-aligned with the first openings, and forming a metal interconnect buried in the first openings and in contact with the conductive region through the second openings.

1 is a plan view of a metal wiring of a semiconductor device formed according to the prior art,

2 (a) to 2 (c) are process diagrams illustrating a method for forming metal wirings in a semiconductor device obtained by cutting the first diagram with a-a lines;

3 is a plan view of a metal wiring of a semiconductor device formed according to the present invention,

4 (a) to 4 (c) are process drawings showing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention, in which FIG.

5 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

35: lower oxide film 37: lower etching mask layer

39: upper oxide film 41: upper etching mask layer

43, 47: photoresist 51: metal wiring

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of a metal wiring of a semiconductor device formed in accordance with the present invention. As shown in the drawing, the metal wires 51 are formed by being embedded in the elongated first openings 45. In addition, the metal wires 51 are in contact with the junctions 33 through the second openings 47 at predetermined portions and are electrically connected to other junctions (not shown) or other conductors (not shown). The second openings 47 have both ends in the width direction coincident with the first openings 45, and both ends in the longitudinal direction are smaller than the joining portions 33, and are included in the first openings 45.

4 (a) to 4 (c) are step diagrams illustrating a method for forming metal wirings in a semiconductor device according to an exemplary embodiment of the present invention, in which FIG. 3 is cut along lines (b) to (b).

Referring to FIG. 4A, a junction portion 33 is formed in a predetermined portion of a semiconductor substrate 31 such as silicon or GaAs by diffusion or ion implantation. Next, an upper oxide film 35 having a thickness of about 3000 to 5000 GPa, a lower etching mask layer 37 having a thickness of about 500 to 1000 GPa, and an upper oxide film 39 having a thickness of about 5000 to 8000 GPa on the entire surface of the upper surface of the semiconductor substrate 31. And an upper etch mask layer 41 having a thickness of about 500 to 1000 Å in order. The lower and upper etch mask layers 37 and 41 may be formed of materials having different etching selectivity, such as silicon nitride (SiN), polycrystalline silicon, or alumina (Al ₂ O ₃ ). The layer 41 is formed of a material having a larger etching selectivity than the lower etching mask layer 37. That is, when the lower etching mask layer 37 is formed of silicon nitride, the upper etching mask layer 41 is formed of polycrystalline silicon or alumina having an etching selectivity larger than that of silicon nitride. Next, first photoresists 43 are formed on the upper etching mask layer 41 by a normal photographic step, and the first openings 45 are formed by using the first photoresists 43 as an etching mask. Form them. The first openings 45 are formed by sequentially removing the upper etching mask layer 41 and the upper oxide layer 39 in the longitudinal direction. Although the junction portion 33 formed on the semiconductor substrate 31 is used as the conductive region, a conductive pattern of metal or polysilicon formed on the insulating layer may be used.

Referring to FIG. 4B, after removing the first photoresists 43, second photoresists 47 are formed on the upper and lower etching mask layers 41 and 37 again. The second openings 49 are formed using the second photoresist 47 as an etching mask to expose the junctions 33. In the above, the width of the second photoresist 47 is larger than the width of the first openings 45 to allow misalignment at the top of the upper etching mask 41, the length of which is smaller than the length of the junctions 33. . In this regard, since the upper etch mask layer 41 has a larger etching selectivity than the lower etch mask layer 37, the second openings 49 may be formed in the width direction, and the upper etch mask layers 41 may extend in the second direction in the longitudinal direction. The photoresist 47 is formed using an etching mask, respectively. Accordingly, the second openings 49 have both ends coincident with both ends of the first openings 45 in the width direction, and are smaller than the lengths of the joints 33 in the longitudinal direction. That is, the widths of the first openings 45 and the second openings 49 are self aligned.

Referring to FIG. 4C, the metal photoconductors 51 which remove the second photoresist 47 and are in contact with the exposed junction 33 embedded in the first and second openings 45 and 49 are exposed. Form. The metal wires 51 are formed on top of the upper etching mask layer 41 after sequentially depositing or depositing titanium of about 300 to 600 mm thick, titanium nitride of about 600 to 900 mm thick, and tungsten of about 8000 to 1200 mm thick. Formed by removing them.

In this regard, the metals formed on top of the upper etch mask 41 may include chemical-mechanical polishing, electron-cyclotron-resonance (ECR), and reactive ion etching. Is removed by the method. At this time, the surfaces of the metal wires 51 embedded in the first openings 45 are also flat. In addition, the metal wires 51 may be formed of aluminum or the like. Next, the protective film 53 is formed on the surface of the structure described above.

5 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device in accordance with another embodiment of the present invention.

Another embodiment of the present invention does not form a mask for preventing the lower oxide layer 35 from being etched when the upper oxide layer 39 is etched while the lower oxide layer 35 and the upper oxide layer 39 are continuously deposited. Rather, to form the first openings 45. In the above, when the upper oxide film 39 is etched in the longitudinal direction by using the first photoresist 43 as an etching mask, the etching time is prevented so that the lower oxide film 35 is not removed. Adjust Next, after the first photoresist 43 is removed, the second photoresist 47 is again formed as shown in FIG. 4B, and the exposed lower oxide layer 35 is removed to form the connection portion 33. Second openings 49 exposing the second openings 49. Subsequently, the same steps as in FIG. 4C are performed.

As described above, in order to form the metal lines, a junction is formed on the semiconductor substrate, and the lower oxide film, the lower etching mask layer, the upper oxide film and the upper etching mask are sequentially stacked, and then the lower etching mask layer is formed using the first photoresist. The first openings are formed to be long to be exposed, and again, the width is larger than the first openings and the length is smaller than the junctions. Aligned to form second openings exposing the junctions. Then, metal is deposited or deposited on the entire surface to contact the exposed junctions filled in the first and second openings, and then the metals in the upper etch mask layer are removed without a mask.

Therefore, according to the present invention, the metal wires can be formed in the first and second openings which are self-aligned to a small width without the misalignment margin of the portion in contact with the connecting portion, thereby reducing the size of the chip. In addition, the metal formed in the entire surface to fill the first and second openings is removed without the mask being formed in the upper etching mask layer except for the first and second openings, so that the lower conductive region or the conductive wire is exposed and etched. This can improve the reliability and yield of the device.

As described above, the present invention has been described and illustrated with reference to the embodiments, but it will be apparent to those skilled in the art that various modifications may be made without departing from the spirit and scope of the present invention.

Claims (6)

In the metal wiring forming method of a semiconductor device electrically connecting the conductive regions, Sequentially depositing a lower oxide film, a lower etching mask layer, an upper oxide film, and an upper etching mask layer on the conductive regions, and forming a first photoresist on the upper etching mask layer except for a predetermined portion; Etching the exposed upper etching mask layer and the upper oxide layer in the longitudinal direction using the first photoresist as a mask to form first openings; Removing the first photoresist and forming a second photoresist layer on the lower and upper etch mask layers, the width of the exposed portion being greater than the first openings and the length is smaller than the conductive region; Removing the exposed lower etch mask layer and lower oxide layer using the second photoresist and the upper etch mask layer to form second openings that are self-aligned with the first openings; Forming metal wirings buried in the first openings and in contact with the conductive region through the second openings. The method of claim 1, And wherein the conductive regions are formed of junctions or conductors. The method of claim 1, And forming the lower and upper etch mask layers in polycrystalline silicon, nitride film or alumina, respectively. The method of claim 3, wherein And forming the upper etch mask from a material having an etch selectivity higher than that of the lower etch mask layer. In the metal wiring forming method of a semiconductor device electrically connecting the conductive regions, Sequentially depositing a lower oxide layer, an upper oxide layer, and an upper etching mask layer on the conductive regions, and forming a first photoresist on the upper etching mask layer except for a predetermined portion; Etching the exposed upper etching mask layer and the upper oxide layer in the longitudinal direction using the first photoresist as a mask to form first openings; Removing the first photoresist and forming a second photoresist layer on the upper etch mask layer and the lower oxide layer, the second photoresist layer having a width larger than the first openings and smaller than the conductive region in length, Removing the exposed lower oxide layer using the second photoresist and the upper etching mask layer to form second openings that are self-aligned with the first openings; Forming metal wirings buried in the first openings and in contact with the conductive regions through the second openings. The method of claim 5, And etching time such that the lower oxide film is not removed in the forming of the first openings.