KR100267046B1 - Sawtooth-voltage generating circuit and parabola-voltage generating circuit and monitor device - Google Patents

Abstract

The present invention provides a sawtooth wave voltage generator circuit, a parabola wave voltage generator circuit, and a monitor device which do not use a time constant circuit.

ROM 1 for storing initial values in each phase range in which the sawtooth voltage to be generated is divided into predetermined phases, and a switching circuit for switching clocks having different frequencies, f ₁ , f ₂ , f ₃ , f ₄ , f ₅ . ), An 8-bit up counter 2 into which the contents of the ROM 1 and a clock from the switching circuit 3 are input, and a clock from the switching circuit 3 are input, and an overflow signal is input to the 8-bit up counter 2. And a digital to analog converter 5 to which count data of the up counters 2 and 4 are input.

Description

Sawtooth voltage generator circuit, parabola wave generator circuit and monitor device

1 is a block diagram showing a configuration of a sawtooth wave voltage generating circuit according to the present invention.

2 is a waveform diagram of the vertical sawtooth voltage to be generated.

3 is a curve diagram showing the change in the count value of the up counter.

4 is a block diagram showing a configuration of a parabola wave voltage generating circuit according to the present invention.

5 is a waveform diagram of the vertical parabola wave voltage to be generated.

6 is a curve diagram showing a change in count value of an up-down counter.

7 is a block diagram showing an application example of a sawtooth wave voltage generator circuit and a parabola wave voltage generator circuit.

8 is a circuit diagram of a conventional vertical sawtooth voltage generator circuit.

9 is a circuit diagram of a conventional vertical parabola wave voltage generating circuit.

<Description of the code | symbol about the principal part of drawing>

1: ROM 2: 8 bit up counter

3: switching circuit 4: 4-bit up counter

5: digital to analog converter 10: 12-bit up-down counter

30: load signal output circuit 31: clock generation circuit

32: vertical sawtooth voltage generating circuit 33: monitor device

35: vertical parabola wave voltage generating circuit

[Industrial use]

The present invention relates to a sawtooth voltage generator circuit, a parabola wave generator circuit and a monitor device.

[Prior art]

A monitor device for a personal computer or a workstation, or a television receiver, includes a vertical sawtooth voltage generator circuit for scanning an electron beam of a CRT and a vertical parabola wave voltage generator circuit for correcting pincoushion type distortion of a display image. .

Both the vertical sawtooth wave voltage generator circuit and the vertical parabola wave voltage generator circuit are constituted by analog circuits.

8 is a circuit diagram of a conventional vertical sawtooth voltage generator circuit. In the initial state, when no charge is charged in the capacitor C ₁ , the input side of the Schmitt circuit G ₁ becomes L level. For this reason, the output side of the Schmitt circuit G ₁ is at the H level, and the diode D ₁ conducts to charge the capacitor C ₁ by the time constants of the capacitor C ₁ and the resistor R ₁ . The capacitor C when the resistance R _f and capacitor C _f is the horizontal component to remove low-pass filter to the vertical synchronizing signal V _SYC in the capacitor C ₁ via for input consisting of the charging of the _first Schmitt circuit G ₁ is turned on the output side is L level Becomes Thus, the charge is a diode D ₂ which is conductive to accumulate in the capacitor C ₁ is discharged at a time constant of the capacitor C ₁ and resistor R _2. Therefore, the transistor TR ₁ is turned on and off in accordance with the voltage change of the capacitor C ₁ , and a vertical sawtooth voltage V _S is generated at the connection portion of the transistor TR ₁ and the resistor R _O.

9 is a circuit diagram of a conventional vertical parabola wave voltage generating circuit. When the vertical deflection current of the sawtooth wave flowing through the vertical deflection yoke DY is fed to the capacitor C ₁₀ which integrates it, the vertical deflection current is integrated by the resistive component of the vertical deflection yoke DY and the capacitor C _{10 so} that the vertical parabola wave voltage is applied to the capacitor C _10. Obtained. The resistor R ₁₁ connected in series with the capacitor C ₁₀ obtains a voltage corresponding to the vertical deflection current waveform, which is used to change the phase of the vertical parabola wave voltage. The vertical parabola voltage thus obtained is input to the positive input terminal + of the operational amplifier OP through the series circuit of the capacitor C ₁₂ and the resistor R ₁₂ , and the voltage generated at the resistor R ₁ is converted into the variable resistor VR ₁ , the capacitor C ₁₃ and the resistor. When through the series circuit of the R ₁₃ to input of the operational amplifier OP unit input terminal, and outputs a voltage of the vertical parabola wave voltage V _P of the input order thereof from the operational amplifier OP.

As described above, conventional vertical sawtooth voltage generator circuits and vertical parabola voltage generator circuits generate a vertical sawtooth wave voltage and a vertical parabola wave voltage analogously by using a time constant circuit consisting of a capacitor and a resistor, for example, of a monitor device. The electron beam of the CRT is scanned, and pincushion distortion is prevented from occurring in the display image. For this reason, when it is desired to use a monitor device having a different deflection angle of the electron beam of the CRT, it is necessary to change the characteristics of the vertical sawtooth wave voltage and the vertical parabola wave voltage. However, in order to change these characteristics, there is a problem in that the capacitor and the resistance of the time constant circuit need to be replaced.

It is an object of the present invention to provide a sawtooth voltage generator circuit, a parabola wave voltage generator circuit, and a monitor device in which an exchange business of circuit components can easily correspond to the characteristics of the sawtooth voltage and parabola wave voltage. It is done.

A sawtooth voltage generating circuit according to the first invention includes a storage unit for storing an initial value of a sawtooth voltage in each phase range in which a sawtooth voltage to be generated is divided into predetermined phases, a selection unit for selectively selecting a clock of a different frequency, and the storage unit. And a digital counter to digitally / analog-convert the count data of the up-counter and the count data of the up-counter.

A parabola wave voltage generating circuit according to a second aspect of the present invention includes a storage unit for storing an initial value of a parabola wave voltage in each phase range obtained by dividing a parabola wave voltage into a predetermined phase, a selection unit for selectively selecting a clock of another frequency, and storing And a digital down-analog converter for digitally / analog converting the count content of the up-down counter and the count data of the up-down counter.

A monitor device according to a third aspect of the invention includes a sawtooth wave voltage generator circuit according to the first claim and a parabola wave voltage generator circuit according to the second claim.

In the first invention, the up-down counter receives the required initial value of the sawtooth voltage stored in the storage unit at predetermined cycles. When the clock of the frequency corresponding to the timing of accepting the initial value is selected and counted upward based on the initial value, a count value corresponding to the required sawtooth voltage is obtained. Digital / analog conversion of this count value provides the required sawtooth voltage.

In the second invention, the up-down counter counts based on the up / down count command data stored in the storage unit. The up-down counter periodically receives the required initial value of the parabola wave voltage stored in the storage unit. When the clock of the frequency according to the timing which accepts an initial value is selected, and counts upwards with respect to an initial value, the count value according to the rising change of a required parabola wave voltage is obtained. When the clock of the frequency according to the timing which accepts an initial value is selected, and it counts down with respect to an initial value, the count value according to the fall change of a required parabola wave voltage is obtained. When the count value thus obtained is digitally / analog converted, the required parabola voltage is obtained.

In the third aspect of the invention, when the characteristics of the sawtooth wave voltage or the parabola wave voltage are changed, an image display suitable for the electron beam deflection angle of the monitor device is obtained.

Hereinafter, the present invention will be described with reference to the embodiments.

1 is a block diagram showing the configuration of a sawtooth wave voltage generating circuit according to the present invention. The initial value of the vertical sawtooth voltage in each period obtained by dividing the vertical sawtooth wave voltage to be generated by one integer of the vertical period and the switching data of the switching circuit described later are stored in the ROM 1. Data of the ROM 1 is input to the 8-bit up counter 2. The load signal S _LD generated in one cycle of integers of the vertical period is input to the load terminal LD of the 8-bit up counter 2. Clocks of different frequencies f ₁ , f ₂ , f ₃ , f ₄ , f ₅ (frequency is f ₁ <f ₂ <f ₃ <f ₄ <f ₅ ) are alternatively selected by the switching circuit 3.

The selected clock is input to the clock terminal CK of the 8-bit up counter and the clock terminal CK of the 4-bit up counter 4. The carry signal output from the ripple carry out terminal RCO of the 4-bit up counter 4 is input to the enable terminal ET of the 8-bit up counter. The count data of the 8-bit up counter 2 and the count data of the 4-bit up counter 4 are input to a digital / analog converter (hereinafter referred to as D / A converter), and are input from the D / A converter 5. The vertical sawtooth voltage V _S is output. The switching circuit 3 is switched controlled by the switching data read from the ROM 1.

Next, the operation of this sawtooth voltage generating circuit will be described with the second diagram showing the vertical sawtooth voltage waveform to be generated.

When the first load signal S _LD is input to the load terminal LD of the 8-bit up counter 2 at the end of one horizontal period, the 8-bit up counter 2 is stored in the ROM 1. The phase of the vertical sawtooth voltage shown in Accept the initial value D ₀ corresponding to ₀ ). In addition, phase ( A switching signal corresponding to ₀ ) is sent to the switching circuit 3 to select a clock f ₂ , for example. The selected clock f ₂ is input to the clock terminal CK of the 8-bit up counter 2 and the 4-bit up counter 4, and the 8-bit up counter 2 and the 4-bit up counter 4 count the clocks, respectively. The count value increases.

Thereafter, when the second load signal S _LD is inputted to the load terminal LD of the 8-bit up counter 2, the 8-bit up counter 2 enters the phase of the vertical sawtooth voltage stored in the ROM 1 (( Accept the initial value D ₁ corresponding to ₁ ). In addition, the phase read from the ROM 1 ( By sending the switching data corresponding to ₁ ) to the switching circuit 3, the switching circuit ₃ selects a clock f ₃ having a higher frequency than the clock f ₂ . This clock f ₃ is counted by the 8-bit up counter 2 and the 4-bit up counter 4 to increase the count value.

However, since the frequency of clock f ₃ counting after receiving the initial value of the second time is higher than the frequency of clock f ₂ that has been counted up to that time, the second load signal S _{LD from} the input time of the first load signal S _LD The count value from the input time of the second load signal S _{LD to} the input time of the third load signal S _LD is larger than the count value up to the input time of. That is, the count value is the linear interpolation of the initial value a count value between the time that accepts an initial value in response to changes in the vertical sawtooth voltage V _S to when to accept the initial value D ₂ after receiving a D ₀ shown in FIG. 2.

In this way, each time the load signal S _LD is periodically input, a new initial value is received, and the clock of the frequency corresponding to the change in the vertical sawtooth wave voltage after the reception is selected as the switching circuit 3 to continue the counting operation as described above. When the count values of the 8-bit up counter 2 and the 4-bit up counter 4 overflow, each count value is erased and the count value changes to zero as shown in FIG.

3 shows the vertical axis as the count value and the horizontal axis as the phase (time). When the count data thus changed are inputted to the D / A converter 5 and subjected to D / A conversion, the vertical sawtooth wave voltage V _{S shown} in FIG. 3 is obtained. The vertical sawtooth wave voltage can be generated continuously by performing the count operation similar to the above every time when one horizontal period ends.

In the present embodiment, the 8-bit up counter 2 and the 4-bit up counter 4 are used as counters, but the present invention is not limited thereto, and three 4-bit up counters may be connected in series. In addition, it is possible to smoothly change the waveform of the vertical sawtooth wave voltage generated by using an up counter having a larger number of bits. In addition, the 8-bit up counter periodically accepts the initial value of the vertical sawtooth voltage in each period in which the vertical sawtooth wave voltage is divided by an integer fraction of the vertical period.However, when the next initial value is accepted, the count value reaches the initial value. Therefore, only the clock may be selected in synchronization with the load signal.

4 is a block diagram showing the configuration of a parabola wave voltage generating circuit according to the present invention. The initial value of the vertical parabola wave voltage in each period obtained by dividing the vertical parabola wave voltage to be generated by an integer fraction of the vertical period, the switching data of the switching circuit described later, and the command data of the up / down count are stored in the ROM 1. . Data of the ROM 1 is input to the 12-bit up-down counter 10. The load signal S _LD generated in one integer period of the vertical period is input to the load terminal LD and the up / down selection terminal UP / DN of the 12-bit up-down counter 10. Clocks of different frequencies f ₁ , f ₂ , f ₃ , f ₄ , f ₅ (frequency is f ₁ <f ₂ <f ₃ <f ₄ <f ₅ ) are alternatively selected by the switching circuit 3. The selected clock is input to the clock terminal CK of the 12-bit up-down counter 10. Count data of the 12-bit up-down counter 10 is input to the D / A converter 5. The switching circuit 3 is controlled by the switching data read from the ROM 1.

Next, a description will be given with reference to FIG. 5 showing a vertical parabola wave voltage waveform to be generated for the operation of this parabola wave voltage generating circuit.

When the first load signal S _LD is input to the load terminal LD of the 12-bit up-down counter 10 at the end of one horizontal period, the 12-bit up-down counter 10 is stored in the ROM 1 (Fig. 5). Phase of vertical parabola voltage shown in Accept the initial value D ₀ corresponding to _zero. Further, command data of an up count corresponding to the initial value D ₀ is received.

Then, phase from the ROM 1 _When switching data corresponding to ₀ is read and sent to the switching circuit 3, the switching circuit ₃ selects the clock f ₃ , for example. The selected clock f ₃ is inputted to the clock terminal CK of the 12-bit up-down counter 10, and the 12-bit up-down counter 10 counts up the clock to increase the count value. Subsequently, when the second load signal S _LD is input to the load terminal LD of the 12-bit up-down counter 10, the 12-bit up-down counter 10 is in phase with the vertical parabola wave voltage stored in the ROM 1. It accepts the command data in the up-count corresponding to the initial value and the initial value D ₁ D ₁ corresponding to the _first. In addition, the switching data read from the ROM 1 is sent to the switching circuit 3. As a result, the switching circuit 3 selects a clock f ₂ having a lower frequency than the clock f ₃ . The clock f ₂ the 12-bit up-down counter (10) goes to the up-counting a count value increases.

However, since the frequency of the clock f ₂ counting after receiving the _second initial value D ₂ is lower than the frequency of the clock f ₃ counted up to that time, the second load signal from the input point of the first load signal S _LD the count value of the p-side than the count value to the input time point of S _LD from the input point of the load signal _LD S for the second time to the input point of the load signal _LD S at the third cycle is smaller. That is, as shown in FIG. 2, the count value accepts the initial value in response to the change in the vertical parabola wave voltage V _P from the initial value D ₀ until the initial value D ₂ is received, and the count value between the time points is a straight line. Will be interpolated. In this manner, each time the load signal S _LD is periodically input, a new initial value is received and the 12-bit up-down counter 10 counts up.

By the way, when the 8th load signal S _LD is input to the load terminal LD during the period in which the vertical parabola wave voltage is lowered, a parabolic voltage V _P , for example, phase _The 12-bit up-down counter 10 accepts an initial value D ₈ corresponding to ₈ and a down count instruction data corresponding to the initial value. The switching circuit 3 selects the clock f _{2 based} on the switching data read from the ROM 1, and counts the clock f ₂ down by the 12-bit up-down counter 10 based on the initial value D ₈ . The value decreases. After that, when the ninth load signal S _LD is input to the load terminal LD of the 12-bit up-down counter 10, the phase of the vertical parabola wave voltage stored in the ROM 1 is received. _The 12-bit up-down counter 10 accepts the command data of the initial value D ₉ corresponding to ₉ and the corresponding down count, and the clock f ₃ having a higher frequency than the clock f ₂ is obtained by switching data read from the ROM 1. selected, and a 12-bit up-down counter 10, the clock f ₃ to the second relative to the base D ₉ goes to the down-counting the count value is reduced.

If the count value overflows, the count value is erased and becomes zero. In this way 8-th load signal S _LD is because the frequency of the clock f ₂ higher for counting the time which the load signal S _LD 9 th than the frequency clock f ₁ for counting when the input type of the 8-th load signal S _LD of The count value counted down from the input time point of the ninth load signal S _{LD to} the time point at which the count value overflows is greater than the count value counted down from the input time point to the ninth load signal S _LD input time point.

That is, the count value linearly interpolates the count value between the time points at which the initial value is received in response to the change in the vertical parabola wave voltage V _P from the initial value D ₈ until the count value becomes zero.

In a phase period in which the change in the vertical parabola wave voltage to be generated is weak, the clock of extremely low frequency is counted up or down by the 12-bit up-down counter 10 to reduce the change in the count value so that the change in the vertical parabola wave voltage is weak. Get the count value corresponding to one change. When the count data thus changed is inputted to the D / A converter 5 and subjected to D / A conversion, the vertical parabola wave voltage V _{P shown} in FIG. 6 is obtained. 6, the vertical axis represents the count value, and the horizontal axis represents the phase (time). The vertical parabola voltage V _P can be continuously generated by performing the same counting operation as described above every time when one horizontal period ends.

In this embodiment, a 12-bit up-down counter is used for the up-down counter. However, this is only an example, and the same effect can be obtained by connecting three 4-bit up-down counters in series. Therefore, in the case where the vertical sawtooth voltage and the vertical parabola voltage are generated by the digital circuit, the characteristics of the vertical sawtooth voltage and the parabola wave voltage can be easily changed by rewriting initial data in the ROM 1. For this reason, it is possible to respond simply without having to replace the capacitor and the resistance of the time constant circuit as in the prior art.

7 is a block diagram showing an application example of a sawtooth wave voltage generating circuit and a parabola wave voltage generating circuit according to the present invention. The load signal S _LD outputted from the load signal output circuit 30 in an integral period of the vertical period is input to the vertical sawtooth wave voltage generator circuit 31 and the vertical parabola wave voltage generator circuit 35. Clocks having different frequencies output from the clock generator circuit are input to the vertical sawtooth wave voltage generator circuit 32 and the vertical parabola wave voltage generator circuit 35. The vertical sawtooth voltage V _S generated by the vertical sawtooth voltage generator 32 and the vertical parabola voltage V _P generated by the vertical parabola wave voltage generator 35 are input to the monitor device 33 including the CRT. As a result, the electron beam of the CRT (not shown) of the monitor device 33 is scanned by the vertical sawtooth voltage V _S , and the scanning of the electron beam is corrected by the vertical parabola wave voltage VP so that the pincushion-free distortion does not occur on the screen of the CRT. Can be displayed.

When the monitor device 33 used is replaced with the monitor device 33 using a CRT having a different deflection angle of the CRT electron beam, the initial values of the vertical sawtooth wave voltage and the vertical parabola wave voltage stored in the ROM are changed to the deflection angle. By rewriting to an appropriate value, the characteristics of the vertical sawtooth wave voltage and the vertical parabola wave voltage can be changed as described above, and an image suitable for the deflection angle can be displayed on the CRT screen of the replaced monitor device 33 without pincushion distortion. . Therefore, the monitor apparatus 33 can be easily responded when replacing the monitor apparatus 33 with a different deflection angle of the CRT.

In the present embodiment, the case where the vertical sawtooth wave voltage generating circuit and the vertical parabola wave voltage generating circuit are applied to the monitor device has been described. However, the present invention is not limited to the monitor device.

As described above, according to the present invention, there is provided a sawtooth voltage generating circuit which can easily change the characteristics of the sawtooth voltage without replacing circuit components. Moreover, the exchange business of a circuit component provides the parabola wave voltage generation circuit which can easily change the characteristic of a parabola wave voltage. In addition, it is possible to simply change the sawtooth voltage and parabola voltage suitable for the CRT to be replaced without exchanging circuit components, and to provide a monitor device which does not generate pincushion distortion on the screen.

Claims (3)

A storage unit storing an initial value of a sawtooth voltage within each phase range in which the sawtooth voltage to be generated is divided into predetermined phases and selection data for selecting a predetermined frequency clock corresponding to the initial value, the initial value of the storage unit and the selection data A readout for reading a signal every one horizontal period in a predetermined order; a selector for selecting the predetermined frequency clock based on the selection data; and counting up at the initial value based on the predetermined frequency clock selected by the selector. A sawtooth voltage generator circuit comprising an up counter and a digital / analog converter for digitally / analogly converting count data of the upcounter. A storage unit for storing an initial value of a parabola wave voltage in each phase range obtained by dividing the parabola wave voltage into a predetermined phase and selection data for selecting a predetermined frequency clock corresponding to the initial value, the initial value of the storage unit and the selection data A reading unit for reading every one horizontal period in a predetermined order, a selection unit for selectively selecting the predetermined frequency clock based on the selection data, and counting up from the initial value based on the predetermined frequency clock selected by the selection unit And a digital / analog converter for digitally / analog converting the count data of said updown counter. A monitor device comprising a CRT (Cathode-Ray Tube), a sawtooth wave voltage generating circuit for scanning an electron beam of the CRT, and a parabola wave voltage generating circuit for correcting pincoushion distortion of the CRT display image. The sawtooth voltage generating circuit may include: a storage unit configured to store an initial value of a sawtooth voltage in each phase range obtained by dividing a sawtooth voltage to be generated into a predetermined phase and selection data for selecting a predetermined frequency clock corresponding to the initial value; A reading unit which reads the initial value of the storage unit and the selection data in a predetermined order every one horizontal period, a selection unit which selects the predetermined frequency clock based on the selection data, based on the predetermined frequency clock selected by the selection unit An up counter that counts up at the initial value, and a count data de count of the up counter. And a digital / analog converter configured to perform de-analog conversion, wherein the parabola wave voltage generation circuit is configured to generate an initial value of a parabola wave voltage within each phase range obtained by dividing the parabola wave voltage into a predetermined phase and a predetermined frequency clock corresponding to the initial value. A storage unit for storing data for selection, a reading unit for reading the initial value of the storage unit and the selection data in a predetermined order every one horizontal period, and selectively selecting the predetermined frequency clock based on the selection data And a selector, an up-down counter for counting down from the initial value based on the predetermined frequency clock selected by the selector, and a digital / analog converter for digital-to-analog converting the count data of the up-down counter. Monitor device.