KR100265354B1 - Small capacity switching system for Integrated Information Network (ISDN) - Google Patents

Abstract

PURPOSE: A low capacity switching system for an ISDN(Integrated Services Digital Network) is provided to extend a subscriber capacity, and to supply various ISDN services. CONSTITUTION: An S connector(10) temporally stores a message when each subscriber terminal attempts connection, and stores the message in a RAM(Random Access Memory) again, then performs interfaces of many ISDN(Integrated Services Digital Network) subscriber terminals. An R connector(20) reads a message received through an SLIC(Subscriber Line Interface Circuit) from an analog subscriber, and converts the message into an ISDN message to transmit the converted ISDN message to a main controller(30), then performs interfaces of analog subscriber terminals. The main controller(30) performs a most significant control in order to supply synchronous clocks to each function. A U connector(40) extracts an only D channel message from a received signal to temporally store the extracted message, and notifies an interrupt of a message reception. Then, the U connector(40) reads the message to add necessary information, and transmits the message to the main controller(30), finally supplies many central office interfaces. PRI(Primary Rate Interface) connector(50) equips a D channel control function for controlling a D channel, and supplies an interface with the main controller(30) by using a mounted SDLC(Synchronous Data Link Control) function.

Description

Small capacity switching system for Integrated Information Network (ISDN)

The present invention relates to a switching system for a small capacity integrated information communication network (ISDN), and more particularly, to a small capacity switching system for a comprehensive information communication network for building an ISDN network when the current telephone network is replaced by an ISDN network in the future.

In the conventional Digital Private Exchange (PBX), since the interface between the terminal connected to the PBX and the PBX does not conform to the standard, the terminal connected to the PBX cannot be used by connecting to the public network. In addition, since the conventional digital PBX is designed to connect a terminal having only one channel while most of them use a unique mode, there is a structural problem in connecting ISDN terminals having a plurality of channels that are currently emerging.

In other words, the backplane, board-to-board interface, or inter-process communication of the switching system should be designed to meet the ISDN characteristics.

On the other hand, in the case of digital PBX developed from the conventional analog system, it is possible to connect terminals having only one channel internally, and only the trunk line interface adds the ISDN function, so it is difficult to extend the ISDN terminal to the conventional digital PBX. In addition, even if the ISDN terminal is connected to the conventional digital PBX, since the respective protocol is used internally, the ISDN message received must be first converted into the unique protocol for protocol processing. In addition, if the ISDN function is frequently added to the local exchange, this new service is very difficult to accommodate in the digital PBX.

In addition, another problem with the conventional digital PBX is that in the process of processing a call, a message is exchanged between each board or between a dedicated line terminal and a dedicated line subscriber access board because it uses a unique format method. Even if the iPABX is realized by adding an ISDN access board to the PBX, there is a fundamental problem that needs to be converted into a unique message to process an incoming ISDN call internally in the system.

Accordingly, the present invention has been proposed to solve the above-mentioned general problems, and provides a private side to provide all ISDN services to the terminal side while ensuring that not only the subscriber access unit but also the primary group interface unit connected to the ISDN local network are fully compliant. The purpose is to provide a small-range switching system for ISDN networks.

In order to achieve the above object, the present invention provides a small-capacity switching system for an integrated telecommunication network for building an integrated ISDN network, each of which has a buffer memory connected to each of a plurality of ISDN subscriber terminals. S connection means for temporarily storing a message arriving when the terminal attempts to access the terminal, and transferring the message to internal memory (RAM) to perform an interface of a plurality of ISDN subscriber terminals; Reads the message from the analog subscriber received through the subscriber line interface circuit (SLIC) connected to each of the plurality of analog subscriber stations and connects each subscriber to the ISDN message, and converts the converted ISDN message to the main control means. R connection means for performing the interface of multiple analog subscriber stations by transmitting; It is connected to the S connection means and the R connection means, and a synchronous clock is provided to each functional part even when the system maintenance, the processing of the layer 2 and layer 3 protocols, the call processing, the B channel switching, and the connection to the network side are disconnected. The main control means for performing the highest level control to be provided; It is connected to the main control means, and extracts and stores only the D-channel message from the received signal (2B + D) temporarily and informs the reception of the message by interrupting, reads the message, adds necessary sentence information, and transmits to the main control means. Hae, Mr. U connecting means for providing a plurality of trunk line interface; And a primary channel speed (PRI) connection means for providing an interface with the main controller means by using a built-in synchronous data link control (SDLC) function. Provides a small capacity switching system for an integrated information network (ISDN).

1 is an ISDN user-network interface reference configuration as defined by the CCITT.

2 is a schematic configuration diagram of a small capacity switching system for an integrated information communication network (ISDN) according to the present invention.

Figure 3 is a block diagram showing an embodiment configuration of the S connection portion of Figure 2 according to the present invention.

4 is a block diagram showing an embodiment configuration of the R connecting portion of FIG. 2 according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a main controller of FIG. 2 according to the present invention; FIG.

Figure 6 is a block diagram showing an embodiment configuration of the U connection of Figure 2 according to the present invention.

Figure 7 is a block diagram showing an embodiment configuration of a PRI connection of Figure 2 according to the present invention.

8 is a CEPT channel address mapping state diagram of FIG. 7 according to the present invention;

9 is a self-configuration diagram of a small capacity switching system for an integrated information communication network (ISDN) according to the present invention.

10 is a polling flowchart performed in the main controller of the small capacity switching system according to the present invention.

Figure 11a is a double index ring structure in a small capacity switching system according to the present invention.

11B is a ring buffer structure diagram of a small capacity switching system according to the present invention.

12 is a primitive frame format diagram of an SDLC required for polling in a small capacity switching system according to the present invention.

* Explanation of symbols for main parts of the drawings

10: S connection 20: R connection

30: main controller 40: U connection

50: PRI connection part 1OO: Small capacity switching system for ISDN

200: ISDN local large-capacity exchanger 11a to 11c: S interface IC

12: 8-bit microprocessor (MPU)

13: ROM 14: RAM

21a to 21c: Subscriber Line Interface (SLIC)

22: 8-bit CPU 23: Memory

24: SDLC control circuit 25: tone generating circuit

26: ring generating circuit 27: DTMF receiving circuit

28: CODEC 31: 16-bit MPU

32: Memory 33: Real Time Clock Generator

34: digital switch 35: digital trunk PLL

36: asynchronous adapter control circuit 37: multiplexer

41: 8-bit MPU 42: Memory

43a to 43c: U interface IC 44: Slip buffer

51: 8-bit MPU 52: Memory

53a, 53b: HDLC control circuit 54a, 54b: series-parallel conversion circuit

55a, 55b: circuit connection circuit (CEPT IC) 56: synchronous clock generation circuit

57: oscillator

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is an ISDN user-network interface reference configuration defined by CCITT, where TE1 (Terminal Equipent Type 1) is an ISDN terminal, TE2 (Termianl Equipent Type 2) is a non-ISDN terminal, a terminal adapter (TA), and NT1 ( Network Termination Type 1) is 1 Layer Functional Network Terminator, NT2 (Network Tetmination Type 2) is 1-3 Layer Functional Network Terminator. ISDN Central Office (ISDN) is a national large-capacity exchanger, Primary Rate Interface (PRI) is the primary speed interface, R is the "R" interface, S is the "S" interface, T is the "T" interface, and U is "U". Each represents an interface.

This standardizes the configuration of users and networks as defined by the International Telegraph and Telephone Advisory Committee (CCITT) and specifies the access standards for each reference point, ie, R, S, T, and U.

However, the small-capacity switching system for an integrated information communication network (ISDN) of the present invention corresponds to a form in which the NT2 and NT1 are combined (hereinafter, simply referred to as "NT12"). In order to connect the reference point with the ISDN CO, only the U reference point or the PR1 connection function is required, but in the present invention, the R reference point connection function was also considered in order to focus on practical extension. Thus, each connection circuit was set to have the connection function with each reference point. The connection circuits include R connection circuits, S connection circuits, U connection circuits, and PRI connection circuits. The main circuit is also implemented as a board for switching.

One embodiment system configuration of the present invention is shown in FIG.

2 is a schematic configuration diagram of a small-capacity switching system for an integrated information communication network (ISDN) according to an embodiment of the present invention, in which 10 is an S connection, 20 is an R connection, 30 is a main control part, and 40 is a U connection part. , 50 is a PRI connection, 100 is a small-capacity switching system for ISDN according to the present invention, 200 is an ISDN national large-capacity exchanger respectively.

As shown in the figure, the small-capacity switching system for ISDN according to the present embodiment includes an S connection portion 10 for connecting eight ISDN subscribers, an R connection portion 20 for connecting four analog subscribers, the S connection portion and R A main control unit 30 connected to the connection unit and performing the highest level control of the system, a U connection unit 40 connected to the main control unit to provide eight trunk line interfaces, and connected to the main control unit A primary group speed (PRI) connecting portion 50 for connecting a line is provided, wherein the S connecting portion 10 and the R connecting portion 20 are connected to the subscriber side, and the U connecting portion 40 and the PRI connecting portion 50 are connected. Are connected to the side of the local exchange (ISDN C.0) 200, respectively.

S connection 10 is implemented as a single board, it is possible to connect 8 ISDN subscribers per board in a point-to-point (PTP) method, point-to-multipoint (PTM) connection through software (S / W) adjustment In this case, up to 64 ISDN subscribers can be connected.

The configuration of the S connecting portion 10 is shown in FIG.

FIG. 3 is a block diagram showing an exemplary configuration of the S connection unit 10 shown in FIG. 2, where 11a to 11c are S interface ICs, 12 is an 8-bit microprocessor (MPU), 13 is a ROM, 14 represents RAM, respectively.

As shown in the figure, one is connected to each of the ISDN subscriber terminals (subscribers # 0 to # 7), each having a first-in first-out (FIFO) buffer memory therein to arrive when the terminal is connected. Eight S-interface circuits 11a to 11c for storing messages, ROMs 13 and RAM 14 connected to the S-interface circuits 11a to 11c by address and data buses; An 8-bit microprocessor (MPU) that reads the message arriving at the FIFO buffer memory in each of the S interface circuits, stores the message in the RAM 14, and then clears the FIFO buffer memory. (12) is provided.

Thus, when any of the ISDN subscriber terminals (subscribers #O to # 7) connected to the S-connector 10 attempts to connect, the P-channel message is carried on a 2B + D signal of 192 Kbps and the S interface IC ( 11a-11c). The S interface ICs 11a to 11c typically have a high level data link control (HDLC) or LAPD control function, and store the arrival message in the internal FIFO buffer memory and then store the arrival message in the MPU 12. Notify the arrival of this by an interrupt. The MPU 12 then reads the message arriving from the FIFO buffer memory in the S interface IC, stores it back in the RAM 14, and clears the FIFO buffer memory to clear the S interface IC. To receive another message.

In order to process the arrived message, it must be transmitted to the main controller 30, which is performed by using a synchronous data link control (SDLD) function in the MPU 12. In this embodiment, a static RAM (SRAM) is used as the RAM 14.

FIG. 4 is a block diagram showing an exemplary configuration of the R connection unit 20 of FIG. 2, where 21a to 21c are Subscriber Line Interface Circuits (SLIC), and 22 is an 8-bit central processing unit (CPU). 23 represents a memory, 24 represents an SDLC control circuit, 25 represents a tone generating circuit, 26 represents a ring generating circuit, 27 represents a DTMF receiving circuit, and 28 represents a voice codec (CODEC).

As shown in the figure, the R connection unit 20 according to the present embodiment is connected to each of the analog subscriber stations (subscribers # 0 to # 3) one by one to the subscriber line interface circuit (SLIC) 21a for connecting each subscriber. To 21c), a memory 23 connected to the subscriber line interface circuits 21a to 21c by an address and data bus, and an 8-bit CPU 22 that reads and converts a message received from the analog subscriber into an ISDN message. ), A synchronous data link control (SDLC) circuit 24 connected to the CPU 22 by an address and data bus to transmit the converted ISDN message to the main controller 30, and the analog subscriber station (subscriber #). A tone generating circuit 25, a ring generating circuit 26, a DTMF receiving circuit 27, and a speech coded decoding circuit (CODEC) 28, which are connected to 0 to # 3, respectively, are provided.

An analog telephone subscriber is connected to each SLIC 21a to 21c of the R connection unit 20. In this embodiment, four analog subscriber stations are connected to one board.

Thus, the message received from the analog subscriber is read by the CPU 22 through the SLIC 21a to 21c, converted into an ISDN message, and then transmitted to the main controller 30 through the SDLC control circuit 24. On the other hand, unlike the case of the D-channel message for processing the signal, the analog voice signal is converted to 64Kbps digital data via the voice codec 28, and loaded on the B1 or B2 channel to form a pulse code modulation highway (PCM Highway). After that, it is input to the switch circuit of the main control part 30. Then, the main controller 30 commands a switch connection to the switch circuit based on the D-channel message received through the SDLC control circuit 24.

5 is a block diagram showing an embodiment of the main controller 30 of FIG. 2, in which 31 is a 16-bit MPU, 32 is a memory, 33 is a real-time clock generator, 34 is a 256 X 256 digital switch, and 35 is shown in FIG. Digital trunk PLL (Phase Locked Loop), 36 asynchronous adapter control circuit, 37 is a multiplexer.

As shown in the figure, a 16-bit MUP 31 for controlling various functions, a memory 32 connected to the MPU 31 by an address and data bus, and a clock are provided to the MPU 31. A real time clock generator 33, a 256 X 256 digital switch 34 connected to the MPU 31 by an address and data bus, and a digital trunk phase fixed connected to the 256 X 256 digital switch 34 A loop (PLL) 35, an asynchronous adapter control circuit 36 connected to the MPU 31 by an address and data bus, and a multiplexer 37 are provided.

The main controller 30 includes four types of boards connected to it (the S connection board 10 and the R connection board 20 connected to the subscriber side, the U connection board 40 connected to the local exchange 200), and In order to collect the D-channel mesher from the PRI access board 50, it is preferable to use a polling method.

In addition, the main body 30 is a top board of the system, and provides not only the maintenance of the system, the processing of layer 2 and layer 3 protocols, call processing, and various service functions, but also the B channel switching and the PRI access board ( 50) Or when the connection between the U-connection board 40 and the network side is disconnected, it is preferable to use a 16-bit MPU in order to be able to perform various functions, such as providing a synchronous clock (Clock) of each functional board.

In general, in the case of general digital PBX, in order to solve the bottleneck of the message between the lowest level subscriber board and the highest level board performing switching and call processing, a separate role of connecting a message from the subscriber board to the top board is provided. The board can be provided. In addition, when a subscriber requests a call, in order to receive and process the call quickly, the subscriber board may locally perform protocol processing except for call processing related to switching.

That is, in general, processor boards share work in a distributed processing manner, but in the case of a small capacity switching system as in the present invention, the main controller 30 performs both call processing and channel switching functions as described above. It is desirable to.

Accordingly, the remaining functional boards except for the main control unit 30 extract the D-channel message from the 2B + D or 30B + D signals received from the subscriber side or the network side, and send the extracted D channel message to the main control unit 30, and the main subject unit 30 Receives it and sends a response message to each function board.

This series of D-channel message exchange procedures are performed in the polling method of FIG.

FIG. 6 is a block diagram showing an exemplary configuration of the U connection portion 40 of FIG. 2, wherein 41 is an 8-bit MPU, 42 is a memory, 43a is a U interface IC, and 43 is a sleep buffer. It is shown.

As shown in the figure, the U-connector 40 extracts only the D-channel message from each of the 2B + D signals received in each of them, stores them in the built-in FIFO buffer memory, and then notifies the MPU 41 of the message reception with an interrupt. 8 U interface circuits 43a to 43c providing an 8-line interface, and FIFO buffer memory built into the U interface circuits 43a to 43c are read to add necessary door information, and the built-in SDLC control function is used. An 8-bit MPU 41 to be transmitted to the main controller 30, a memory 42 connected to the U interface circuits 43a to 43c and the MPU 41 by an address and data bus, and the U interface. A slip buffer 44 for correcting a phase difference of a clock generated when two or more U interface circuits of the circuits 43a to 43c is activated may be provided.

The U connecting portion 40 has a structure similar to that of the S connecting portion 10 described above. That is, eight U interface ICs 43a to 43c are embedded in each board to provide an eight-line interface. Then, each of the U interface ICs 43a to 43c is connected with a D channel control IC to extract only the D channel message from the received 2B + D signal, store the D channel message in the built-in FIF0 buffer memory, and then use the MPU 41. Notifies the side of receiving a message with an interrupt.

Then, the MPU 41 reads it, adds necessary fingerprint information, and transmits it to the main controller 30 using the built-in SDLC control function. In addition, the B channel is connected to the switch IC in the main control 30 via the backplane through the PCM Highway directly from each of the U interface ICs 43a to 43c.

In addition, when the PRI IC in the PRI connection unit 50 is activated by being connected to an ISDN CO side, a clock is extracted from the PRI connection unit 50 to maintain synchronization of the entire system. If not, that is, if the PRI connection 50 is not mounted on the self or is mounted but not activated due to an error or the like, the synchronization of the system should be made to match the clock received from the network.

Accordingly, a circuit capable of extracting the clock should be provided in the U connection portion 40. If two or more U interface lines of the eight U interface ICs 43a to 43c are activated, Since a phase difference of a clock may occur, it is preferable to further include a slip buffer 44 as a means for correcting this.

FIG. 7 is a block diagram showing an embodiment of the PRI connection unit 50 of FIG. 2, in which 51 is an 8-bit MPU, 52 is a memory, 53a and 53b are HDLC control circuits, and 54a and 54b are serial-to-parallel conversion. Circuits 55a and 55b show European circuit connection circuits (CEPT ICs), 56 show synchronous clock generation circuits, and 57 show oscillators.

As shown in the figure, the PRI connection unit 50 according to the present embodiment includes a D-channel control IC for controlling the D-channel, and uses the built-in synchronous data link control (SDLC) function to control the main controller 30. 8-bit MPU 51 which provides an interface with the < RTI ID = 0.0 > 1, < / RTI > a memory 52 connected to the MPU 51 by an address and data bus, and HDLC control circuits 52a and 53b connected to the address and data bus. ) And the first and second lines (in this embodiment, for the sake of understanding, the European system (CEPT) line is taken as an example, but in other cases, the present invention can be easily applied. First and second line connection circuits (CEPT ICs) 55a and 55b for connecting to those skilled in the art, and the address and data buses and the first and second line connection circuits. Each of the first and second lines Serial-to-parallel conversion circuits 54a and 54b for controlling the connection circuits 55a and 55b, an oscillator 57 for generating and outputting a specific frequency signal, the first and second line connection circuits 55a and 55b, and Synchronous clock generation circuits 56 are connected to the oscillators 57 and provide clock signals for maintaining the overall synchronization of the system.

PRI connection unit 50 according to the present embodiment configured as described above is preferably configured as one functional board. In addition, the one PRI function board may include a circuit for connecting two CEPT lines, and may be provided with serial and serial conversion circuits 54a and 54b to control the respective CEPT ICs 55a and 55b. In addition, since the input / output pins of the CEPT ICs 55a and 55b accept only serial streams and cannot directly connect with the address and data buses of the MPU 51, the serial / parallel conversion circuits 54a and 54b. Is provided between the MPU 51 and the CEPT ICs 55a and 55b, and is preferably mapped to have an address map as shown in FIG.

In the common line signaling system, channel 0 of the 32 channels of the CEPT system is used for frame synchronization, and channel 16 is used for the D-channel signal.

Accordingly, the MPU 51 requires a D-channel control IC to control the channel 16. The interface between the main controller 30 and the board using the SDLC in the MPU 51 is different from that of other boards. same.

In addition, a synchronous clock generation circuit 56 is provided to maintain overall synchronization of the system, and the synchronous clock generation circuit 56 includes an 8KHz frame signal from the CEPT ICs 55a and 55b and the oscillator 57. Input the 16.384MHz frequency signal from together, to generate the desired synchronization signal, such as 2MHz, 4MHz, 8MHz, and send it to the main controller 30 so that the system is synchronized.

9 is an exemplary diagram of a self-configuration of a small capacity switching system for an integrated information communication network (ISDN) according to the present invention.

In the figure, board # 0 is the PRI connection 50, boards # 1 to # 5 are the S connection 10, board # 6 is the R connection 20, and board # 7 is the U connection 40. Is the location where it is mounted.

When the system is powered on, each board performs initialization, and all boards except for the main controller wait for a polling message from the main controller.

10 is a flowchart illustrating an example of a polling process performed by the main controller 30 of the small capacity switching system according to the present invention.

Looking at the execution process with reference to the drawings, first, a subroutine 101 for initializing the ring buffer variable for board-to-board communication, securing available dynamic memory, and initializing various variables is performed. Then, an initial value is set in each port and registers of various ICs, the UART, the SDLC, and the like are initialized, and then an interrupt 102 is set to perform hardware initialization. Next, a subroutine 103 to read the mounting state of each board connected to the port of the main control unit 30 to be detected by the main control unit 30 is performed. For convenience of explanation, assuming that boards # 2 and # 4 of boards # 0 to # 7 are not mounted, the mounting board set is {0, 1, 3, 5, 7}. Polling is initiated based on the stored values.

Now, looking at the next step, after first sending a polling request signal (POLL＿rep) to the first board # 0, and waits for a response, if there is no message to send to the main controller 30 in the board # 0 polling recognition signal Send (POLL ack), otherwise send data (DATA? Ind).

Therefore, even if there is a message received from the subscriber or the network, the subscriber side access board or the network side access board cannot transmit unless it receives the polling request (POLL＿req) from the main control unit 30, and the polling request from the main control unit ( You must receive a POLL＿req before you can send it piggyback.

Through the above-described process, after performing polling of the board # 0, polling continues to the next board # 1, board # 3, and so on.

In order to transmit data to the SDLC, the data of the ring buffer area in the RAM allocated in the buffer and variable initialization process 101 is written down, the address is designated as the source, and the SDLD transmission port is designated as the sink address. Next, transmit the transmission line when it is idle.

At this time, the first ring buffer state before the transmission operation is a state in which the head pointer H and the tail pointer T are respectively 0, and in this state, after writing data to be transmitted to the ring buffer, the head pointer H is described. Only increase to 1. When an interrupt indicating that the transmission is successful is generated, the tail pointer T is increased so that both the head and the tail pointers H and T become 1s. The double index ring structure and the ring buffer structure thereof are shown in FIGS. 11A and 11B as an example.

12 is a primitive frame format diagram of an SDLC required for polling in a small capacity switching system according to an exemplary embodiment of the present invention, which is commonly used as a primitive format of an SDLC.

When the main control unit 30 transmits a message to the S connection unit 10, the recipient address in the frame format is assigned a value between 1 and 5 as the S connection unit, and the sender address is 10H.

On the contrary, when the message is sent from the S connection section 10 to the main control section 30, the sender address and the recipient address are changed.

And, if there are multiple subscribers in the board like the S connection, a value between 0 and 7 is used to identify the subscriber. Can be identified.

With the commercialization of ISDN (Commercial Information and Communication Network), various types of new ISDN terminals have emerged, and the development of voice-oriented communication to video-oriented communication has increased the demand for technology to simultaneously accommodate voice and data channels. As described above, if a private ISDN network is constructed using the system proposed as a preferred embodiment of the present invention, up to 40 subscribers can be connected when using the point-to-point method, and up to 320 subscribers can be connected when using the point-to-multipoint method. It has the effect of appropriately expanding subscriber capacity, and is installed with ISDN terminals in factories, offices, buildings, schools, hospitals, hotels, etc. to provide two channels (voice and data) for each line. It has the effect of enabling the provision of various integrated information communication network (ISDN) services.

In addition, the present invention has the effect that it is possible to provide all the services provided by the existing ISDN exchange to the terminal as it is, and to easily accommodate the provision of various additional application services. On the other hand, the present invention as described above can be suitably utilized as a switching system for accommodating multimedia terminals appearing in the future.

Although the foregoing has been described with respect to preferred embodiments of the present invention, those skilled in the art will understand that various implementations are possible within the scope of the technical idea of the present invention.

Claims (6)

A small-capacity switching system for an integrated information communication network (ISDN) for constructing a private integrated information communication network (ISDN), comprising a buffer memory connected to each of a plurality of ISDN subscriber terminals to temporarily receive a message that arrives when an attempt is made to access each subscriber station. S connection means for performing the interface of a plurality of ISDN subscriber terminal by storing and transferring to the internal memory (RAM); Reads the message from the analog subscriber received through the subscriber line interface circuit (SLIC) connected to each of the plurality of analog subscriber stations and connects each subscriber to an ISDN message, and converts the converted ISDN message to the main control means. R connection means for performing the interface of multiple analog subscriber stations by transmitting; It is connected to the S connection means and the R connection means, and the synchronous clock is provided to each function even when the system maintenance, the processing of the layer 2 and layer 3 protocols, the call processing, the B channel switching, and the connection to the network side are disconnected. The main control means for performing the highest level control to be provided; It is connected to the main control means, extracts and stores only the D-channel message from the received signal (2B + D) temporarily, informs the reception of the message with an interrupt, reads the message and adds necessary information to the main control means. U connecting means for providing a plurality of trunk line interfaces by transmitting; And a first channel speed (RPI) access means for providing an interface with the main control means by using a built-in synchronous data link control (SDLC) function. Small capacity switching system for Integrated Information Network (ISDN). The plurality of S-interface circuits of claim 1, wherein the S-connection means is connected to each of a plurality of ISDN subscriber terminals, each having a FIFO buffer memory therein to store a message arriving when the terminal attempts to connect. ; Memory means coupled to the plurality of S interface circuits by an address and data bus; And a microprocessor (MPU) coupled to the address and data bus for reading messages stored in FIFO buffer memories in the plurality of S interface circuits and storing them in the memory means and then clearing the FIF0 buffer memory. Small capacity switching system for (ISDN). 2. The terminal of claim 1, wherein the R connection means comprises: a plurality of subscriber line interface circuits (SLIC) connected to each of a plurality of analog subscriber stations and connecting each subscriber; Memory means coupled to an address and data bus to said plurality of subscriber line interface circuits; A microprocessor for reading messages received from the plurality of analog subscribers and converting the received messages into ISDN messages; A synchronous data link control (SDLC) circuit coupled to the microprocessor by an address and data bus and transmitting a converted ISDN message to the main controller means; And an integrated information communication network (ISDN) including a tone generating circuit, a ring generating circuit, a DTMF receiving circuit, and a speech encoding decoding circuit (CODEC) for converting analog speech signals into digital data, respectively, connected to the plurality of analog subscriber stations. Small capacity switching system. 2. The main control unit according to claim 1, wherein the main control means includes system maintenance, processing of layer 2 and layer 3 protocols, call processing, B channel switching, the primary group speed (PRI) connection means or the connection between the U connection sudin and the network side. A microprocessor that performs all functions, including providing a synchronous clock of the function board when it is performed; Memory means coupled to the microprocessor by an address and data bus; A real time clock generator for providing a clock to the microprocessor; A digital switch connected to the microprocessor by an addresser and a data bus; A digital trunk phase locked loop (PLL) coupled to the digital switch; And an asynchronous adapter control circuit coupled to the microprocessor via an address and data bus. The multi-line interface according to claim 1, wherein the U connection means extracts only the D-channel message from each of the 2B + D signals received, stores the D-channel message in the built-in buffer memory, and informs the microprocessor of the message reception as an interrupt. A plurality of U interface circuit to provide; A microprocessor that reads the buffer memory embedded in the plurality of U interface circuits, adds necessary fingerprint information, and transmits the necessary fingerprint information to the main control means using an embedded SDLC control function; A memory 42 coupled to the plurality of U interface circuits and the microprocessor by an address and data bus; And a slip buffer for correcting a phase difference of a clock generated when two or more U interface circuits of the plurality of U interface circuits are activated. 2. The apparatus of claim 1, wherein the PRI connection means comprises: a microprocessor having D channel control means for controlling the D channel and providing an interface with the main control means by using a built-in synchronous data link control (SDLC) function; A memory coupled to the microprocessor by an address and data bus; An HDLC control circuit coupled to the address and data bus; First and second line connection circuits (CEPT ICs) for connecting the first and second lines; A serial-to-parallel conversion circuit connected to the address and data bus and the first and second line connection circuits to control the first and second line connection circuits, respectively; An oscillator for generating and outputting a specific frequency signal; And a synchronous clock generation circuit connected to the first and second line connection circuits and the oscillator, respectively, to provide a clock signal for maintaining the overall synchronization of the system.