KR100264206B1 - Charge pump of flexible clock pulse - Google Patents

Charge pump of flexible clock pulse Download PDF

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KR100264206B1
KR100264206B1 KR1019970074107A KR19970074107A KR100264206B1 KR 100264206 B1 KR100264206 B1 KR 100264206B1 KR 1019970074107 A KR1019970074107 A KR 1019970074107A KR 19970074107 A KR19970074107 A KR 19970074107A KR 100264206 B1 KR100264206 B1 KR 100264206B1
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voltage
internal
applied voltage
vdd
clock
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KR1019970074107A
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KR19990054302A (en
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송주현
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김영환
현대반도체주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor

Abstract

PURPOSE: An internal voltage generator is provided to stabilize the operation of a semiconductor memory by maintaining the rising time and the magnitude of the internal voltage regardless of the value of a power source(Vdd). CONSTITUTION: The internal voltage generator includes an applied voltage detector(100), and a variable oscillator(200). The internal voltage generator is used for the semiconductor memory which includes a voltage raiser outputting an internal voltage(Vpp) and a voltage adjustor which receives the internal voltage and a reference voltage(Vref) and outputs a constant voltage(Vreg) under the control of a program signal(PGM). The applied voltage detector detects the voltage level of the external voltage(Vdd) from the reference voltage and a detect driving signal(Vdet-en) and outputs an external voltage level signal. The variable oscillator outputs a clock whose period is varied with response to the voltage level of the external voltage from an oscillator driving signal(OSC_EN) and the external voltage level signal.

Description

내부전압 발생장치Internal voltage generator

본 발명은 내부전압 발생장치에 관한 것으로서, 상세하게는 반도체 메모리 등에서 쓰기작업시 필요한 내부승압전압 또는 지우기작업에 필요한 부전압을 외부인가전압의 크기에 관계없이 안정적으로 발생시킬 수 있는 내부전압 발생장치에 관한 것이다.The present invention relates to an internal voltage generator, and more particularly, to an internal voltage generator capable of stably generating an internal boost voltage required for a write operation or a negative voltage required for an erase operation regardless of the magnitude of an externally applied voltage. It is about.

도 1는 종래의 내부전압 발생장치의 블록도이다.1 is a block diagram of a conventional internal voltage generator.

종래의 내부전압 발생장치는 외부인가전압(Vdd)이 인가되고 발진구동신호(OSC_EN)에 의하여 일정주기의 클럭(CLOCK)을 출력하는 발진부(10)와, 상기 클럭(CLOCK)을 입력받아 내부승압전압(Vpp)을 출력하는 승압부(20)와, 내부승압전압(Vpp)과 기준전압(Vref)을 입력받고 프로그램신호(PGM)에 조정에 의하여 정전압(Vreg)을 상기 승압부(20)로 출력하는 전압조절부(30)로 구성된다.In the conventional internal voltage generator, an oscillation unit 10 which outputs a clock CLOCK of a predetermined period by an externally applied voltage Vdd is applied and the oscillation driving signal OSC_EN is input, and the internal voltage is increased by receiving the clock CLOCK. The booster 20 which outputs the voltage Vpp and the internal booster voltage Vpp and the reference voltage Vref are input, and the constant voltage Vreg is adjusted to the booster 20 by adjusting the program signal PGM. It consists of a voltage adjusting section 30 to output.

상기 종래의 내부전압 발생장치는 다음과 같이 동작한다.The conventional internal voltage generator operates as follows.

발진구동신호(OSC_EN)와 외부인가전압(Vdd)을 이용하여 발진부(10)에서는 승압부(20)에 필요한 일정주기의 클럭(CLOCK)을 출력한다. 상기 발진부(10)에 출력된 일정주기의 클럭(CLOCK)은 승압부(20)에 입력되어 내부승압전압(Vpp)을 출력한다. 그리고, 상기 출력되는 내부승압전압(Vpp)은 외부인가전압(Vdd)에 따라 전압의 크기와 원하는 전압까지의 상승시간이 크게 차이를 나타내기 때문에 전압조절부(30)에서는 상기 승압부(20)의 내부승압전압(Vpp)과 기준전압(Vref) 및 프로그램신호(PGM)을 입력받아 정전압(Vreg)을 만들어 상기 승압부(20)로 출력한다.Using the oscillation drive signal OSC_EN and the externally applied voltage Vdd, the oscillator 10 outputs a clock CLOCK having a predetermined period necessary for the booster 20. The clock CLOCK having a predetermined period output to the oscillator 10 is input to the booster 20 to output the internal boosted voltage Vpp. In addition, the output step-up voltage (Vpp) has a large difference between the magnitude of the voltage and the rise time up to the desired voltage according to the external applied voltage (Vdd) in the voltage regulator 30 in the booster 20 The internal boosted voltage Vpp, the reference voltage Vref, and the program signal PGM are input to generate a constant voltage Vreg, and output the same to the booster 20.

그러나, 종래의 기술은 발진부에서 출력되는 클럭(CLOCK)이 높은 외부인가전압(Vdd)이 인가되면 주기가 짧아지고 출력되는 내부승압전압(Vpp)도 빨리 승압되나, 전류의 소모가 매우 크게되어 전력손실이 크며, 잡음으로 인하여 내부회로가 불안정하여진다. 또한 낮은 외부인가전압(Vdd)이 인가되면 발진부에서 출력되는 클럭(CLOCK)주기가 길어지므로 내부승압전압(Vpp)은 늦게 승압되고 낮은 낮은 승압전압(Vpp)이 만들어져 상기 내부승압전압(Vpp)을 사용하는 메모리의 동작속도가 늦어지고 정확한 동작이 이루어지지 못하는 문제점을 가진다.However, in the related art, when an externally applied voltage Vdd with a high clock clock output from the oscillator is applied, the cycle is shortened and the internal boosted voltage Vpp is quickly boosted, but the current consumption is very large and the power is increased. The loss is large and noise makes the internal circuit unstable. In addition, when a low externally applied voltage Vdd is applied, the clock cycle output from the oscillator becomes longer, so the internal boost voltage Vpp is boosted lately and a low low boost voltage Vpp is generated, thereby reducing the internal boost voltage Vpp. The operation speed of the memory to be used is slow and accurate operation is not achieved.

따라서, 본 발명은 상기 종래의 문제점을 해결하여 외부인가전압(Vdd)의 크기에 관계없이 출력되는 내부승압전압(Vpp)의 상승시간과 크기를 일정하게 유지하여 메모리의 동작을 안정화시킬 수 있는 내부전압 발생장치에 관한 것이다.Accordingly, the present invention solves the above-mentioned problems and maintains the rise time and magnitude of the internal boost voltage Vpp output regardless of the magnitude of the externally applied voltage Vdd, thereby internally stabilizing the operation of the memory. It relates to a voltage generator.

상기 목적을 달성하기 위한 본 발명에 따른 내부전압 발생장치는 내부승압전압(Vpp)을 출력하는 승압부와, 내부승압전압(Vpp)과기준전압(Vref)을 입력받고 프로그램신호(PGM)에 조정에 의하여 정전압(Vreg)을 상기 승압부로 출력하는 전압조절부와, 기준전압(Vref)과 인가전압 검출 구동신호(Vdet-en)에 의하여 외부인가전압(Vdd)의 레밸을 검출하여 외부인가전압 레밸신호(Vdd30, Vdd36)을 출력하는 인가전압 검출부와, 발진구동신호(OSC_EN) 및 상기 외부인가전압 레밸신호(Vdd30, Vdd36)에 의하여 외부인가전압(Vdd)의 레밸에 따라 주기가 변화하는 클럭(CLOCK)을 상기 승압부로 출력하는 가변 발진부로 구성된다.The internal voltage generator according to the present invention for achieving the above object is a boost unit for outputting the internal boost voltage (Vpp), the internal boost voltage (Vpp) and the reference voltage (Vref) is received and adjusted to the program signal (PGM) The voltage regulating unit outputs the constant voltage Vreg to the boosting unit, and the level of the external applied voltage Vdd is detected by the reference voltage Vref and the applied voltage detection driving signal Vdet-en to thereby apply the external voltage level. An applied voltage detector for outputting the signals Vdd30 and Vdd36, and a clock whose period varies depending on the level of the external applied voltage Vdd by the oscillation drive signal OSC_EN and the external applied voltage level signals Vdd30 and Vdd36. And a variable oscillator for outputting CLOCK) to the booster.

도 1는 종래의 내부전압 발생장치의 블럭도1 is a block diagram of a conventional internal voltage generator

도 2는 본 발명에 따른 내부전압 발생장치의 블록도2 is a block diagram of an internal voltage generator according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10. 발진부 20, 300. 승압부10. Oscillator 20, 300. Booster

30, 400 전압조절부 100. 인가전압 검출부30, 400 voltage regulator 100. applied voltage detector

200. 가변 발진부200. Variable Oscillator

이하, 첨부한 도면을 참고하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 내부전압 발생장치의 블록도이다.2 is a block diagram of an internal voltage generator according to the present invention.

상기 본 발명에 따른 내부전압 발생장치는 내부승압전압(Vpp)을 출력하는 승압부(300)와, 내부승압전압(Vpp)과 기준전압(Vref)을 입력받고 프로그램신호(PGM)에 조정에 의하여 정전압(Vreg)을 상기 승압부(300)로 출력하는 전압조절부(400)와, 기준전압(Vref)과 인가전압 검출 구동신호(Vdet-en)에 의하여 외부인가전압(Vdd)의 레밸을 검출하여 외부인가전압 레밸신호(Vdd30, Vdd36)을 출력하는 인가전압 검출부(100)와, 발진구동신호(OSC_EN) 및 상기 외부인가전압 레밸신호(Vdd30, Vdd36)에 의하여 외부인가전압(Vdd)의 레밸에 따라 주기가 변화하는 클럭(CLOCK)을 상기 승압부(300)로 출력하는 가변 발진부(200)로 구성된다.The internal voltage generating device according to the present invention receives the boosting unit 300 for outputting the internal boosting voltage Vpp, the internal boosting voltage Vpp and the reference voltage Vref, and is adjusted to the program signal PGM. The level of the externally applied voltage Vdd is detected by the voltage controller 400 outputting the constant voltage Vreg to the booster 300 and the reference voltage Vref and the applied voltage detection driving signal Vdet-en. Level of the external applied voltage Vdd by the applied voltage detector 100 for outputting the externally applied voltage level signals Vdd30 and Vdd36 and the oscillation drive signal OSC_EN and the externally applied voltage level signals Vdd30 and Vdd36. According to the present invention, a variable oscillation unit 200 outputs a clock CLOCK whose period changes according to the boosting unit 300.

상기 인가전압 검출부(100)에서 출력되는 외부인가전압 레밸신호(Vdd30, Vdd36)는 외부인가전압(Vdd)의 레밸을 세밀하게 감지하기 위하여 두 개이상의 신호로 구성할 수 있다.The externally applied voltage level signals Vdd30 and Vdd36 output from the applied voltage detector 100 may be configured with two or more signals to detect the level of the externally applied voltage Vdd in detail.

상기 본 발명에 따른 내부전압 발생장치는 다음과 같이 동작한다.The internal voltage generator according to the present invention operates as follows.

상기 인가전압 검출부(100)는 기준전압(Vref)과 인가전압 검출 구동신호(Vdet-en)를 입력받아 외부인가전압(Vdd)의 레밸을 검출하여 외부인가전압 레밸신호(Vdd30, Vdd36)을 출력한다.The applied voltage detector 100 receives the reference voltage Vref and the applied voltage detection driving signal Vdet-en to detect the level of the external applied voltage Vdd and outputs the external applied voltage level signals Vdd30 and Vdd36. do.

이때, 인가되는 외부인가전압(Vdd)이 3.0V 이하 일때는 외부인가전압 레밸신호(Vdd30, Vdd36)는 모두 "로우"상태가 된다.At this time, when the externally applied voltage Vdd is 3.0V or less, the externally applied voltage level signals Vdd30 and Vdd36 are both in a "low" state.

상기, 출력되는 외부인가전압 레밸신호(Vdd30='로우', Vdd36='로우')와 발진구동신호(OSC_EN)가 가변 발진부(200)에 입력되면 출력되는 클럭(CLOCK)의 주기가 빨라진다.When the externally applied voltage level signals Vdd30 = 'low' and Vdd36 = 'low' and the oscillation driving signal OSC_EN are input to the variable oscillator 200, the cycle of the clock CLOCK is output faster.

또한 인가되는 외부인가전압(Vdd)이 3.0V 이상 3.6V 이하 일때는 외부인가전압 레밸신호(Vdd30, Vdd36)는 '하이', '로우' 상태가 된다.When the externally applied voltage Vdd is 3.0V or more and 3.6V or less, the externally applied voltage level signals Vdd30 and Vdd36 become 'high' and 'low' states.

상기, 출력되는 외부인가전압 레밸신호(Vdd30='하이', Vdd36='로우')와 발진구동신호(OSC_EN)가 가변 발진부(200)에 입력되면 출력되는 클럭(CLOCK)의 주기는 상기 외부인가전압(Vdd)이 3.0V이하 일때보다는 늦어진다.When the externally applied voltage level signal (Vdd30 = 'high', Vdd36 = 'low') and the oscillation driving signal OSC_EN are input to the variable oscillator 200, the period of the clock CLOCK outputted is the external. It is later than when the voltage Vdd is 3.0V or less.

또한 인가되는 외부인가전압(Vdd)이 3.6V 이상 일때는 외부인가전압 레밸신호(Vdd30, Vdd36)는 모두 '하이' 상태가 된다.When the externally applied voltage Vdd is 3.6V or more, the externally applied voltage level signals Vdd30 and Vdd36 are all in a high state.

상기, 출력되는 외부인가전압 레밸신호(Vdd30='하이', Vdd36='하이')와 발진구동신호(OSC_EN)가 가변 발진부(200)에 입력되면 출력되는 클럭(CLOCK)의 주기는 상기 외부인가전압(Vdd)이 3.0V이상 3.6V 이상 일때보다는 늦어진다.When the externally applied voltage level signal (Vdd30 = 'high', Vdd36 = 'high') and the oscillation driving signal OSC_EN are input to the variable oscillator 200, the period of the clock CLOCK outputted is the external. The voltage Vdd is slower than when 3.0 V or more and 3.6 V or more.

상기 가변발진부(200)에서 출력된 클럭(CLOCK)의 주기에 따라승압부(300)에서는 내부승압전압(Vpp)을 출력한다. 그리고 상기 승압부(300)의 내부승압전압(Vpp)은 기준전압(Vref) 및 프로그램신호(PGM)을 입력받아 전압조정부(400)에 입력되어 정전압(Vreg)을 만들어 상기 승압부(300)로 출력한다.The booster 300 outputs the internal boosted voltage Vpp according to the period of the clock CLOCK output from the variable oscillator 200. The internal boosting voltage Vpp of the boosting unit 300 receives a reference voltage Vref and a program signal PGM and is input to the voltage adjusting unit 400 to generate a constant voltage Vreg to the boosting unit 300. Output

상기 승압부(300)는 입력되는 외부인가전압(Vdd)이 낮으면 클럭(CLOCK)의 주기가 빨라져 승압동작시간을 빠르고 인가되는 외부인가전압(Vdd)에서 내부승압전압(Vpp)으로의 승압정도가 커지며, 입력되는 외부인가전압(Vdd)이 높으면 클럭(CLOCK)의 주기가 늦어져 승압동작시간이 늦어지고 인가되는 외부인가전압(Vdd)에서 내부승압전압(Vpp)으로의 승압정도가 작아진다.When the externally applied voltage Vdd is low, the period of the clock CLOCK is shortened, so that the boosting unit 300 boosts the boosting operation time quickly from the externally applied voltage Vdd to the internal boosted voltage Vpp. When the externally applied voltage Vdd is high, the cycle of the clock is delayed, and the step-up operation time is delayed, and the voltage boosting degree from the externally applied voltage Vdd to the internal boosted voltage Vpp decreases. .

따라서, 본 발명은 외부인가전압(Vdd)의 레밸이 높을 때 발생하는 소비전력을 크게 줄일 수 있고, 노이즈 발생도 줄여 회로가 안정되며 출력되는 내부승압전압(Vpp)의 높이와 승압시간이 일정하게 유지할 수 있으므로 메모리 장치의 동작이 정확히 이루어지는 잇점이 있다.Therefore, the present invention can greatly reduce the power consumption generated when the level of the externally applied voltage Vdd is high, reduce the occurrence of noise, and stabilize the circuit. The height of the internal boosted voltage Vpp and the boosting time are constant. As it can be maintained, the operation of the memory device is accurate.

Claims (3)

내부승압전압(Vpp)을 출력하는 승압부와, 내부승압전압(Vpp)과기준전압(Vref)을 입력받고 프로그램신호(PGM)에 조정에 의하여 정전압(Vreg)을 상기 승압부로 출력하는 전압조절부를 가지는 반도체 메모리 등에서 쓰기작업시 필요한 내부승압전압 또는 지우기작업에 필요한 부전압을 발생시킬 수 있는 내부전압 발생장치에 있어서,A booster for outputting the internal boosted voltage Vpp, and a voltage adjuster for receiving the internal boosted voltage Vpp and the reference voltage Vref and outputting a constant voltage Vreg to the booster by adjusting the program signal PGM. In an internal voltage generator capable of generating an internal boost voltage required for a write operation or a negative voltage required for an erase operation in a semiconductor memory or the like, 기준전압(Vref)과 인가전압 검출 구동신호(Vdet-en)에 의하여 외부인가전압(Vdd)의 레밸을 검출하여 외부인가전압 레밸신호을 출력하는 인가전압 검출부와,An applied voltage detector for detecting the level of the external applied voltage Vdd by the reference voltage Vref and the applied voltage detection driving signal Vdet-en and outputting an external applied voltage level signal; 발진구동신호(OSC_EN) 및 상기 외부인가전압 레밸신호에 의하여 외부인가전압(Vdd)의 레밸에 따라 주기가 변화하는 클럭(CLOCK)을 상기 승압부로 출력하는 가변 발진부로 구성되어 외부인가전압(Vdd)의 변화에 관계없이 일정한 승압시간과 높이의 내부전원을 발생시킬 수 있는 것이 특징인 내부전압 발생장치.The oscillation drive signal OSC_EN and a variable oscillation unit for outputting a clock CLOCK whose period changes depending on the level of the external applied voltage Vdd by the external applied voltage level signal are output to the booster. An internal voltage generator characterized in that it can generate an internal power supply with a constant boosting time and height regardless of the change of. 청구항 1에 있어서, 상기 인가전압 검출부는The method of claim 1, wherein the applied voltage detection unit 외부인가전압(Vdd)의 레밸을 세밀하게 구분하여 출력되는 외부인가전압 레밸신호를 두 개이상 출력하는 것이 특징인 내부전압 발생장치.An internal voltage generator characterized in that it outputs two or more externally applied voltage level signals which are output by dividing the level of externally applied voltage (Vdd) in detail. 청구항 1에 있어서, 상기 가변 발진부는The method of claim 1, wherein the variable oscillator 외부인가전압(Vdd)이 높을수록 클럭(CLOCK)의 주기가 늦어지는 것이 특징인 내부전압 발생장치.Internal voltage generator characterized in that the cycle of the clock (CLOCK) is delayed as the externally applied voltage (Vdd) is higher.
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US7183830B2 (en) 2004-06-29 2007-02-27 Samsung Electronics Co., Ltd. Integrated circuit and method for generating a clock signal
US7489566B2 (en) 2006-07-07 2009-02-10 Samsung Electronics Co., Ltd. High voltage generator and related flash memory device
CN107017606A (en) * 2017-05-25 2017-08-04 乐清市诚富电器科技有限公司 A kind of zero sequence is inverted from locking-typed control circuit of earth leakage and its method

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KR100338953B1 (en) * 1999-12-29 2002-05-31 박종섭 High voltage generation circuit
KR100451991B1 (en) * 2002-07-12 2004-10-08 주식회사 하이닉스반도체 Internal power voltage generating circuit
KR100436128B1 (en) * 2002-07-16 2004-06-14 주식회사 하이닉스반도체 Device for controlling voltage generator
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KR100825021B1 (en) * 2006-06-29 2008-04-24 주식회사 하이닉스반도체 Inner-voltage generator
KR100881540B1 (en) * 2007-11-12 2009-02-05 주식회사 하이닉스반도체 Oscillator circuit for semiconductor memory device
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US7183830B2 (en) 2004-06-29 2007-02-27 Samsung Electronics Co., Ltd. Integrated circuit and method for generating a clock signal
DE102005031075B4 (en) * 2004-06-29 2011-01-13 Samsung Electronics Co., Ltd., Suwon Integrated circuit and method for generating a clock signal
US7489566B2 (en) 2006-07-07 2009-02-10 Samsung Electronics Co., Ltd. High voltage generator and related flash memory device
CN107017606A (en) * 2017-05-25 2017-08-04 乐清市诚富电器科技有限公司 A kind of zero sequence is inverted from locking-typed control circuit of earth leakage and its method

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