KR100263194B1 - Aging method of plasma display elements - Google Patents

Aging method of plasma display elements Download PDF

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KR100263194B1
KR100263194B1 KR1019960042812A KR19960042812A KR100263194B1 KR 100263194 B1 KR100263194 B1 KR 100263194B1 KR 1019960042812 A KR1019960042812 A KR 1019960042812A KR 19960042812 A KR19960042812 A KR 19960042812A KR 100263194 B1 KR100263194 B1 KR 100263194B1
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vdd
aging
voltage
electrode
pulse
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KR1019960042812A
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KR19980023348A (en
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박자호
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김영남
오리온전기주식회사
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/42—Measurement or testing during manufacture
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)
  • Gas-Filled Discharge Tubes (AREA)

Abstract

PURPOSE: An aging method for a plasma display panel is provided to increase the control efficiency without damaging of a driving circuit by reducing voltage variation(dV/dt) on FETs of aging voltage generation circuit during generation of an aging voltage(VDD) by half. CONSTITUTION: A pulse of +VDD/2 and -VDD/2 is applied on at least one electrode of the plurality of electrodes. Then, another pulse of +VDD/2 and -VDD/2 is applied on the rest electrodes. At last, a voltage difference corresponding to the aging voltage(VDD) is detected between the pulse of +VDD/2 and -VDD/2 on the one electrode and the pulse of -VDD/2 and +VDD/2 on the rest electrodes.

Description

플라즈마 표시소자의 에이징 방범Aging security of plasma display devices

제1도는 PDP의 일례로서 3전극소자를 보이는 단면도,1 is a cross-sectional view showing a three-electrode device as an example of a PDP,

제2도는 3전극소자에서 종래의 에이징 방법을 보이는 파형도,FIG. 2 is a waveform diagram showing a conventional aging method in a three-electrode device,

제3도는 4전극소자를 보이는 단면도,FIG. 3 is a cross-sectional view showing a four-electrode element,

제4도는 4전극소자에서 종래의 에이징 방법을 보이는 파형도,4 is a waveform diagram showing a conventional aging method in a four-electrode element,

제5도는 본 발명에 의한 3전극소자의 에이징 방법을 보이는 파형도,FIG. 5 is a waveform diagram showing an aging method of a three-electrode device according to the present invention,

제6도는 본 발명에 의한 4전극소자의 에이징 방법을 보이는 파형도이다.6 is a waveform diagram showing an aging method of a four-electrode device according to the present invention.

* 도면의 주요부분에 사용된 부호의 설명Description of reference numerals used in the main parts of the drawings

X,Y : 전극 S,S1,S2 : 보조전극X, Y: electrode S, S1, S2: auxiliary electrode

VDD : 에이징(aging)전압 GND : 기저(基底)전압(=0)VDD: aging voltage GND: ground voltage (= 0)

본 발명은 플라즈마 표시소자(PDP: Plasma Display Panel)의 제조에 관한 것으로, 특히 그 에이징(aging)방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) manufacturing method and, more particularly, to an aging method thereof.

가장 간단한 구성의 PDP는 두 기판에 전극이 서로 교차대향 구성된 직류(DC)형 PDP인바, DC형 PDP는 구동이 간단하지만 방전개시가 늦고 메모리 효과가 없어 발광휘도가 낮으며 고해상도의 동화상 표시가 어려워, 교류(AC)형이나 하이브리드(hybrid)형등 여러 가지 개선된 PDP가 출현하였다.In the simplest configuration, the PDP has a direct current (DC) type PDP in which electrodes are crossed and oppositely arranged on two substrates. The DC type PDP is simple to drive, but has a low discharge brightness and low memory brightness. , Alternating current (AC) type, and hybrid type.

이들중 AC형의 고휘도와 DC형의 간단한 구동을 달성할 수 있는 PDP중의 하나가 다전극형 PDP인바, 제1도에는 먼저 3전극 PDP를 도시하였다.Among these PDPs, one of the PDPs capable of achieving AC type high brightness and DC type simple driving is a multi-electrode type PDP, and in the first drawing, a three-electrode PDP is shown first.

제1도에서, 두 기판(P1,P2)에는 기본적인 전극(X,Y)이 교차 대향 배열되고, 어느 한 전극(Y)에 보조전극(S)이 평행으로 배열되어 두 대향전극(X,Y)간에 주(主)방전을 두 인접전극(Y,S)간의 보조방전이 촉진 및 유지하게 된다.In FIG. 1, basic electrodes X and Y are arranged in a crossing arrangement on two substrates P1 and P2 and auxiliary electrodes S are arranged in parallel on any one of the electrodes Y to form two counter electrodes X and Y The auxiliary discharge between the two adjacent electrodes Y and S promotes and maintains the main discharge.

여기서 각 전극(X,Y,S)들은 인쇄방법으로 형성되는 것이 일반적인 바, 인쇄방법은 인쇄페이스트(paste)로 패턴(pattern)인쇄한 뒤 이를 건조 및 소성(燒成)시켜 전극(X,Y,S)을 구성한 것이므로 상당한 불순물이 잔류하고 있어서, PDP의 제조후 정격(政格)전압을 인가해서는 방전이 일어나지 않는다.Here, each of the electrodes X, Y, and S is formed by a printing method. In the printing method, a pattern is printed with a paste, followed by drying and firing, , S), so that a considerable amount of impurities remain, and discharge is not caused by application of a rated voltage after the manufacture of the PDP.

즉 PDP는 초기에는 정격전압보다 상당히 높은 전압에서 방전을 일으키며 이 상태로 구동을 개시하면 불순물이 방출되며 점차 그 특성이 안정화되어 정격전압으로 방전이 일어날 수 있게 되는 것이다.That is, the PDP initially discharges at a voltage significantly higher than the rated voltage. When the PDP starts driving in this state, the impurities are discharged, and the characteristics of the PDP gradually become stable, so that the discharge can occur at the rated voltage.

이러안 안정화 과정을 PDP의 제조후 인위적으로 수행해주는 것이 에이징(aging)과징이다. 에이징은 에이징 전압을 점차 정격전압까지 낮추어 주는 방법이나, 일정한 에이징 전압을 인가하되 펄스(pulse)형태로 인가하여 점차 펄스의 폭이나 갯수를 감소시키는 방법이 사용되고 있는데, 후자의 방법이 제어가 용이하여 주로 사용되고 있다.Aging is the process of artificially performing the stabilization process after PDP manufacturing. Aging is a method of gradually lowering the aging voltage to the rated voltage, but a method of decreasing the width or number of pulses gradually by applying a constant aging voltage in a pulse form is used. The latter method is easy to control It is mainly used.

제1도에 도시된 3전극 소자의 펄스방식 에이징방법은 제2도에 도시된 바와 같이 정격전압의 2배 정도의 에이징전압(VDD)을 두 전극(Y,S)에 교호적인 펄스로 인가하는 방식으로 이루어진다(GND는 기저전압 0임).In the pulse-type aging method of the three-electrode device shown in FIG. 1, as shown in FIG. 2, an aging voltage VDD of about twice the rated voltage is applied to the two electrodes Y and S in alternate pulses (GND is zero ground voltage).

이하의 설명에서는 주로 전극(Y)과 이에 평행한 보조전극(S)간의 에이징을 설명하지만, 대향전극(X)과의 에이징도 유사한 과정으로 이루어진다.In the following description, the aging between the electrode Y and the auxiliary electrode S parallel thereto is described, but the aging with the counter electrode X is also similar.

한편 제3도에는 보조전극(S1,S2)이 2개인 4전극소자가 도시되어 있는 바, 그 에이징도 제4도에 도시된 바와 같이 각 전극(Y,S1,S2)간에 교호적으로 에이징전압(VDD)의 펄스가 인가되도록 하고 있다.3 shows a four-electrode element having two auxiliary electrodes S1 and S2. Aging of the four auxiliary electrodes S1 and S2 is alternately performed between the electrodes Y, S1 and S2 as shown in FIG. (VDD) is applied.

여기서 일반적인 PDP의 정격전압은 통상 150내지 250V에 비교적 고전위를 사용하게 되는 바, 이에 따라 에이징전압(VDD)은 400내지 500V정도가 사용된다.Here, the rated voltage of a general PDP is usually 150 to 250 V, and a relatively high potential is used. Accordingly, an aging voltage (VDD) of about 400 to 500 V is used.

그런데 PDP의 구동에 사용되는 FET의 내압(耐壓)은 통상 500V 정도로서 에이징시 약간의 전압불안정으로도 구동회로가 손상될 위험성이 매우 크게 된다. 뿐만아니라 FET등 일반적인 스위칭(switching)소자로 달성할 수 있는 전압변화율(dV/dt)은 200V/ns 이하인 바, 전위차(dV)가 매우 커서 적절한 제어도 어려운 문제가 수반된다.However, the withstand voltage of the FET used for driving the PDP is usually about 500V, and therefore there is a great risk that the driving circuit is damaged even when voltage is unstable at the time of aging. In addition, since the voltage change rate (dV / dt) that can be achieved by a general switching device such as a FET is 200 V / ns or less, the potential difference (dV)

이에 따라 본 발명의 목적은 구동회로의 적절한 제어가 가능하며 구동회로의 손상우려가 없는 에이징방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide an aging method capable of appropriately controlling a driving circuit and not damaging the driving circuit.

이와 같은 목적의 달성을 위해 본 발명에 의한 에이징방법은To achieve the above object, an aging method according to the present invention includes:

복수의 전극간에 에이징 전압(VDD)을 교호적인 펄스형태로 인가하는 에이징방법에 있어서,An aging method for applying an aging voltage (VDD) between a plurality of electrodes in the form of alternating pulses,

어느 한 전극에 +VDD/2와 -VDD/2의 펄스를 교호적으로 인가하고,A pulse of + VDD / 2 and -VDD / 2 is alternately applied to one of the electrodes,

나머지 전극에 +VDD/2 또는 -VDD/2의 펄스를 인가하여,A pulse of + VDD / 2 or -VDD / 2 is applied to the remaining electrode,

한 전극의 + 또는 -VDD/2 펄스와 나머지 전극의 - 또는 +VDD/2 펄스간에 VDD에 해당하는 전위차(電位差)를 형성하는 것을 특징으로 한다.A potential difference corresponding to VDD is formed between the + or -VDD / 2 pulse of one electrode and the - or + VDD / 2 pulse of the remaining electrode.

이러한 구성에 의하면 에이징시 구동전압이 FET의 내압보다 충분히 낮아지므로 구동회로가 손상될 우려가 없으며 전압변화율도 종래의 1/2이 되어 적절한 제어가 이루어질 수 있게 된다.According to this configuration, since the driving voltage at the time of aging is sufficiently lower than the breakdown voltage of the FET, there is no fear of damaging the driving circuit, and the rate of voltage change is also reduced to 1/2 of the conventional one.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제5도에는 먼저 제1도에 도시된 바와 같은 3전극소자의 에이징에 적합한 방법을 도시하고 있는데, 한 전극, 예를들어 전극(Y)에는 에이징 전압(VDD)의 1/2에 해당하는 구동전압(VDD/2)이 기저전압(GND)을 중심으로 +VDD/2와 -VDD/2로 교번하고 있다.FIG. 5 shows a method suitable for aging a three-electrode element as shown in FIG. 1, wherein one electrode, for example, the electrode Y, is driven with a half of the aging voltage VDD The voltage (VDD / 2) alternates between + VDD / 2 and -VDD / 2 around the ground voltage (GND).

한편 다른 전극, 예를들어 보조전극(S)에는 +VDD/2 또는 -VDD/2의 펄스가 교호적으로 인가되고 있다.On the other hand, a pulse of + VDD / 2 or -VDD / 2 is alternately applied to another electrode, for example, the auxiliary electrode S.

이에 따라 두 전극(Y, S) 사이에는 두 펄스마다 +VDD/2 - (-VDD/2) =VDD, 즉 에이징전압에 해당하는 전위치가 형성된다.Accordingly, + VDD / 2 - (-VDD / 2) = VDD, that is, the entire position corresponding to the aging voltage is formed between the two electrodes Y and S for each two pulses.

한편 제6도에는 제3도에 도시된 4전극 소자의 에이징에 적합한 방법을 도시하고 있는 바, 한 전극(Y)에는 +VDD/2와 -VDD/2의 구동전압이 교번하고, 다른 전극(S1,S2)들에는 +VDD/2의 구동전압이 교호적으로 인가되어 전극(Y)과 보조전극(S1,S2)들 사이에는 네 펄스마다 +VDD/2 -(-VDD/2) = VDD의 전위차가 형성된다.6 shows a method suitable for aging the four-electrode element shown in FIG. 3, in which the driving voltage of + VDD / 2 and -VDD / 2 is alternately applied to one electrode Y, VDD / 2) = VDD / 2 for every four pulses between the electrode Y and the auxiliary electrodes S1 and S2 by alternately applying a driving voltage of + VDD / Is formed.

즉 본 발명에 의하면 종래 에이징전압(VDD)의 1/2의 구동전압으로 에이징전압(VDD)에 해당하는 전위차를 형성하여 에이징을 수행하게 되는 것이다.That is, according to the present invention, a potential difference corresponding to the aging voltage (VDD) is formed at a driving voltage of 1/2 of the conventional aging voltage (VDD) to perform aging.

이에 따라 소요 에이징전압(VDD)이 400 내지 500V일 때 구동전압(VDD/2)은 200 내지 250V가 되므로 FET의 내압보다 충분히 낮아 역압(逆壓)이나 리플(ripple)의 발생등 전압 불안정시에도 FET의 손상이 없게 된다. 또한 전압변화율(dV/dt)도 종래의 1/2에 불과하게 되어 FET등 일반적인 스위칭소자에 의해 적절히 제어할 수 있게 된다.Accordingly, when the required aging voltage VDD is 400 to 500 V, the driving voltage VDD / 2 becomes 200 to 250 V, which is sufficiently lower than the breakdown voltage of the FET, so that even when voltage is unstable such as reverse pressure or ripple The FET is not damaged. Also, the voltage change rate (dV / dt) is only half of that of the conventional device, so that it can be properly controlled by a general switching device such as an FET.

이에 따라 본 발명은 구동회로의 손상우려 없이 효율적인 제어가 가능한 에이징이 이루어질 수 있게 하는 효과가 있다.Accordingly, the present invention has the effect of enabling aging to be efficiently controlled without fear of damaging the drive circuit.

Claims (1)

플라즈마 표시소자의 복수의 전극간에 정격전압보다 높은 에이징 전압(VDD)을 교호적인 펄스형태로 인가하는 에이징 방법에 있어서,An aging method for applying an aging voltage (VDD) higher than a rated voltage between a plurality of electrodes of a plasma display device in the form of alternating pulses, 상기 복수의 전극중 어느 한 전극에 +VDD/2와 -VDD/2의 펄스를 교호적으로 인가하고,A pulse of + VDD / 2 and -VDD / 2 is alternately applied to one of the plurality of electrodes, 나머지 전극에 +VDD/2 또는 -VDD/2의 펄스를 인가하여,A pulse of + VDD / 2 or -VDD / 2 is applied to the remaining electrode, 상기 한 전극의 + 또는 -VDD/2 펄스와 상기 나머지 전극의 - 또는 +VDD/2 펄스간에 상기 에이징전압(VDD)에 해당하는 전위차를 형성하는 것을 특징으로 하는 플라즈마 표시소자의 에이징방법.Wherein a potential difference corresponding to the aging voltage (VDD) is formed between the + or -VDD / 2 pulse of the electrode and the - or + VDD / 2 pulse of the remaining electrode.
KR1019960042812A 1996-09-30 1996-09-30 Aging method of plasma display elements KR100263194B1 (en)

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KR100736261B1 (en) * 2001-06-29 2007-07-06 오리온피디피주식회사 Aging Method For Plasma Display Panel
KR20030066896A (en) * 2002-02-05 2003-08-14 삼성에스디아이 주식회사 Method for aging plasma display panel wherein waveform of applied pulse is improved
KR100456437B1 (en) * 2002-03-18 2004-11-09 구자회 Aging method for plasma display panel
KR100528692B1 (en) * 2002-08-27 2005-11-15 엘지.필립스 엘시디 주식회사 Aging Circuit For Organic Electroluminescence Device And Method Of Driving The same
KR20040072111A (en) * 2003-02-08 2004-08-18 현대 프라즈마 주식회사 Asing process of plasma display panel
KR100603828B1 (en) * 2003-03-17 2006-07-24 엘지.필립스 엘시디 주식회사 Bias-aging method and the circuit structure for AMOLED

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