KR100261032B1 - Inverse quantizer for digital video camera - Google Patents

Abstract

PURPOSE: An inverse quantizing apparatus of a DVC(digital video camera) is to optimize an inverse quantizing function to be fit for a specification of the DVC, thereby simplifying a circuit construction of the apparatus. CONSTITUTION: A state controlling portion(100) controls an entire timing to perform an inverse quantizing operation. An area number output portion(110) counts input VLD data in a DCT(discrete cosine transform) block unit according to control of a state controlling portion. A DC register(140) stores a class number and an inverse quantizing number according to control of a state controlling portion. An amp register(130) stores amp data according to control of a state controlling portion. A run generating portion(120) generates 0 according to input run data. An inverse quantization deciding portion(150) receives the area number output from the area number output portion, and the class number and the inverse quantizing number output from the DC register to decide an inverse quantizing step and then output the step according to control of the run generating portion.

Description

INVERSE QUANTIZER FOR DIGITAL VIDEO CAMERA

The present invention relates to an inverse quantizer for implementing an algorithm for extending a compressed video signal in a digital video camera (DVC).

In general, the quantization of the input DCT data is a factor that has a decisive effect on the compression rate and the encoding performance of the digital data, so that the bit amount of the compressed video data can be adjusted by changing the quantization step.

The quantization process is performed by an area number, a class number, and a quantization number. The quantization process is performed in units of DCT blocks including 8 x 8 pixels, which form one DCT block. This is because the first DCT data of the 64 DCT data has a DC value and the remaining 63 DCT data have an AC value.

That is, since 16-bit data input first in one DCT block is DC data, quantization is always performed in units of DCT blocks forming 64 data.

On the other hand, the quantization interval in the DCT block is determined by a class number, an area number, and a quantization number, as shown in FIG. 1, wherein the class number is the value of the AC coefficient value in the DCT block as shown in FIG. The magnitude, i.e., the absolute value of the AC coefficient, can be easily determined, and the area number is determined according to the position in the DCT block, that is, the position of the coefficient of the DCT block, as shown in FIG.

In addition, the quantization numbers are determined one by one in macroblock units consisting of six DCT blocks. Since the amount of data generated in one video segment consisting of five macroblocks is set to be limited to a predetermined bit amount in the DVC standard, The quantization number must be set to meet the specification.

As described above, in order to dequantize and decompress the quantized and compressed data, it is necessary to undergo an inverse quantization process in which the above process is inversely performed.

That is, the inverse quantizer determines the inverse quantization step by three variables of a quantization number, a class number, and an area number, and performs inverse quantization with this value.

The dequantizer of DVC which dequantizes Variable Length Decoder (VLD) data as input according to the dequantization number, class number, and area number set as described above should be simple in circuit while complying with DVC specification.

Accordingly, an object of the present invention is to provide an inverse quantizer for performing stretching according to a specification and simplifying a circuit in a DVC.

In order to achieve the above object, the dequantizer of the DVC according to the present invention is a state control means for adjusting the overall timing to perform dequantization, and counts in units of DCT blocks whenever VLD data is input according to the control of the state control means. An area number output means for outputting a corresponding area number, a DC register for storing class numbers and inverse quantization numbers input under control of the state control means, and an amplifier for storing amplifier data input under control of the state control means A register generating means for generating a '0' according to the run data input under the control of the state control means, and an area number output from the area number output means under the control of the state control part and from the DC register. Dequantization step is determined by inputting output class number and dequantization number. And inverse quantization step determination means for outputting under control of the run generation means, and amplifier data output from the amplifier register in accordance with dequantization step output from the dequantization step determination means under control of the run generation means. Characterized in that it consists of inverse quantization means for inverse quantization.

1 is a diagram for explaining quantization interval determination.

2 is a diagram for explaining class number determination.

3 is a diagram for explaining an area number in a DCT block;

4 is a block diagram of an inverse quantization apparatus of DVC according to the present invention

5 (a) is a structural diagram of the DC data

5 (b) is a structural diagram of the AC data

* Explanation of symbols for main parts of the drawings

100: state control unit 110: area number output unit

111: counter 112: region generator

120: run generator 121: run counter

122: pulse generator 130: amplifier resistor

140: DC register 150: dequantization step determination unit

160: inverse quantizer

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 4, the quantization apparatus of the DVC according to the present invention includes a state controller 100, an area number output unit 110, a run generator 120, an amplifier register 130, a DC register 140, and an inverse. It is composed of a quantization step determiner 150, and an inverse quantizer 160.

The state controller 100 adjusts the overall timing to perform dequantization.

The area number output unit 110 counts in units of DCT blocks every time the VLD data (ICOEF [15: 0]) is input under the control of the state controller 100, and corresponds to the area number AREA [1: 0]. A counter 111 which counts each time VLD data (ICOEF [15: 0]) is input and resets each time one DCT block is input according to the control of the state controller 100, and The area number generator 112 generates an area number AREA [1: 0] corresponding to the count value output from the counter 111 and outputs the area number AREA [1: 0] to the inverse quantization step determination unit 150.

Here, the DCT block is composed of one DC data consisting of 16 bits and 63 AC data, and a total of 64 VLD data (ICOEF [15: 0]). That is, the DCT block is composed of 8 x 8 DCT data, the first DCT data is a DC data containing a 2-bit class number, 4-bit dequantization number and a 9-bit DC coefficient value representing the DCT block, The second to last 64th DCT data is AC data containing 9 bits of amplifier data and 6 bits of run data.

The DC data includes a 2-bit class number (CL [1: 0]) and a 3-bit dequantization number (IQNO [3: 0]) as shown in FIG. That is, the DC data is a 2-bit class number (ICOEF [1: 0]), a 1-bit mode number (ICOEF [2]), and a 9-bit DC coefficient (ICOEF [ 11: 3]), and a 3-bit inverse quantization number (ICOEF [12:15]).

In addition, the AC data includes 9-bit amplifier data (ICOEF [8: 0]) and 6-bit run data (ICOEF [14: 9]) as shown in FIG.

The counter 111 is composed of a 6-bit counter by counting '64' from '0' to '63' for the VLD data clock input according to the input of the VLD data output from the state controller 100. 64 VLD data, that is, one DCT block is counted and reset each time one DCT block is input, that is, whenever 64 VLD data is input, according to the control of the state controller 100.

The DC register 140 stores a class number CL [1: 0] and an inverse quantization number IQNO [3: 0] input under the control of the state controller 100.

The amplifier register 130 stores amplifier data (ICOEF [8: 0]) input under the control of the state controller 100.

The run generator 120 generates '0' according to the run data (ICOFF [14: 9]) input under the control of the state controller 100, and under the control of the state controller 100. The run counter 121 generates '0' while counting the input run data ICOFF [14: 9], and when the count value of the run counter 121 reaches '0', a pulse is generated to generate run data. It consists of a pulse generator 122 to indicate that the output is complete.

The inverse quantization step determination unit 150 controls the area number AREA [1: 0] output from the area number output unit 110 and the DC register 140 under the control of the state control unit 100. The inverse quantization step IQSTEP [2: 0] is determined by inputting the class number CL [1: 0] and the inverse quantization number QNO [3: 0], which are output from the Output according to the control.

The inverse quantizer 160 controls the amplifier register 130 according to an inverse quantization step IQSTEP [2: 0] output from the inverse quantization step determiner 150 under the control of the run generator 120. Inverse quantization of the amplifier data AMP [8: 0] outputted from the quantization of the inverse quantization step IQSTEP under the control of the run generator 120. A shifter for shifting the amplifier data AMP [8: 0] output from the amplifier register 130 according to [2: 0]).

The operation of the quantization device of the DVC according to the present invention configured as described above will be described.

When DC data, which is the first VLD data among the 64 VLD data forming one DCT block, is input, the state controller 100 resets the counter 111 and outputs a DCT data clock to the counter 111. In this case, when the VLD data clock is input, the counter 111 increases by '1' to count.

Meanwhile, the state controller 100 controls the DC register 140 to control the 2-bit class number CL [1: 0] and the 4-bit dequantization number IQNO [3: 0] in the DC data. Save it.

That is, the DC data includes a 2-bit class number CL [1: 0] and a 4-bit dequantization number IQNO [3: 0], as shown in Fig. 5A. Under the control of the state control unit 100 is stored in the DC register 140.

As such, 64 VLD data forming one DCT block after the 2-bit class number CL [1: 0] and the 3-bit inverse quantization number IQNO [3: 0] are stored in the DC register 140. When AC data, which is the second VLD data, is input, the state controller 100 outputs a VLD data clock to the counter 111. In this case, when the DCT data clock is input, the counter 111 increases by '1' to count.

When the counting value of the counter 111 increases to '1' and becomes '2', the area generator 112 receives a counting value '2' output from the counter 111 as shown in FIG. 3. The area number '0' will be output.

That is, the DCT block is zigzag scanned from the first VLD data into which the DC data including the DC coefficient value is input, as shown in FIG. 3. Accordingly, according to the 64 counting values from '0' to '63' output from the counter 111, the area generator 112 knows the current position of the data and the area number (AREA [1 :) of the position. 0]).

In other words, the area number has a value from '0' to '3' by counting the position in the DCT block and decoding it.

When the area number is output from the area generator 112 while the dequantization number and the class number are stored in the DC register 140 as described above, the state control unit 100 controls the DC register 140 to control the DC register ( The class number CL [1: 0] and the inverse quantization number stored in 140 are output to the inverse quantization step determination unit 150.

In this way, when the class number CL [1: 0], the inverse quantization number IQNO [3: 0], and the area number AREA [1: 0] are input, the inverse quantization step determination unit 150 shows FIG. The dur quantization step is determined as shown.

On the other hand, the AC data is a bitstream of a series of valid constants as run-amplifier values consisting of run data and amplifier data.

Therefore, when the first AC data is input, the run counter 121 of the run generator 120 resets the run data (ICOEF [8: 0]) of the AC data from the state control unit 100. Counts according to the output clock and outputs '0'. That is, the run counter 121 outputs '0' according to the clock while decreasing by '1' according to the clock that is reset by the run data. In other words, the number of '0' corresponding to the value of the run data is output, and the inverse quantizer 160 reverses '0' output from the run counter 121 according to the dur quantization step of '0'. Quantize and output That is, '0' output from the run counter 121 is outputted as DCT data without being dequantized.

At this time, when all the '0' corresponding to the run data is output and the counting value of the run counter 121 becomes '0', the pulse generator 122 generates a pulse to complete the output of the run data and the amplifier data. Indicates that it is time to quantize dur.

When the pulse is generated in the pulse generator 122 as described above, the inverse quantization step determiner 150 outputs the inverse quantization step IQSTEP [2: 0] to the inverse quantizer 160.

In addition, if the amplifier data (ICOEF [8: 0]) is input after the run data is input, the amplifier register 130 stores it under the control of the state controller 100, and in the pulse generator 122 When a pulse is generated and input to the amplifier register 130, the amplifier register 130 outputs the stored amplifier data AMP [8: 0] to the dequantizer 160.

The inverse quantizer 160 dequantizes the amplifier data according to the inverse quantization step output from the inverse quantization step determiner 150. That is, the input 9-bit amplifier data is quantized by shift left in the inverse quantizer by the inverse quantization step, and is output as 9-bit dequantization data, that is, DCT data.

When the process is described sequentially as follows.

First, when DC data is input, the inverse quantization number and class number are stored in the DC register 140. Next, when AC data is input, the area number output unit 110 outputs an area number, and inverse quantization step determination unit. In 150, the dequantization number is determined.

When run data of the AC data is input, the run counter 121 of the run generator 121 outputs '0' to the dequantizer 160 as much as the run data so as to dequantize it to '0'. At this time, when the amplifier data of the AC data is input again, the amplifier register 130 stores it.

When the number of '0's is output from the run counter 121 as much as the run data value, the pulse generator 122 generates a pulse.

When the pulse is generated, the inverse quantization step determination unit 150 outputs the inverse quantization number to the inverse quantizer 160 and outputs the amplifier data from the amplifier register 130 to perform inverse quantization.

Next, when AC data, which is the third VLD data, is input among the 64 VLD data forming one DCT block, the state controller 100 outputs a VLD data clock to the counter 111. In this case, when the VLD data clock is input, the counter 111 increases by '1' to count.

When the counting value of the counter 111 increases to '1' and becomes '3', the area generator 112 receives the counting value '3' output from the counter 111 as shown in FIG. 3. The corresponding area number will be output.

When the area number is generated in this way, the above process is repeated to dequantize the third VLD data and output the DCT data.

By continuing to dequantize the remaining 64th VLD data in this manner, one DCT block is quantized. As such, when one DCT block is dequantized, the counter 111 is reset to '0'. Then, when the first VLD data of the next DCT block is input, the above method is repeated.

As described above, the inverse quantization apparatus of the DVC according to the present invention can optimize the inverse quantization function to conform to the DVC specification and simply implement the circuit.

Claims (9)

State control means for adjusting the overall timing to perform dequantization; Area number output means for counting in units of DCT blocks and outputting a corresponding area number each time VLD data is input under the control of the state control means; A DC register for storing a class number and an inverse quantization number input under control of the state control means; An amplifier register for storing amplifier data input under the control of the state control means; Run generation means for generating a '0' in accordance with the run data input under the control of the state control means; Under the control of the state control unit, a dequantization step is determined by inputting an area number output from the area number output means, a class number and an inverse quantization number output from the DC register, and output according to the control of the run generation means. Inverse quantization step determination means; And An inverse quantization unit configured to inversely quantize the amplifier data output from the amplifier register according to the inverse quantization step outputted from the inverse quantization step determination unit under the control of the run generation means. . The method of claim 1, wherein the dequantization means And a shifter for shifting the amplifier data output from the amplifier register according to the inverse quantization step output from the inverse quantization step determination means under the control of the run generation means. The method of claim 1, wherein the DCT block is Dequantization apparatus of DVC, characterized by 64 VLD data. The method of claim 3, wherein the DCT block is Inverse quantization device of DVC characterized by consisting of one DC data of 16 bits and 63 AC data. 5. The apparatus of claim 4, wherein the DC data includes a 2-bit class number and a 4-bit dequantization number. The method of claim 4, wherein the AC data is DVC dequantizer, characterized in that it contains 9 bits of amplifier data and 6 bits of run data. The method of claim 1, wherein the area number output means A counter that counts each time VLD data is input and resets each time one DCT block is input according to the control of the state control means; And And an area number generator for generating a corresponding area number according to the count value output from the counter 111 and outputting the area number to the quantization step determination means. The method of claim 7, wherein the counter Dequantizer of DVC, characterized in that consisting of a 6-bit counter. The method of claim 1, wherein the run generating means A run counter that generates '0' while counting the run data input according to the control of the state control means; And And a pulse generator for generating a pulse when the count value of the run counter reaches '0' to indicate that output of the run data is completed.

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