KR100260312B1 - Pseudo random noise offset auto-generation of digital mobile communication - Google Patents

Abstract

PURPOSE: A pseudo random noise offset automatic generator is provided to reduce the size of a circuit by removing a circuit for extracting a primary output value and simplifying a circuit extracting a shift value, using an existing mask circuit intact. CONSTITUTION: A pseudo random noise offset automatic generator includes a 15-bit linear shift sequence register(LSSR)(1) for outputting a state output value when a 'MFSR_CLK' signal is HIGH and for maintaining its previous state for one period when the 'MFSR_CLK' signal is shifted to LOW to insert '0' bit into the shift output value. A mask circuit(2) combines the mask output value from a mask table(5) and the state output value from the 15-bit LSSR(1). A NOR gate(11) NOR-operates the shift output value outputted via the mask circuit(2) and a load enable signal(L_E). A zero bit insertion circuit(10) inserts a zero bit into the bit of the value(S1) outputted via the NOR gate(11). An AND gate(12) performs an AND operation for a zero enable(Zero_En) signal from the zero enable(Zero_En) control terminal(10-2) and a system clock to output the 'MFSR-CLK' signal to the 15-bit linear shift sequence register(LSSR)(1). An inverter(13) inverts the system clock to input the result into a zero bit insertion circuit(10).

Description

Pseudorandom Noise Offset Automatic Generator in Digital Mobile Communication System

1 is a typical PN offset automatic generator circuit diagram.

2 is a PN offset automatic generator circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1: 15-bit LSSR 2: Mask Circuit

5: mask table 10: zero bit insertion circuit

10-1: 4-bit binary counter 10-2: zero enable control stage

11: noah-gate 12: end-gate

13: inverter

The present invention relates to a 64-chip pseudo random noise (PN) offset automatic generator used in a code division multiple access (CDMA) method. The present invention relates to a PN offset automatic generator in a digital mobile communication system in which a generator structure is manufactured in a simple structure and outputs only shifted values for establishing accurate system synchronization.

Generally, in a mobile phone system of a digital mobile communication system using a code division multiple access method, since a plurality of base stations must each have a unique pilot, all base stations use the same PN sequence generator, and each base station has a unique offset for each base station in the base sequence. sfift) is assigned to identify the base station.

At this time, the basic unit of offset is 64 PN chip, and the characteristic equation that generates PN sequence is “minimum poiynomial (order: 15)”.

P _I (χ) = χ ¹⁵ + χ ¹³ + χ ⁹ + χ ⁸ + χ ⁷ + χ ⁵ +1

Use P _(Q) (χ) = χ ¹⁵ + χ ¹² + χ ¹¹ + χ ¹⁰ + χ ⁶ + χ ⁵ + χ ⁴ + χ ³ + 1.

In addition, when 14 consecutive '0s' are generated at the PN sequence output, by inserting one more '0' value bit into the 14 bits generated, the period of the PN sequence is changed from 2 ¹⁵ -1 to 2 ¹⁵ . Establish system motivation.

Under the above operation, when looking at the PN sequence generator, which is a device used in the digital modulation / demodulation unit on the terminal side, it generates a primary output value and a shifted shift output value of the primary value. As shown in FIG. 1, the configuration includes a 15-bit Linear Shift Sequence Register (hereinafter referred to as LSSR) 1 for outputting a Primary Output and a State Output. ; A mask circuit (2) for outputting a shifted value with respect to said primary output value; A primary zero value insertion circuit (3) for inserting a zero value at a position at which a zero value is inserted when outputting a primary value in the 15-bit LSSR (1); When the shift output value is outputted from the mask circuit 2, the shift circuit 0 comprises a shift zero value compensating insertion circuit 4 for compensating the shift value by inserting a zero value at a position where the zero value is inserted.

The primary zero value insertion circuit 3 compares the state output value A output from the 15-bit LSSR 1 with the initial 15 bit value B, and if the two values are equal (A = B), A first comparator 3-1 for outputting a 'high' value; First and second di-flip planes 3-2 and 3-3 for outputting values output from the first comparator 3-1 according to a system enable signal S_E; An end-gate (3-4) for outputting a sequence enable signal (Seq_En) to the 15-bit LSSR (1) side; The shift zero value compensating insertion circuit (4) comprises: a third di-flip (4-1) for delaying and outputting a value output from the mask circuit (2) according to a system enable signal (S_E); The 15-bit binary counter 4-2, the value D output from the 15-bit binary counter 4-2, and the offset value C are compared to each other and output from the 15-bit binary counter. A second comparator 4-3 for outputting a 'low' value when the value D is greater than or equal to (D≥C); A fourth de flip flip 4-4 that receives a value output from the second comparator 4-3 through an AND-gate, and outputs the input value according to a system enable signal S_E; ; One terminal (0) receives a shift value output from the mask circuit (2), and one terminal (1) receives a value output from the third di-flip-flop (4-1), these two inputs One of the determined values is composed of a mux 4-5 for selectively outputting the output value according to the output value of the fourth di-flop flop 4-4 input to the select terminal 5.

In addition, the inverters (I), NAND (N), and (A), and Oa-gate which are not given signs in the above-described configuration are separately indicated in the drawings by the preceding letter, and the process used when describing the circuit is described. I will explain.

Looking at the operating state of the main part of the PN offset automatic generator configured as described above are as follows.

When the load-enable signal L_E and the LSSR load state signal are input to the 15-bit LSSR 1, a state output value is output as an output thereof, and the signal is again output to the first comparator ( 3-1).

The first comparator 3-1 receives a state value input to one terminal A and an initial value of 15 bits input to one terminal B, compares the two values, and as a result, the two values are the same. Outputs a 'high' value.

At this time, the initial value of 15 bits used in this circuit is the value of '000 ‥‥ 0100', and the comparator always outputs 'low' value, and when the two input values are same as above, it outputs 'high' value. do.

The meaning of this 'high' value indicates that 14 '0' value bits occur, and then it is time to insert one more '0' value bit into the next bit. After the occurrence, the 'high' value is output from the first comparator 3-1.

In this case, when the value output from the first comparator 3-1 continues to be normally output of '0' and the operation when '1' is output, the operation will be described below.

① First, when a normal '0' value is outputted, '0' is applied to the first di-flip-flop 3-2 connected to the first comparator 3-1, and this value is NAND-. A value of '0', which is input to one side of the gate N and output from the first comparator 3-1 of the previous clock, is input to the other side of the NAND-gate N (3-3). ) And the inverter I is input as a '1' value (0 and 1 are applied to both input terminals).

Then, a value of '1' is output from the NAND gate N, which is input to the end gate 3-4, and consequently, the sequence enable signal maintains a high state.

② When the value '1' is output from the first comparator 3-1, the value '1' is input to one side of the NAND gate N and the first comparator 3-1 of the previous clock is input to the other side. A value of '0', which is the value output from the second key, is input as a '1' value through the second di-flip flop 3-3 and the inverter I (1 and 1 are applied to both input terminals).

Then, a value of '0' is output from the NAND gate N, which is input to the end gate 3-4, and as a result, the sequence enable signal is changed into a 'low' state.

In this case, the output is stopped in the 15-bit LSSR 1 and continues one cycle of the previous clock.

③ If '0' is input to the first comparator 3-1 again through the above steps, '0' is input to one side of the NAND gate N, and the first comparator 3 of the previous clock to the other side. A value '1', which is a value output from -1), is input as a value '0' through the second de-flip flop 3-3 and the inverter I (0 and 0 are applied to both input terminals).

Then, a value of '1' is output from the NAND gate N, which is input to the end gate 3-4, and as a result, the sequence enable signal is set to a high state again.

The following operation repeats the above process, and the primary value is output through the above process.

On the other hand, the operation for extracting the shifted value of this value is as follows.

The shift value input through the mask circuit 2 is input to one side terminal O of the mux 4-5 and the third di-flip flip 4-1, and the two input values are selected. Look at the output process; The offset value inputted to one terminal C of the second comparator 4-3 is set according to a position where a zero value is to be inserted and input.

In this state, the 15-bit binary counter 4-2, which is operated according to the counter load enable CL_E signal and the load enable L_E signal, is operated to display a counter result of the second comparator 4-2. When input to one terminal (D) of the terminal, the comparator 4-2 compares the two input values, and as a result of comparison, the value D input from the 15-bit binary counter 4-2 is the offset value (B). Greater than), changes its output to a 'high' value.

That is, in normal state, 'low' value is always output so that the value input to terminal 0 of mux (4-5) is selected and output, and when 'high' value is output, it goes to terminal 1 of mux (4-5). Selective output of the input value.

This is to output the shift value also latched in the third de-flip flop 4-1 when the 15-bit LSSR 1 sustains one cycle clock.

As described in detail above, although the conventional PN offset generator has an offset identified for each base station, the process of inserting a zero bit is too complicated due to the primary output value, and the system is also difficult to implement.

In addition, since the primary output value is not a commonly used value, it does not need to be output separately. This value complicates the process of extracting the shift output value, and the normal sequence having 2 ¹⁵ -1 periods does not work well. It is not.

Therefore, in order to solve the conventional problem described above, the existing mask circuit can be used as it is, but the circuit for extracting the primary output value is removed, and the circuit for extracting the shift value can be simply configured to reduce the circuit area. In addition, the aim is to provide a PN automatic generator that reduces the cost of device implementation and benefits economically.

That is, in the pseudo-random noise (PN) offset automatic generator used in the digital mobile communication system, the state output value is output when the 'MFSR_CLK' signal is high, and when the 'MFSR_CLK' signal goes low, the entire state for one period. A 15-bit linear shift sequence register (LSSR) for holding '0' bits into the shift output value by holding? A mask circuit for receiving a mask output value output from a mask table and a state output value output from the 15-bit LSSR, and combining the mask output values; A NOR-gate for performing a NOR operation on the shift output value output through the mask circuit and the load enable signal L_E; A four-bit binary counter counting the signal S1 input through the NOR-gate, and a value output from each terminal of the four-bit binary counter to detect a continuous 14th '0' bit. A zero bit insertion circuit having a zero enable (Zero_En) control stage for converting a zero enable (Zero_En) value to a 'low' value at the time point; As an AND-gate which performs an AND processing of a zero enable signal and a system clock outputted from the zero enable control stage, and outputs a 'MFSR_CLK' signal to the 15-bit linear shift sequence register (LSSR). It implements a pseudorandom noise offset automatic generator.

DETAILED DESCRIPTION Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, and the same elements as in the prior art will be described with the same reference numerals.

2 is a circuit diagram of a PN offset automatic generator according to the present invention. When the 'MFSR_CLK' signal is high, the state output value is output. When the 'MFSR_CLK' signal goes low, the previous state is maintained for one cycle. A 15-bit linear shift sequence register (LSSR) 1 for inserting a '0' bit into the slot; A mask circuit (2) which receives a mask output value output from the mask table (5) and a state output value output from the 15-bit LSSR (1), and combines and outputs them; A no-gate (11) for performing a NOR operation on the shift output value output through the mask circuit (2) and the load enable signal (L_E); A zero bit insertion circuit (10) for inserting a zero bit into the bit of the value (S1) output through the NOR-gate (11) and outputting the key; The AND gate 12 processes and processes a system clock and a zero enable signal output from the zero enable control terminal 10-2, thereby performing the 15-bit linear shift sequence register LSSR ( In step 1), the 'MFSR_CLK' signal is output, and the inverter 13 inverts the system clock and inputs it to the zero bit insertion circuit 10.

In addition, the zero bit insertion circuit 10 includes a 4-bit binary counter 10-1 for counting a signal 51 input through the NOR-gate 11; Combining the values output from the respective terminals of the 4-bit binary counter 10-1 to convert the zero enable (Zero_En) value to a 'low' value at the time of detecting the 14th consecutive '0' bit. It consists of a zero enable (Zero_En) control stage 10-2.

Referring to the main operation process of the present invention configured as described above in detail.

The 15-bit linear shift sequence register (LSSR) 1 loads the initial value of the base sequence according to 'MFSK_CLK' when the load enable signal L_E is active, and then shifts the loaded 15 bits. The controller outputs a state output value to the mask circuit 2 according to the 'MFSK_CLK' inputted in the 'high' state.

At the same time, the mask table 5 also outputs the mask output Mask_Out value to the mask circuit 2 according to the off_addr and the mask enable signal Mas_En.

Here, the mask table 5 has 512 addresses equal to the number of offsets 0 to 511, and mask output values corresponding to different offsets are stored for each address.

In this case, the mask output value is a value obtained by calculating 512 different output values through an N × N transformation matrix according to different offsets 0 to 511 based on the initial values of the base sequence.

Accordingly, the mask table 5 continuously outputs the mask output value stored at the specific address to the mask circuit when the mask enable signal is activated after the specific address is designated by the off_address.

In the mask circuit 2 receiving the two signals, 15 terms are combined with each other using an exclusive gate and an exclusive or-gate, and then output as a shifted value. This is the sequence of offsets you want.

However, the period of the value is still 2 ¹⁵ -1 and goes through the zero bit insertion circuit 10 to make it 2 ^15. The process is as follows.

The value output from the mask circuit 2 is again inputted to the NOR-gate 11 to be calculated with the load enable L_E value, and then the 4-bit binary counter 10-1 in the zero bit insertion circuit 10. ) And the clock input to the 4-bit binary counter 10-1 are the inverted values of the system clock through the inverter 13.

When the value S1 is input, the 4-bit binary counter 10-1 counts it. When 14 consecutive '0' bits are detected, the 4-bit binary counter 10-1 is outputted from the 4-bit binary counter 10-1. The value is shifted 'low' by the zero enable control stage 10-2.

When the zero enable value is continuously changed to 'high' and then transitioned to 'low', the output of the end-gate 12 that ANDs the value and the system clock is also changed to 'low'. Accordingly, the 'MFSR_CLK' signal input to the 15-bit LSSR (1) becomes '0' for one cycle, and the previous state is continued for one more cycle, thereby inserting '0' into the bit of the clock that continues. Will be.

As described above, the present invention controls the process of inserting the '0' bit into the shift output value as a zero enable signal, which is very simple to implement and at the same time establishes a more accurate system synchronization, and the system structure is simplified and the installation cost is low. There is an advantage.

As described in detail above, in the present invention, due to the generation of the primary output value in the existing PN offset generator, the system implementation becomes considerably complicated, and the cost is also increased as the system implementation area increases. By simply removing the head value output part and simply inserting the zero bit into the shift output value, the system area is reduced as well as the cost is reduced.

Claims (1)

In the pseudo random noise (PN) offset automatic generator used in the digital mobile communication system, the state output value is output when the 'MFSR_CLK' signal is high, and the state is maintained for one cycle when the 'MFSR_CLK' signal goes low. A 15-bit linear shift sequence register (LSSR) 1 which inserts a '0' bit into the shift output value; A mask circuit (2) which receives a mask output value output from the mask table (5) and a state output value output from the 15-bit LSSR (1), and combines and outputs them; A NOR-gate (11) for performing a NOR operation on the shift output value output through the mask circuit (2) and the load enable signal (L_E); The 4-bit binary counter 10-1 for counting the signal S1 input through the NOR-gate 11 and the value output from each terminal of the 4-bit binary counter 10-1 are combined. Zero-bit insertion circuit having a zero enable (Zero_En) control stage 10-2 for converting a zero enable (Zero_En) value to a 'low' value at the time of detecting the 14th consecutive '0' bits. (10) and; Processes the zero enable (Zero_En) signal and the system clock output from the zero enable (10) control terminal 10-2 to the 'MFSR_CLK' signal to the 15-bit linear shift sequence register (LSSR) 1 The pseudo-random noise offset automatic generator in the digital mobile communication system, characterized in that consisting of the end-gate (12) for outputting the.