KR100259974B1 - Synchronous semiconductor memory device - Google Patents

Abstract

PURPOSE: A synchronous memory device is provided to reduce the current amount dissipated during auto refresh operation. CONSTITUTION: The device includes a memory cell array(100), the first device(200), the second device(300) and a control circuit(400). The memory cell array(100) stores predetermined information. The first device(200) generates an internal signal synchronized with an outer clock signal which is implied from outside. The second device(300) detects whether a column address strobe signal, a row address strobe signal and the outer signal are in activated at the same time to generates an auto refresh signal which is set active during the auto refresh operation synchronized with the internal clock signal. The first device is inactivated during the auto refresh signal generated at the second signal is activated and is activated during the auto refresh signal generated at the second signal is inactivated to generate the internal clock signal. The control circuit(400) controls the peripheral circuits(500) which operate memory cell array manipulation synchronized by the internal clock signal output from the first device.

Description

Synchronous Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device that operates in synchronization with an external clock signal.

는 행 어드레스 스트로브 신호(row address stobe signal)이고, 신호

는 열 어드레스 스트로브 신호(column address stobe signal)이며, 신호(W)는 기입 동작, 독출 동작, 그리고 프리 챠아지 동작시 활성화되는 신호이다.1 and 2 show timing charts of conventional read and write operations and timing charts of auto refresh operations, respectively. The signal clk is an external clock signal applied from the outside, and the signal pclk is an internal clock signal synchronized with the external clock signal clk. signal

Is a row address strobe signal and the signal

Is a column address strobe signal, and signal W is a signal that is activated during a write operation, a read operation, and a precharge operation.

가 활성화된 후 다시 활성화되는 구간 동안에 열 어드레스 스트로브 신호

가 활성화됨에 따라 독출 또는 기입 동작을 수행하게 된다. 그리고, 도 2에 도시된 바와같이, 오토 리프레쉬 동작은 행 어드레스 스트로브 신호

, 열 어드레스 스트로브 신호

, 그리고 신호 (W)가 동시에 활성화될 때 오토 리플레쉬 동작을 알리는 신호 (prfh)이 활성화되는 동안 이루어진다.A synchronous semiconductor memory device, in particular a synchronous dynamic random access memory (hereinafter referred to as a synchronous DRAM) device, is a clock buffer circuit that generates an internal clock signal pclk in synchronization with an external clock signal clk. Synchronize the internal circuits to the external clock signal clk. As shown in Figure 1, the row address strobe signal

Address strobe signal during the interval in which is activated and then activated again

As is activated, a read or write operation is performed. And, as shown in Figure 2, the auto refresh operation is a row address strobe signal

Column address strobe signal

And while the signal prfh indicating the auto refresh operation is activated when the signal W is simultaneously activated.

1 and 2, the internal clock signal pclk continues to toggle during the read operation, the write operation, and the auto refresh operation. In the read and write operation period, the internal clock signal pclk must be continuously toggled in order to control the read and write operations in synchronization with the external clock signal clk. However, in the auto refresh operation section, since no operation is controlled in synchronization with the external clock signal clk after the signal prfh is activated, the internal clock signal is not necessary during this period.

As such, current is consumed as the internal clock signal pclk is continuously generated during the auto refresh operation, and the current is increased in proportion to the external clock frequency. Therefore, unnecessary current is consumed during the auto refresh operation, and the amount thereof becomes larger in the high frequency system.

Accordingly, an object of the present invention is to provide a synchronous semiconductor memory device capable of reducing the amount of current consumed during an auto refresh operation.

1 is a timing diagram of a conventional read and write operation;

2 is a timing diagram of a conventional auto refresh operation;

3 is a block diagram showing a configuration of a synchronous semiconductor memory device according to the present invention;

4A is a detailed circuit diagram of FIG. 3 in accordance with a preferred embodiment of the present invention;

4B is a wiring diagram showing signal wiring for supplying an internal clock signal to other circuits in a chip;

5 is a timing diagram during read and write operations according to an embodiment of the present invention;

6 is a timing diagram during auto refresh operation according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100: cell array 200: clock buffer circuit

300: auto refresh signal generating circuit 400: control circuit

500: circuit block associated with the memory cell

According to one aspect of the present invention for achieving the above object, a memory cell array for storing predetermined information; First means for generating an internal clock signal synchronized with an external clock signal applied from the outside; Second means for detecting whether a row address strobe signal, a column address strobe signal, and an external signal are simultaneously activated to generate an auto refresh signal synchronized with the internal clock signal and activated during an auto refresh operation; The first means is deactivated while the auto refresh signal generated by the second means is activated and is activated when the auto refresh signal is deactivated to generate the internal clock signal; And a control circuit for controlling peripheral circuits that perform an operation related to the memory cell array in synchronization with the internal clock signal output from the first means.

In this embodiment, the first means comprises: decoding means for coding the internal clock signal and the auto refresh signal; Delay means for delaying a signal output from said decoding means for a predetermined time; And a signal output from the delay means as an output driving means for driving the internal clock signal.

In this embodiment, the external signal is activated at least during the auto refresh operation.

In this embodiment, said decoding means comprises: a first inverter string comprising an odd number of inverters connected in series with an output terminal of said second means; A first NAND gate having one input terminal connected to an output terminal of the inverter string and a type force terminal to which the external clock signal is applied; And a first inverter for inverting the output of the first NAND gate.

In this embodiment, the delay means includes: a second inverter column connected to an output terminal of the first inverter and comprising an odd number of inverters; And a second NAND gate having one input terminal connected to an output terminal of the second inverter row, a type force terminal connected to an output terminal of the first inverter, and an output terminal connected to an input terminal of the output driving means. do.

In this embodiment, the output driving means for outputting the internal clock signal includes an odd number of inverters sequentially connected in series between the delay means and the connection point.

Such a device makes it possible to disable the clock buffer circuit during an auto refresh operation.

Reference will now be made in detail with reference to FIGS. 3 to 5 according to an embodiment of the present invention.

Referring to FIG. 3, in the novel synchronous semiconductor memory device of the present invention, an internal clock signal pclk synchronized with an external clock signal clk is generated while an auto refresh operation is performed. The clock buffer circuit 200 using the auto refresh signal prfh is provided so that the clock buffer circuit 200 for the circuit 200 is disabled. This makes it possible to reduce the amount of current consumed during the auto refresh operation.

3 is a block diagram of a synchronous semiconductor memory device according to the present invention.

,

, 및 (W)를 입력받아 내부 클럭 신호(pclk)에 응답하여 상기 신호들

,

, 및 (W)가 동시에 활성화되는지 여부를 검출하여 오토 리프레쉬 동작을 알리는 오토 리프레쉬 신호(prfh)를 발생한다. 그리고, 내부 클럭 신호(pclk)에 동기되는 제어 회로(400)에 의해서 제어되는 메모리 셀 관련 회로 블럭(500)은 메모리 셀 어레이(100)에 저장된 정보를 독출하거나 그것에 특정 정보를 저장하기 위한 것이다.Referring to FIG. 3, a synchronous semiconductor memory device includes a memory cell array 100 for storing information, a clock buffer circuit 200, an auto refresh signal generation circuit 300, a control circuit 400, and a peripheral circuit. Field 500. The clock buffer circuit 200 is for generating the internal clock signal pclk in synchronization with the external clock signal clk. Auto refresh signal generation circuit 300 is a signal

,

, And (W) receive the signals in response to the internal clock signal pclk

,

It detects whether or, and (W) are activated at the same time to generate an auto refresh signal prfh indicating the auto refresh operation. The memory cell related circuit block 500 controlled by the control circuit 400 synchronized with the internal clock signal pclk is for reading information stored in the memory cell array 100 or storing specific information therein.

4A shows a detailed circuit diagram of FIG. 3 in accordance with a preferred embodiment of the present invention.

, 열 어드레스 스트로브 신호

, 및 외부 신호(W)가 동시에 활성화되었는지 여부를 검출하여 내부 클럭 신호(pclk)에 동기된, 오토 리프레쉬 동작을 알리는, 오토 리프레쉬 신호(prfh)를 발생하기 위한 것으로서, 검출 회로(detection circuit) (320), 전달 트랜지스터(MN1), 래치 회로(latch circuit) (340), 그리고 지연 회로(delay circuit) (360)로 이루어져 있다.Referring to FIG. 4A, the auto refresh signal generation circuit 300 may include a row address strobe signal.

Column address strobe signal

And a detection circuit for generating an auto refresh signal prfh, which detects whether the external signal W is simultaneously activated and informs the auto refresh operation synchronized with the internal clock signal pclk. 320, a transfer transistor MN1, a latch circuit 340, and a delay circuit 360.

,

및 (W)를 입력받아 이러한 신호들

,

및 (W)가 동시에 활성화되었는지를 검출하기 위한 것으로서, 인버터들(11)~(15)과 낸드 게이트(G1)로 이루어져 있다. 상기 낸드 게이트(G1)의 입력 단자들은 행 및 열 어드레스 스트로브 신호들

, 및

를 반전시키기 위한 인버터들(I1) 및 (I2)의 출력 단자들과, 신호 (W)를 소정 시간 지연시키기 위해 순차로 직렬로 연결된 2 개의 인버터들(I3) 및 (I4) 중 인버터 (I4)의 출력 단자에 접속되며, 그것의 출력 단자는 인버터(I5)를 통해 전달 트랜지스터(MN1)의 일 입력 단자에 접속되어 있다.The detection circuit 320 is a signal

,

And (W) receive these signals

,

And to detect whether (W) is activated at the same time, consisting of inverters (11) to (15) and the NAND gate (G1). Input terminals of the NAND gate G1 are row and column address strobe signals.

, And

The output terminals of the inverters I1 and I2 for inverting the inverter and the inverter I4 of the two inverters I3 and I4 sequentially connected in series to delay the signal W for a predetermined time. Is connected to one input terminal of the transfer transistor MN1 through an inverter I5.

The transfer transistor MN1 has its internal clock signal pclk applied to its gate and its source-drain channel, i.e. a current path, is connected between the inverter I5 and the latch circuit 340. have. The latch circuit 340 connected between the transfer transistor MN1 and the delay circuit 360 includes inverters I6 and I7 which are mutually latched. The delay circuit 360 has one input terminal connected to an inverter chain having an odd number of inverters I8 to I12 connected in series, and another input terminal connected to a latch circuit 340. The NOR gate G2 has an output terminal for outputting the auto refresh signal prfh.

The clock buffer circuit 200 receives an external clock signal clk and outputs an internal clock signal pclk for controlling logic timing in a chip, and includes a decoding circuit 220 and a delay circuit 240. And an output driving circuit 260. The decoding circuit 220 receives an external clock signal clk through an input input terminal, and connects an odd number of inverters I13 to I15 connected in series to another input terminal, and connects the inverter I16 to the input terminal. The NAND gate G3 has an output terminal connected to the delay circuit 240.

The delay circuit 240 is connected to the NAND gate G4 through which an input terminal has one inverter terminal consisting of three inverters I17 to I19 and directly connected to an output terminal of the decoding circuit 220. Consists of. The output driving circuit 260 consists of inverters I20 to I21 sequentially connected in series between the output terminal of the NAND gate G4 and the connection point N1 for the output of the internal clock signal pclk. . The internal clock signal pclk is used for all control circuits in the chip, so the output load is very large. Accordingly, the inverters I20 to I21 in the output driving circuit 260 are configured to have a high driving capability.

4B shows a signal wiring diagram for supplying an internal clock signal to other circuits in the chip.

The signal wiring method illustrated in FIG. 4B is a structure for minimizing skew of an internal clock signal and is commonly referred to as an H-tree method. RC modeling of signal lines through which the internal clock signal pclk is transmitted according to the H-tree method is illustrated in FIG. 4A. The destination of the internal clock signal pclk, that is, the control circuits and other logics, are connected to the end of the H-tree, respectively.

5 and 6 show timing charts during the auto refresh operation and the read and write operations of the present invention. Based on the operation timing diagrams of FIGS. 5 and 6, the operation of the present invention will be described below with reference to FIGS. 3 to 4.

Referring to FIG. 5, read and write operations of a synchronous DRAM device typically include a sequence of cycles such as row active, read and write operations, row precharge, and other row active. Has and is done. Since the read and write operations are controlled by a clock signal generated inside the chip in synchronization with the external clock signal clk, that is, the internal clock signal pclk, as shown in FIG. The signal pclk must be generated.

6, when the external clock signal clk transitions from a low level to a high level, the signals RAS and CAS are activated at a low level and the signal W ) Is activated to a high level and the auto refresh operation is performed. At this time, the auto refresh signal generation circuit 300 receives the signals RAS, CAS, and W, detects whether they are activated at the same time, and generates a signal prfh indicating the auto refresh operation. The auto refresh signal prfh is a pulse signal maintained at a high level with a certain width. At the same time, the high level signal prfh generated from the auto refresh signal generation circuit 300 is applied to the clock buffer circuit 200. Accordingly, the clock buffer circuit 200 is inactivated by the high level signal prfh, and as shown in FIG. 6, does not generate the internal clock signal pclk during the auto refresh operation. When the auto refresh operation is completed, the clock buffer circuit 200 generates the internal clock signal pclk again in synchronization with the external clock signal clk.

As such, by controlling the clock buffer circuit 300 with the signal prfh activated during the auto refresh operation, the clock buffer circuit 200 is implemented to prevent the toggle of the internal clock signal pclk during the auto refresh operation. It was. That is, when the signal prfh is activated in the auto refresh cycle, the internal clock signal pclk is not generated by deactivating the clock buffer circuit 200 using the signal prfh.

When the auto refresh operation is completed and the signal prfh is inactivated, the clock buffer circuit 200 is activated again to toggle the internal clock signal pclk and prepare to receive a command such as low active. By deactivating the clock buffer circuit 200 during the auto refresh operation, first, the current consumed by the clock buffer circuit 200 can be eliminated, and second, since the internal clock signal pclk does not toggle, Current consumption of the charger / discharger against loading of lines for transmission is prevented, and current consumed by the control circuits synchronized with the third internal clock signal pclk can be prevented.

As described above, the current consumed by it can be prevented by deactivating the clock buffer circuit during the auto refresh operation.

Claims (6)

A memory cell array for storing predetermined information; First means for generating an internal clock signal synchronized with an external clock signal applied from the outside; Second means for detecting whether a row address strobe signal, a column address strobe signal, and an external signal are simultaneously activated to generate an auto refresh signal synchronized with the internal clock signal and activated during an auto refresh operation; The first means is deactivated while the auto refresh signal generated by the second means is activated and is activated when the auto refresh signal is deactivated to generate the internal clock signal; And a control circuit for controlling peripheral circuits which perform an operation related to the memory cell array in synchronization with the internal clock signal output from the first means. 2. The apparatus of claim 1, wherein the first means comprises: decoding means for coding the internal clock signal and the auto refresh signal; Delay means for delaying a signal output from said decoding means for a predetermined time; And an output driving means for receiving the signal output from the delay means and driving the internal clock signal. The synchronous semiconductor memory device of claim 1, wherein the external signal is activated at least during an auto refresh operation. 3. The apparatus according to claim 2, wherein said decoding means comprises: a first inverter string comprising an odd number of inverters connected in series with an output terminal of said second means; A first NAND gate having one input terminal connected to an output terminal of the inverter string and another input terminal to which the external clock signal is applied; And a first inverter for inverting the output of the first NAND gate. 5. The apparatus as claimed in claim 2 or 4, wherein the delay means comprises: a second inverter column connected to an output terminal of the first inverter and comprising an odd number of inverters; A second NAND gate having one input terminal connected to an output terminal of the second inverter string, another input terminal connected to an output terminal of the first inverter, and an output terminal connected to an input terminal of the output driving means. A synchronous semiconductor memory device. 3. The synchronous semiconductor memory device according to claim 2, wherein said output drive means for outputting said internal clock signal comprises an odd number of inverters sequentially connected in series to an output terminal of said delay means.

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