KR0158492B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device in which the output of a column address buffer of a dynamic random access memory (DRAM) operated in nibble mode is controlled to improve flexibility of read and write operations in nibble mode. The memory device is characterized in that the column address signal is controlled and output by a write control signal WEB input from the outside.

Description

Semiconductor memory device

1 is a timing diagram of a lead operation in an extended nibble mode of a conventional semiconductor memory device.

2 is a timing diagram of a write operation in an extended nibble mode of a conventional semiconductor memory device.

3 is a block diagram of a nibble mode dynamic random access memory for carrying out the present invention.

4 is a block diagram of a column address buffer and a column address output control circuit according to the present invention.

5 is a detailed circuit diagram of a reset signal generator according to the present invention.

6, 7 and 8 are operation timing diagrams of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, to control burst data input / output in nibble mode of a dynamic random access memory (DRAM) in response to a transition state of an external write control signal. It relates to a circuit and a method.

In the DRAM operation mode, an operation mode in which a plurality of data is output by one external column address signal is commonly called a nibble mode. The DRAM operating in the nibble mode described above is described in detail on pages 112 to 125 of the Morse memory data book issued by Samsung Electronics Co., Ltd. in 1993, which is also commonly referred to as normal nibble mode. Although only the contents related to the 4-bit nibble are described in the above-described databook, the embodiment of the present invention described below is not limited to 4-bit data access, and a plurality of data may be stored by an external column address strobe signal CASB. It should be noted that all of the modes of operation in which the output of a plurality of data recorded or recorded in a cell are sequentially executed can be applied.

The nibble mode of a typical DRAM can read or write 4 bits of contiguous data by one column address. The first bit of the 4 bits strobes the column address externally in the usual manner, which means that the column address strobe signal CASB latches the column address signal provided from the outside at the time of the first fall, ie, activation. The 4-bit data accessed during the nibble mode is toggling the column address strobe signal CASB from high to low during the period in which the row address strobe signal RASB is activated low by two address bits. The remaining 3 bits are accessed by the counter.

In the nibble mode as described above, 4-bit data must be sequentially accessed when one column address is set, and only 4 bits can be read or written by one column address signal in a row where the row address strobe RASB is activated. As in the page page mode, a problem arises in that four or more data cannot be accessed for the same row address without the precharge time of the row address strobe signal RASB.

In order to solve the problem of the nibble mode DRAM as described above, a technique for extending a column address signal has been developed. This technique is called Extended Nibble mode in the art. One example of such an extended nibble mode is described in detail in US Pat. No. 4,984,271 (hereinafter referred to as a prior patent).

1 and 2 show operation timing diagrams related to leads and lights in the extended nibble mode shown in the above patent. The operation of the extended nibble mode disclosed in the prior art will be briefly described with reference to the lead timing diagram of the extended nibble mode shown in FIG. Now, the above-mentioned normals are accepted by receiving a plurality of column address signals such as column addresses Yi, Yi + 1, and Yi + 2 during the period in which the row address strobe signal RASB is activated, and reading 4-bit data for each column address signal. Resolves an issue that occurred in nibble mode. That is, the problem that the row address strobe signal RASB accepts only one column address signal effectively during the active period is solved.

2 is a write / lead maximum cycle timing diagram of an extended nibble mode. While the row address strobe signal RASB is activated, a plurality of column address signals Yi and Yi + 1 may be received to perform 4 bits read and 4 bits write on each column address signal.

In the extended nibble mode, only one bit of read or 4-bit data can be written by one column address signal, and this operation can be very disadvantageous in a system requiring high performance. Will have For example, when only one bit of data is to be written for the column address signal Yi and four bits of data are to be written to the column address signal Yi + 1, the conventional extended nibble mode reads one bit and then reads 3 bits. The disadvantage of discarding three bits of data by accessing the bits of data to the column address signal Yi + 1.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of continuously executing a write / lead in nibble mode by inputting a new external address in response to toggling of an external write control signal.

Another object of the present invention is to provide a semiconductor memory device which performs input / output corresponding to an operation mode of the write control signal while changing a column address in nibble mode to an external column address in response to toggling of an external write control signal. Is in.

Another object of the present invention is to enable a nibble operation mode in which a plurality of data are sequentially inputted and output in synchronization with a column address strobe signal to stop a moment by toggling of a write control signal, thereby inputting a new external column address in a short time, and operating mode. It is to provide a write control signal change detection circuit for changing the.

The present invention for achieving the above object, relates to a circuit technology for detecting the external write control signal WEB in the extended data out mode of the pipelined nibble (external signal column address strobe signal) External control signal recording control signal WEB is H when CASB is low L H L H, L H L H When toggling is repeated in the state of L, or when the external write control signal is repeatedly toggled as described above when the column address strobe signal CASB is high, the circuit detects only the first transition and confronts the circuits controlling the internal column address. It is characterized in that the operation is performed so that the continuous operation of the nibble mode is smoothly achieved by transferring information.

A semiconductor memory device according to the principles of the present invention

It is characterized by the configuration.

Hereinafter, a detailed description of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a nibble mode DRAM for carrying out the present invention, which is a memory array 12, a control clock generator 14, a refresh controller 16, a refresh counter 18, a row address buffer 20, a column address buffer 24, a column address. It consists of an output control part 22, a row decoder 24, a data input buffer 28 and a data output buffer 30. The function of each part is as follows.

The memory array 12 is a memory block in which a plurality of memory cells are arranged in row and column directions. The control clock generator 14 receives a row address strobe signal RASB, a column address strobe signal CASB, and a write control signal WEB to generate a control clock for controlling reads and writes. The refresh controller 16 generates a refresh control signal for refresh by a control clock output from the control clock generator 14. In addition, the refresh counter 18 connected to the output node of the refresh controller 16 generates a row address selection signal for selecting a row address during the refresh operation by the refresh control signal. Have The row address buffer 20 inputs the control clock generator 14, the output of the row address counter 18, and the address signals A0 to Ai supplied from the outside to output the row address signals. In this case, the output of the row address buffer 20 is determined by an address signal input from an external source during read and write operations, and the operation is determined by the refresh counter 18 during a refresh operation. The column address output controller 22 generates a column address control signal and an internal column address signal for controlling the column address signal input from the outside by the output of the control clock generator 14. The column address buffer 24 generates a column address by inputting a control clock output from the control clock generator 14, a column address output control signal output from the column address output controller 22, an internal column address, and an address input from the outside. The row decoder 24 selects one of a plurality of word lines in the memory array 12 by a row address signal output from the row address buffer 20. The column decoder 26 decodes the column address signal output from the column address buffer 24 to select one column line among the plurality of columns in the memory array 12. The input / output line and the input / output sense amplifier 27 provide a path for writing data stored in the memory cells selected by the row decoder 26 and the column decoder 27 to read or external data, and sense and amplify the data of the input / output line. The data input buffer 28 writes data input from an external data input / output terminal DQ? -DQn to the memory array 12 through the input / output line and the input / output sense amplifier 27. The data output buffer 30 transmits the data of the memory cell to the external data input / output terminals DQ? -DQn by the output control signal OEB and the control signal output from the control clock generator 14.

Most of the configuration of the nibble mode dynamic random access memory shown in FIG. 3 is similar to the operation of a general nibble mode DRAM that is currently generalized, and it can be understood by those skilled in the art without detailed explanation. It is extremely important to note that operations other than those blocks that are integrally involved in this document will not be described. In the following detailed description, only the parts related to the present invention, that is, the configuration of the column address output control unit 22 and the column address buffer 24 and detailed operations thereof will be described.

4 is a detailed block diagram of the column address output controller 22 and the column address buffer 24 according to the present invention. This configuration includes a column control clock generator 32 which generates a column control clock PIC by inverting the column address strobe signal CASB, and detects a transition state of the write control signal WEB in a section in which the column control clock PIC is disabled. A nibble counter 36 which generates a nibble counting signal PEAE by nibbling a reset signal generator 34 which generates a set signal RESET and nibble counting by the input of the reset signal RESET at the same time as the nibble counting of the column control clock PIC. A column address buffer control unit 38 for inputting the column control clock PIC and the address selection signal PEAE to generate a column address control signal PYALB for selecting an external column address / internal column address, and a least significant two-bit column address signal CA0, Input CA0B, CA1, CA1B to input internal column address signals PCA0, PCA1 according to the preset sequence in nibble mode. The generated column address signal generator 40 and the generated internal column address signals PCA0 and PCA1 are latched in an internal register in response to the activation of the column address control signal PYALB, respectively, and stored in the stored column according to the column control clock PIC. The latch circuits 42 and 44 which output column addresses NCA0 and NCA1 and the external address Ai are predecoded by deactivation of the column address control signal PYALB to buffer the column addresses CAi and CAiB, and the latched internal column address signals NCA0 and NCA1. Is composed of a plurality of column address buffers 50 to 54 which pre-decode and buffer the column address buffers 46 and 48 buffering the column addresses CAi and CAiB and the external column address Ai (Cai) by the column address control signal PYALB. The configuration of the column address buffer and the column address output control unit configured as shown in FIG. 4 is described in great detail in the semiconductor memory device invented by the inventor of the present invention and filed in December 1995 by the present applicant. Note that in the present invention, only operations related to the reset signal generator and detailed operations related thereto will be mentioned.

5 is a detailed circuit diagram of the reset signal generator 34 according to the present invention, which is initialized by all states of the PR signal enabled high by activation of the row address strobe signal RASB and is the column address of the write control signal WEB. The reset signal RESET is generated by the combination of the column control clock PIC which is the inverted signal of the strobe signal CASB. That is, the circuit of FIG. 5 detects the toggling state of the write control signal WEB in a state where the column control clock PIC transitions to high or low, and generates a reset signal RESET set to low for a predetermined period.

6, 7 and 8 are the timing diagrams for the operation of FIG. 5, and FIG. 6 is a timing diagram for explaining the operation of the case 1 and the case 2, and FIGS. 7 and 8 are the case 1 And detailed operation waveforms of case 2.

Hereinafter, the operation of FIG. 5 according to the present invention will be described in detail with reference to FIGS. 6, 7, and 8.

An initial potential of each node N1 to N7 of the reset signal generation circuit shown in FIG. 5 is as follows. In the precharge state in which the row address strobe signal RASB, the column address strobe signal CASB, and the write control signals WEB are all high as shown in FIG. 6, the PR signal generated by the row address strobe signal RASB remains low. . The NMOS 94 is turned on by the inverter 92 which inputs the PR signal of the row, and the column control clock PIC generated by the column address strobe signal CASB also has the row state. Therefore, PMOS 106 is turned off by inverter 102 having the column control clock PIC as input, and node N6 is turned low. The potential of the node N6 is latched by the inverters 96 and 98 and makes the node N7 low through the inverters 96 and 100 to keep the reset signal RESET high.

At this time, since the column control clock PIC outputted by the column address strobe signal CASB is low, the output of the inverter 70 which inputs the column control clock PIC is outputted high, and the transmission gate 74 is turned on by the inverter 72 which inputs it. Node N1 and node N2 remain connected. The combination circuit 67 outputs high by the output signals of the inverters 63 and 76 which input the signals of the nodes N1, N2 and the inverted nodes N1B, N2B, and the node N3 receives the output of the combination circuit 67 as an input. Set the level of to low to make the transfer gate 201 turn on. As a result, the potential of the external signal recording control signal WEB is transmitted to the nodes N1 and N2 through the inverters 56 and 58, so that the recording control signals WEB and the nodes N1 and N2 have the same level. At this time, the information to which the recording control signal WEB transitions is transmitted to the nodes N1, N2, N4, N5, and the nodes N4B, N5B, respectively, but the node N6 is in a low state, and thus the reset signal RESET cannot be changed to another state. .

Next, as shown in FIG. 6, the row address strobe signal RASB is activated low and the column address strobe signal CASB is activated low.

The PR signal determined by the row address strobe signal RASB becomes high, and the inverter 92 which inputs the PR signal turns off the NMOS 94 and turns on the PMOS 104. Since the column control clock PIC outputted by the column address strobe signal CASB becomes high after the PR signal goes high, the inverter 102 which inputs the column control clock PIC turns off the PMOS 106 so that the PMOS 104, 106, 108 are turned on. The node N6 is made high and the inverters 96 and 98 latch the potential of the node N6. Thus, the potential of node N7 transitions from low to high through inverters 96 and 100.

The information in which the column address strobe signal CASB transitions from high to low is transferred to the input node of the inverter 70 through the column control clock PIC, and according to the above method, the transmission gate 74 is turned off and the node N1 and the node N2 are open to each other. Thus, the node N2 cannot receive the information of the external recording control signal WEB. In this state, when the recording control signal WEB transitions from high to low as in the case of FIG. 6, the transfer gate 60 is kept in the on state, so that the transition information of the recording control signal WEB is transmitted to the node N1. At this time, the node N1 is low, the node N1B is high, the node N2 is high, and the node N12B is low, and the combination circuit 67 inputs the signals of the four nodes to output a low. Inverter 68 having the output of the combination circuit 67 outputs high to make node N3 high. Therefore, transmission gate 60 is turned on to block node N1 and the external write control signal WEB so that the write control signal WEB is again low → This information is not transmitted to the node N1 even if it transitions high.

Subsequently, when the column address strobe signal CASB transitions from low to high, the column control clock PIC goes low and the node N2, which is in a high state by the transfer gate 74, is turned on by the inverters 70 and 72 which input the column control clock PIC. Transition from high to low is performed by N1. At this time, the transition information is transmitted to nodes N4 and N5 and nodes N4B and N5B, respectively, to pull down the output of the combination circuit 88 to transition the reset signal RESET to low. When the reset signal RESET transitions low by the operation as described above, the inverter 112 turns on the NMOS 110 to transition the node N6 low. Therefore, the reset signal RESET transitions high because it is low by the inverters 96 and 98.

In addition, when the reset signal transitions high, the column address strobe signal CASB remains high. Therefore, the inverter 112 that inputs the column control clock PIC is PMOS 106, so that the inverter 112 that reset signal RESET is input. The NMOS 110 remains off and the PMOS 108 remains on even though the level of the node N6 cannot be changed. Thereafter, when the column address strobe signal CASB transitions from high to low, the node N6 is transitioned to the high state by the inverter 102 and the PMOS 106 which input the column control clock PIC.

When the column address strobe signal CASB transitions from low to high, the nodes N1 and N2 become the same potential and the combination circuit 67 for inputting the signals of the nodes N1, N2, nodes N1B and N2B outputs a high signal. The inverter 68 inputting the high signal output from the combination circuit 67 outputs a low signal to the node N3 to turn on the transmission gate 60. By this operation, the external write control signal WEB and the nodes N1, N2 have the same phase. At this time, even if the recording control signal WEB is shifted to a different level, the nodes N1 and N2 have the same potential, so that the transmission gate 60 is not turned off. Further, even if the level of the external write control signal WEB is shifted while the level of the node N6 is in the low state, the level of the reset signal RESET does not shift. However, when the external control signal WEB transitions while the level of the node N7 is high, the information changes the level of the nodes N2, N4, N5 and N4B, N5B, and eventually the output of the combination circuit 88 transitions to the pull-down state. By doing so, the reset signal RESET transitions to a low state. Subsequently, the reset signals RESET transition to high again by transitioning the nodes N6 and N7 low again by the reset signals RESET, PMOS 106, and NMOS 110.

Therefore, it can be seen that the circuit configured as described above outputs the output of the reset signal RESET in the form of one short pulse whenever the external write control signal WEB is transitioned. The reset pulse RESET generated by the recording control signal WEB by high to low, low to high or more toggling by the above operation is supplied to the nibble counter 36 shown in FIG. At this time, the nibble counter 36 supplies the nibble counting signal PEAE reset and initialized by the reset signal RESET shifted to the low to the column address buffer controller 38.

The column address buffer controller 38 generates a column address control signal PYALB for selecting an external column address signal Ai by the initialized nibble counting signal PEAE, and the column address buffers 46 to 54 connected thereto are inputted from the outside. Is transmitted to the column decoder 26 shown in FIG. 3 so that the read or write operation is executed from an external address.

As described above, in the nibble mode, an external address is selected so that one bit of data can be read immediately by toggling the recording control signal WEB in nibble mode, and then the data of several bits can be written or vice versa. By doing so, the flexibility of the data access operation can be increased.

Claims (2)

A memory array in which a plurality of memory cells are arranged in row and column directions, a row decoder for selecting a word line in the memory array in response to a row address input, and a column line in the memory array in response to a column address input A semiconductor memory having a column decoder to select and a column address buffer which precodes an external address to provide a column address to the column decoder and generates an internal column address which is increased from the input external address by a nibble mode counting control. An apparatus, comprising: detecting a toggling of an external write control signal during an activation and deactivation period of a column address strobe to strobe a column address in the memory cell, and supplying the external address to the column address buffer to supply the external address. Since the semiconductor memory device, it characterized in that the plurality of data is successively data includes a reset pulse generating circuit for control so that the recording or reading. The semiconductor memory device of claim 1, wherein the reset pulse generation circuit is initialized in response to deactivation of the row address strobe signal.