KR100259946B1 - Bus arbitration apparatus and method between two fifos - Google Patents

Abstract

PURPOSE: A common bus sharing method and system is provided to transmit effectively data among a plurality of FIFO(First Input First Output) devices via a common bus interfaced with other board. CONSTITUTION: The system comprises the first FIFO device(113), the second FIFO device(114), a controller(115) and a common bus(116). The first FIFO device(113) stores the data waiting to be transmitted from the first memory(111) to the first memory(117) of the other board. Also the second FIFO device(114) stores the data waiting to be transmitted from the first memory(112) to the first memory(118) of the other board. The controller(115) performs an overall control for allowing the two FIFO devices to share the common bus by checking a data storage amount of the FIFO device and outputting a corresponding signal to the FIFO devices. The common bus(116) is a data path connected between the two FIFO devices(113,114).

Description

Apparatus and method for occupying common bus between two covers

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to selective bus occupancy devices and methods between First Input First Outputs (FIFOs), and more particularly to efficient bus occupancy devices and methods between redundancies implemented with redundancy.

In general, an electronic and communication system device using a microprocessor is a collection of a plurality of processor modules composed of a plurality of boards. In addition, because they operate in conjunction with each other, communication between these boards is a very important problem. The communication method may include communication through a common memory provided in one board, communication through a common bus connected between two boards, and in the present invention, two packets are effectively communicated with one common bus. Data transfer method).

Accordingly, an object of the present invention is to provide an effective common bus occupancy device between a plurality of packets to perform data transfer through another board and a common bus.

In order to achieve the above object, a common bus occupancy control apparatus among a plurality of packs includes: a plurality of packs each storing data received during a processor operation, and every change of the plurality of packs is given priority according to a data storage state. The controller is configured to determine a signal and apply a bus occupancy signal to which the priority is given, and that the signal received the bus occupancy signal occupies the one common bus to transfer data stored in the signal to another board. It features.

Another object of the present invention is to provide a method of effectively occupying a common bus between two packets to communicate with other boards.

In order to achieve the above object, a common bus occupancy method between two packets includes: a first process of outputting a bus occupancy signal to a first captive signal during operation of a processor and transferring data in the first cover to another board through the common bus; Checking whether the bus occupancy request signal of the second cover is generated during the data transmission; and performing a second process if the bus occupancy request signal of the second cover is generated again if the bus occupancy request signal of the second cover is not generated. A third process of outputting a bus occupancy signal to transfer data in the second fabric to another board through the common bus, and checking whether a bus occupancy request signal of the first fabric is generated; When the request signal does not occur, the third process is performed again, and when the bus occupancy request signal of the first cover is generated, the fourth process is performed again. Shall be.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a hardware configuration regarding the occupation of a common bus between two FIFOs according to the present invention.

2 shows the internal data storage of two FIFOs in accordance with each flag state in accordance with the present invention;

3 is a control flow diagram for performing effective bus occupation between two FIFOs in accordance with the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 shows a configuration for transferring two packets to the other board through one data transmission path according to the present invention.

Referring to FIG. 1, the first memory 111 and the second memory 112 store various data. That is, program data, data necessary for executing the program, temporary data generated during the execution of the program, and the like are stored. The first pocket 113 stores data waiting to be transferred from the first memory 111 to the first memory 117 of the opposite board. The second fabric 114 stores data waiting to be transferred from the second memory 112 to the second memory 118 of the opposite board. In this case, the first PPO 113 and the second PPO 114 transmit the data to the other board through one common bus 116 in a FIFO method, that is, a first input first output method. To pass. The regulator 115 controls the overall operation for effective bus occupancy between the two envelopes 113 and 114. That is, the amount of data storage in the two packets 113 and 114 is determined, and a control signal corresponding thereto is outputted to the first packet 113 or the second packet 114. The common bus 116 is one data path connected between two boards. The first memory 117 of the other board stores data transmitted from the first cover 113 through the common bus 116. The second memory 118 of the other board stores data transmitted from the second cover 114 through the common bus 116.

2 is a diagram illustrating data storage amounts of the first and second packets according to the present invention according to each flag state.

Referring to FIG. 2, in the first cover 113, 1a represents an almost full state (APAFn), 1b represents a half full state (AHFn), 1c represents an almost empty state (APAEn), and 1d is completely An empty state (AEFn) is shown.

In the second envelope 114, 2a represents almost full (BPAFn), 2b represents half full (BHFn), 2c represents almost empty (BPAEn), and 2d represents fully empty (BEFn). Indicates.

Hereinafter, an operation according to the present invention will be described in detail based on the configuration of FIGS. 1 and 2.

In FIG. 1, the two packets 113 and 114 continue to store data as long as a processor (not shown) operates, and the amount thereof changes every minute. Therefore, the adjuster 115 should determine the data storage amount of every change in the two packets 113 and 114 to determine which one should be given priority accordingly.

Herein, the priorities given in accordance with the data storage amount (flag state) of the two packets are shown in Table 1 below.

Flag state of the first coat Flag state of the second cover Related Expressions Bus Occupation Completely empty Almost empty Half full Almost cold Completely empty Almost empty Half full Almost cold Y Y A Y N Y Formula (1) B N Y N Y Formula (5) A N Y N N Formula (2) B N N N N N N Formula (6) A N N N N N Y N Formula (3) B N N Y N N N Y N Formula (7) A N N Y N N N Y Y Formula (4) B N N Y Y N N Y Y Formula (8) A

When Table 1 corresponds to Formula (1), the second envelope 114 is almost empty (PAEn) but not completely empty (EFn), and the first envelope 113 is completely empty. Since it is (EFn), the case where the bus occupancy priority is given to the said 2nd cover 114 is shown.

Here, the formulas of Table 1 for assigning bus occupancy priority using flags (EFn, PAEn, HFn, PAFn) indicating the internal storage of the two packets are listed in Table 2 below.

bpri [0] <=! BPAEn && BEFn &&! AEFn; -------- Formula (1) bpri [1] <= BEFn && BPAEn &&! APAEn; -------- Formula (2 bpri [2] <=! BHFn && BPAFn &&AHFn; -------- Formula (3) bpri [3] <=! BPAFn; -------- Formula (4) apri [0 ] <=! APAEn && AEFn & &! BPAEn; -------- Formula (5) apri [1] <= AHFn & & APAEn &&BHFn; -------- Formula (6) apri [2 ] <=! AHFn & & APAFn & &BPAFn; -------- Equation (7) apri [3] <=! APAFn; -------- Equation (8) In this case, the state of the field is 'true' condition, for example, the! BPAEn represents the state that the second envelope is almost empty (PAEn))

In Table 2, bpri [] and apri [] are variables indicating bus occupancy request signals output according to a storage state combination of the two packets. The bpri [] and apri [] have four signals, respectively, and if any one of the four signals becomes “high”, the priority for occupying the bus is given. For example, when the equation (1) is described, the state corresponding to the equation (1) is that the second cover 114 is almost empty (PAEn) but not completely empty (EFn), and the first cover Since 113 is completely empty (EFn), the signal corresponding to the first region of bpri [], that is, bpri [0], becomes “high”, which causes the second cover 114 to stop the bus. You have priority to seize.

In other words, when any one of the signals bpri [0], bpri [1], bpri [2], and bpri [3] goes high, the second packet 114 occupies the bus, and the apri [0] If any one of the signals apri [1], apri [2], and apri [3] becomes high, the first packet 113 occupies the bus.

3 is a diagram illustrating a control process of the regulator 115 according to the present invention.

First, the adjuster 115 determines whether operation of the processor has been started in step 311. In this case, when detecting the start of the operation of the processor, the controller 115 proceeds to step 313, and when it fails to detect the start of the operation of the processor, the controller 115 proceeds to step 321 to enter a standby state. Here, the operation of the processor may be interpreted in various meanings, but in the present invention, it is defined as a time point at which communication with the other board is started. On the other hand, the controller 115, which detects the start of the operation of the processor and proceeds to step 313, outputs a bus occupancy signal to the first picpo 113 so that the first pico 113 having the first priority occupies the bus. do. Therefore, the data stored in the first envelope 113 is transferred to the first memory 117 of the opposite board. The regulator 115 checks whether a bus occupancy request signal of the second cover 114 is generated in step 315. That is, it is checked whether any one of the four bpri [0: 3] signals mentioned above becomes "high". At this time, when the bus occupancy request signal of the second cover 114 occurs, the regulator 115 proceeds to step 317. When the bus occupancy request signal of the second cover 114 does not occur, the adjuster 115 is performed. Return to step 313 to continue to apply the bus occupancy signal to the first cover 113. On the other hand, the controller 115 detects the occurrence of the bus occupancy signal of the second cover 114 and outputs a bus occupancy signal to the second cover 114 by the controller 115 proceeding to step 317. Control to occupy the bus. In step 319, the regulator 115 checks whether a bus occupancy request signal of the first cover 113 is generated. At this time, when the bus occupancy request signal of the first cover 113 occurs, the regulator 115 returns to step 313 to output a bus occupancy signal to the first cover 113, and the first cover 113 When no bus occupancy request signal is generated, the controller 115 returns to step 317 to continuously output a bus occupancy signal to the second cover 114.

That is, as described above, in the present invention, an initial bus occupancy priority is given to the first packet 113 at the start of the processor operation, and then the data storage amount of the second packet 114 is determined by the first packet 113. The bus occupancy priority is converted into the second cover 114 at a point in time where the amount of storage is greater than the storage amount. In other words, the present invention is implemented by repeating the operation of changing the bus occupancy priority at a time when a data storage amount that is not occupied by the bus that occupies the bus increases.

In addition, as an embodiment of the present invention, the contents of steps 313 to 315 of FIG. 3 are represented in a hardware program language as shown in Table 3 below.

Afifo: beginif (| bpri) beginDsm <= Bfifo; endend

Next, the contents ranging from step 317 to step 319 of FIG. 3 are expressed in a hardware program language, as shown in Table 4 below.

Bfifo: beginif (| apri) beginDsm <= Afifo; endend

Here, the Dsm is a variable that designates the cover that has the current bus occupancy rights.

As described above, according to the present invention, the bus occupancy method between the two captives can be effectively adjusted in real time according to the data variation in the captives using a flag indicating the amount of data stored therein. In addition, by considering the importance of data contained in the case, as necessary, the priority of any case is secured so that it is possible to prevent data from being damaged and to securely transmit data.

Claims (3)

In the common bus occupancy control device between a plurality of packs, A plurality of packets each storing data received when the processor is operated, Every change of the plurality of packets is made up of an adjuster for determining the priority is given according to the data storage state, and applying a bus occupancy signal to the priority is given, The device receiving the bus occupancy signal occupies the common bus and transfers data stored in the packet to another board. In the method of occupying a common bus among a plurality of packs, A first process of determining a priority given according to a data storage state of the plurality of targets; And a second process of transferring the data in the priority-applied cover to another board through the common bus and performing the first process again. In the method of occupying a common bus between two guns, A first process of outputting a bus occupancy signal to a first capsule during operation of the processor and transferring data in the first capsule to another board through the common bus; A second process of checking whether a bus occupancy request signal of the second cover is generated during the data transmission, and performing the first process again if it does not occur; When the bus occupancy request signal of the second packet occurs, the bus occupancy signal is output to the second captive to transfer data in the second fabric to another board through the common bus, and the bus occupancy request signal of the first cap A third step of examining whether When the bus occupancy request signal of the first cover does not occur, the third process is performed again, and when the bus occupancy request signal of the first cover occurs, the fourth process is performed again. How to occupy a common bus between two guns.