KR100259140B1 - Incorder and decorder satisfying with mtr condition - Google Patents

Abstract

PURPOSE: An encoder and decoder satisfying a maximum transition run(MTR) condition is provided to remove an error caused by the structure of a bit by satisfying a maximum transition run(MTR) condition when data are stored or read. CONSTITUTION: The relation of output data(C1-C5) and input data(M1-M4) using the Karnaugh map is described as follows. C1 = M2M3 + M2M4, C2 = M3M4 + M1M2M3, C3 = M1, C4 = M3M4 + M1M2M4, and C5 = M3M4 + M2M4. A logical gate constructed by using an OR gate, an AND gate, and a NOT gate codes data inputted by an inherent logical and outputs 5-bit coded data. For example, if M1=0, M2=1, M3=1, and M4=0, the coded output is C1=0, C2=0, C3=0, C4=1, and C5=0. Thus, 4-bit input data(M1-M4) are coded for making 5-bit output data satisfy a maximum transition run(MTR) condition. The process for obtaining coded output data(C1-C5) from 4-bit input data(M1-M4) conversely using the karnaugh map is described as follows. M1 = C3, M2 = C1 + C2C5, M3 = C2 + C1C4 + C3C4, and M4 = C5 + C2C4.

Description

Encoder and Decoder Meet MTR Conditions

1 is a diagram showing the relationship between 4-bit input data of an "encoder and decoder satisfying an MTR condition" and 5-bit coded data satisfying an MTR condition;

2 shows a Carnot map for the design of the present invention " encoder that satisfies the MTR condition "

3 is a logic circuit diagram showing an embodiment of the present invention " encoder that satisfies an MTR condition "

4 is a logic circuit diagram showing an embodiment of a "decoder satisfying an MTR condition" of the present invention;

5 is a diagram illustrating an encoding process and a decoding process of an "encoder and decoder satisfying an MTR condition" of the present invention.

* Explanation of symbols for main parts of the drawings

C1 to C5: output data M1 to M4: input data

The present invention relates to an encoder (ENCODER) and a decoder (DECODER), in particular, when storing digital data on the magnetic recording medium, or read the stored data, because the bit to meet the MTR (MAXIMUM TRANSITION RUN) conditions, This is to ensure that no transition occurs more than three times in succession.

As is well known, one of the errors that occur when reading stored data in a high density magnetic recording medium storing digital data is due to the structure of bits stored in the magnetic recording medium.

In other words, when a bit transition in which a bit transitions from "0" to "1" or "1" to "0" is three or more consecutive times, there is a high probability that an error occurs when data is read. It is true.

The MTR condition refers to a condition that prevents bit transitions from occurring three or more times in succession. For example, the MTR condition refers to a condition such that a bit string such as "101010" or "10101" is not generated.

However, in the conventional data storage system, data is stored / read in a bit string designated by each programming language or a user program, which causes a problem that the MTR condition is not satisfied and an error occurs.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems. Particularly, when storing or reading data, the present invention satisfies the " MTR condition, " which can eliminate an error due to the bit structure by satisfying the MTR condition. Encoder and decoder ".

In order to achieve the above object, the present invention " encoder that satisfies the MTR condition " means that the output of encoded data is C1, C2, C3, C4, C5, and the input is M1, M2, M3, M4. time,

It is configured to satisfy the logic of the technical configuration features.

On the other hand, the present invention "decoder that satisfies the MTR condition", when the output of the decoded data is M1, M2, M3, M4, the input is C1, C2, C3, C4, C5,

It is configured to satisfy the logic of the technical configuration features.

The present invention " encoder and decoder satisfying the MTR condition " is capable of satisfying the MTR condition by storing the data through the encoder and reading the stored data through the decoder. This prevents errors due to three or more consecutive bit transitions.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment according to the technical idea of the present invention "encoder and decoder satisfying the MTR condition" configured as described above in detail as follows.

As is well known, a 4-bit input having 16 codewords can be processed, and the minimum output bit of the codeword that satisfies the MTR condition is 5 bits.

Therefore, in the present embodiment, an encoder having a 4-bit input and a 5-bit output, and a decoder having a 5-bit input and a 4-bit output will be described as an example.

Example 1

Embodiment 1 shows an embodiment according to the technical spirit of the present invention "encoder that satisfies the MTR condition".

FIG. 1 shows 4-bit input data M1 to M4 and 5-bit coded output data C1 to C5 in which the MTR condition is substituted for the input data M1 to M4.

Therefore, as shown in FIG. 2, the relationship between the output data C1 to C5 and the input data M1 to M4 is summarized using the CARRNAUGH MAP as shown in FIG. Is the same as

On the other hand, in FIG. 3, the OR gate, AND gate, and NOT gate are used to satisfy the logic of Formulas [1] to [5].

Each logical gate configured as described above encodes data input by its own logic and outputs 5-bit coded data.

For example, if M1 = 0, M2 = 1, M3 = 1, M4 = 0, the coded output would be C1 = 1, C2 = 0, C3 = 0, C4 = 1, C5 = 0.

Therefore, as shown in FIG. 1, the 4-bit input data M1 to M4 are coded so that the 5-bit output data C1 to C5 satisfy the MTR condition.

Example 2

Embodiment 2 shows an embodiment according to the technical spirit of the present invention "decoder that satisfies the MTR condition".

First, in Fig. 1, equations [6] to [9] are obtained by applying a carno map to the process of obtaining coded output data C1 to C5 from four bits of input data M1 to M4. .

In addition, by using an OR gate, an AND gate, and a NOT gate, as shown in FIG. 4, a circuit is configured to satisfy the logic of the above formulas [6] to [9].

The present invention " decoder that satisfies the MTR condition " is configured to decode input 5-bit data and output 4-bit data by logic unique to the logic gate.

For example, if C1 = 1, C2 = 0, C3 = 0, C4 = 1, C5 = 1, the coded output is M1 = 0, M2 = 1, M3 = 1, M4 = 0.

Therefore, as shown in FIG. 1, the 5-bit encoded data C1 to C5 satisfying the MTR condition are decoded into the 4-bit original data M1 to M4.

In other words, as shown in FIG. 5, when data is stored, the input data is encoded and stored by using the encoder described in the first embodiment so as to satisfy the MTR condition, and when the stored data is read, By decoding the encoded data into the original data through the decoder described in the second embodiment, it is possible to prevent errors due to three or more consecutive bit transitions.

As described above, the present invention "encoder and decoder that satisfies the MTR condition", especially when storing the data, if the data to be stored through the encoder to satisfy the MTR condition, and the decoder to read the stored data, By restoring the encoded data through, it is possible to prevent an error due to three or more consecutive bit transitions.

Claims (2)

When the output of encoded data is C1, C2, C3, C4, C5, and its input is M1, M2, M3, M4, Encoder satisfying the MTR condition, characterized in that configured to satisfy the logic of. When the output of the decoded data is M1, M2, M3, M4, and its input is C1, C2, C3, C4, C5, And a decoder that satisfies the MTR condition.