KR100258605B1 - Structure of semiconductor l.o.c package - Google Patents
Structure of semiconductor l.o.c package Download PDFInfo
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- KR100258605B1 KR100258605B1 KR1019950036140A KR19950036140A KR100258605B1 KR 100258605 B1 KR100258605 B1 KR 100258605B1 KR 1019950036140 A KR1019950036140 A KR 1019950036140A KR 19950036140 A KR19950036140 A KR 19950036140A KR 100258605 B1 KR100258605 B1 KR 100258605B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- AOSZTAHDEDLTLQ-AZKQZHLXSA-N (1S,2S,4R,8S,9S,11S,12R,13S,19S)-6-[(3-chlorophenyl)methyl]-12,19-difluoro-11-hydroxy-8-(2-hydroxyacetyl)-9,13-dimethyl-6-azapentacyclo[10.8.0.02,9.04,8.013,18]icosa-14,17-dien-16-one Chemical compound C([C@@H]1C[C@H]2[C@H]3[C@]([C@]4(C=CC(=O)C=C4[C@@H](F)C3)C)(F)[C@@H](O)C[C@@]2([C@@]1(C1)C(=O)CO)C)N1CC1=CC=CC(Cl)=C1 AOSZTAHDEDLTLQ-AZKQZHLXSA-N 0.000 claims description 6
- 229940126657 Compound 17 Drugs 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000007906 compression Methods 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 230000001737 promoting effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 4
- 230000006835 compression Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
제1도는 일반적인 L. O. C 패키지 구조를 나타내는 것으로Figure 1 shows a typical L. O. C package structure
a도는 정단면도이고,a degree is a sectional view,
b도는 평단면도.b is a cross-sectional view.
제2도는 본 발명에 의한 L. O. C 패키지 구조를 나타내는 것으로,2 shows the L. O. C package structure according to the present invention,
a도는 본딩패드가 중심부에 부착된 상태를 나타낸 정단면도이고,a is a front sectional view showing a state where the bonding pad is attached to the center part,
b도는 본딩패드가 외곽에 부착된 상태를 나타내는 정단면도.b is a front sectional view showing a state in which a bonding pad is attached to the outside.
제3도는 본 발명에 의한 본딩패드의 구조를 나타내는 것으로, 제3도는 칩 상부에 접착전의 상태를 나타낸 요부 단면도이고, 제3도는 칩 상부에 접착후의 상태를 나타내는 요부 단면도.3 is a sectional view showing the structure of the bonding pad according to the present invention, and FIG. 3 is a sectional view of the main part showing the state before bonding to the upper part of the chip, and FIG. 3 is a sectional view of the main part showing the state after bonding to the upper part of the chip.
도 4는 본 발명에 의한 다른 실시예를 나타내는 것으로,Figure 4 shows another embodiment according to the present invention,
a도는 정단면도이고,a degree is a sectional view,
b도는 평단면도.b is a cross-sectional view.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : L. O. C 패키지 11 : 칩10: L. O. C Package 11: Chip
13 : 범프 14 : 폴리머(Polymer)13: bump 14: polymer
15 : 본딩패드 16 : 리드15: bonding pad 16: lead
17 : 컴파운드17: compound
본 발명은 반도체 L. O. C(Lead On Chip) 패키지 구조에 관한 것으로, 특히 L. O. C 패키지를 제작시 칩 상부에 설치되는 본딩패드의 위치를 자유롭게 설정할 수 있고, 또한 패키지의 두께를 얇게 제작할 수 있도록 하기 위하여 패키지의 내측으로 위치하게 되는 수개의 리드 하부에 접착하게 되는 본딩패드를 이방성 전도 필름(Anistoropic Conductive Film)으로 형성하고, 상기 본딩패드의 하부에 위치하게 되는 칩(Chip) 상부로는 회로설계에 입각한 범프(Bump)를 형성하여 상호 부착시키므로 패키지를 제작시 본딩패드의 위치를 자유롭게 설정할 수 있으며, 패키지의 두께 역시도 최소화 할 수 있는 반도체 L. O. C(Lead On Chip) 패키지 구조에 관한 것이다.The present invention relates to a semiconductor lead on chip (LO C) package structure, and in particular, in order to be able to freely set the position of the bonding pad installed on the chip when manufacturing the LO C package, and to make the thickness of the package thinner. Bonding pads, which are bonded to the lower parts of the leads, which are positioned inside the package, are formed of an anisotropic conductive film, and the upper part of the chip, which is located below the bonding pads, is based on a circuit design. The present invention relates to a semiconductor lead-on-chip (LOC) package structure that can freely set the position of a bonding pad when manufacturing a package because the bumps are formed and attached to each other.
일반적으로 종래의 반도체 L. O. C 패키지 구조는 제1a, b도에 도시된 바와 같이 패키지의 내측으로 위치하게 되도록 양측으로 수개 형성되는 리드 하부에 본딩패드(5)를 접착형성하여 칩(1) 상부에 중앙 일정위치로 중앙에 소정의 이격거리를 형성하도록 접착 설치되어 있다.In general, in the conventional semiconductor LO C package structure, as shown in FIGS. 1A and 1B, bonding pads 5 are bonded to the lower parts of leads formed on both sides so as to be positioned inside the package. The adhesive is provided so as to form a predetermined separation distance in the center to the center constant position.
또한, 상기의 중앙에 형성된 칩(1)과 리드(6)를 회로적으로 상호 연결시켜 주기위한 와이어(4)가 본딩작업에 의해 연결형성되어 있으며, 상기 구성물들의 외곽으로는 컴파운드(17)로 성형되어 있다.In addition, a wire 4 for interconnecting the chip 1 and the lead 6 formed in the center of the circuit is interconnected by a bonding operation, and the compound 17 is formed outside of the components. It is molded.
한편, 상기 패키지의 컴파운드(17)된 부위의 내측으로 위치하게 되는 리드(6)는 와이어(4) 본딩 공정상의 편의등을 용이하게 하기 위해 내측으로는 하향 경사지도록 형성되어 구성되어 있다.On the other hand, the lid 6 positioned inside the compound 17 portion of the package is formed to be inclined downward inward to facilitate convenience in the bonding process of the wire 4.
그러나, 이와 같이 구성되는 본딩패드(5)가 중앙부에 위치해야만 하는 문제로 제작상의 한정적인 제약이 초래되었고, 또한 구조적으로 얇고 소형화되가는 패키지의 추세를 따라 가기에는 한계성이 야기되었으며, 와이어(4)를 연결수단으로 사용하므로 인한 전기적인 저항손실등이 문제시되었다.However, a problem in that the bonding pads 5 configured as described above should be located at the center part has caused limitations in manufacturing, and also has limitations in keeping with the trend of a package that is structurally thin and miniaturized. Electrical resistance loss due to the use of the
따라서, 본 발명은 상기와 같은 문제점들을 감안하여 안출한 것으로, 칩의 상부에 설치되는 본딩패드의 배치를 자유롭게 하여도 하부에 설치되는 칩과의 상호 회로적연결이 가능하도록 하여 칩 설계시에 칩 기능을 최대한으로 활용할 수 있는 자유로운 본딩패드의 설계를 할 수 있으며, 또한 와이어 본딩공정이 사라지게 되므로 제작공정과 시간이 단축됨은 물 패키지의 두께를 최소화 할 수 있고, 와이어를 통한 전기적 저항손실을 미연에 방지 할 수 있는 반도체 L. O. C 패키지 구조를 제공하는데 그 목적이 있다.Accordingly, the present invention has been made in view of the above problems, and even when the bonding pads provided on the upper part of the chip are free to be arranged, the circuits can be interconnected with the chip installed on the lower side. Free bonding pads can be designed to make the best use of the function, and the wire bonding process is eliminated, which reduces the manufacturing process and time, thereby minimizing the thickness of the water package and reducing the electrical resistance loss through the wire. The purpose is to provide a semiconductor LO C package structure that can be prevented.
이러한, 본 발명의 목적은 내측 중앙에 칩을 구비하고 상기 칩 상부 양측으로 칩과의 부착이 용이토록 하부에 본딩패드를 형성한 수개의 리드를 일체로 몰드성형한 반도체 L. O. C 패키지 구조에 있어서, 상기 본딩패드를 이방성 전도필름으로 형성하여 내측으로 위치되는 수개의 리드 하부에 부착시켜 상부에 회로설계에 입각한 수개의 범프를 일체로 형성한 칩에 열압착을 이용하여 상호 회로적으로 연결형성되도록 구성하여 달성될 수 있다.The object of the present invention is to provide a semiconductor LO C package structure in which a plurality of leads having a chip in the inner center and bonding pads formed on the lower side of the chip on both sides of the chip to easily bond with the chip are integrally molded. The bonding pad is formed of an anisotropic conductive film and attached to a lower portion of the lead positioned inwardly so that the bonding pads are interconnected to each other by using thermocompression bonding on a chip integrally formed with several bumps based on a circuit design. Can be achieved by configuration.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 좀더 구체적으로 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 제3도와 제4도에 도시된 바와 같이 내측 중앙에 칩(11)을 형성하고 상기 칩(11) 상부 양측으로 하부에 상기 칩(11)과 부착이 용이토록 본딩패드(15)를 형성한 수개의 리드(16)가 일체로 컴파운드(17) 성형되어 있다.As shown in FIG. 3 and FIG. 4, the chip 11 is formed at the inner center, and the bonding pad 15 is easily attached to the chip 11 at both sides of the upper part of the chip 11. The several leads 16 formed are integrally molded with the compound 17.
한편, 상기 리드(16)와 칩(11)의 상호 부착을 용이토록 하기 위해 형성된 본딩패드(15)는 열압착시 압착된 부분은 열로 인해 폴리머(14)(Polymer)가 녹게되어 상호간의 통전상태를 유지할 수 있으며 그 외의 부위는 절연상태를 유지할 수 있도록 형성된 이방성 전도필름(12)으로 형성되어 있다.On the other hand, the bonding pad 15 formed to facilitate the mutual attachment of the lead 16 and the chip 11, the pressed portion during the thermal compression is the polymer 14 (Polymer) is melted due to the heat is energized between each other The other portions are formed of the anisotropic conductive film 12 formed to maintain the insulating state.
그리고, 상기 컴파운드(17)된 부위의 내측으로 위치하게 되는 리드(16)는 외측으로 하향경사지게 형성되어 있다.In addition, the lid 16 positioned to the inside of the compound 17 is formed to be inclined downward to the outside.
또한, 상기 본딩패드(15)의 하부에 위치하게 되는 칩(11)의 상부로는 회로설계에 입각한 수개의 범프(13)가 상부에 형성된 본딩패드(15)와 대향되게 일체로 형성되어 상호 열압착을 이용하여 연결구성되어 있다.In addition, a plurality of bumps 13 based on a circuit design may be integrally formed to face the bonding pads 15 formed on the upper portion of the chip 11 positioned below the bonding pads 15. It is connected by heat compression.
이와 같이 구성되는 본체 L. O. C 패키지 구조는 제3도와 제4도에 도시된 바와 같이 상기 본딩패드(15)를 열압착시 압착된 부분, 즉 칩(11) 상부에 회로설계에 입각하여 수개 돌출형성된 범프(13) 부위로 내부에 형성되어 있는 수개의 폴리머(14)가 녹으면서 밀도가 집중되어 통전상태를 유지할 수 있도록 연결설치되며 그외의 부위는 절연상태를 유지할 수 있도록 형성된 이방성 전도필름(12)으로 형성하여 줌으로서 칩(11)의 상부에 설치되는 칩(11)과의 상호 회로적 연결이 용이하도록 할 수 있고, 그러므로 칩(11) 설계시에 칩(11) 기능을 최대한으로 활용할 수 있는 자유로운 설계를 할 수 있도록 한 것이다.As shown in FIG. 3 and FIG. 4, the main body LO C package structure configured as described above has a plurality of protrusions formed on a portion of the bonding pad 15 that is pressed during thermocompression, that is, on the chip 11 based on a circuit design. Anisotropic conductive film 12 formed so as to maintain a state of conduction while other polymers 14 formed inside the bump 13 are melted and concentrated at a density. It is possible to facilitate the mutual circuit connection with the chip 11 installed on the top of the chip 11 by forming a zoom, and thus can maximize the function of the chip 11 when designing the chip 11. It is designed to allow free design.
또한, 와이어본딩공정이 자연적으로 사라지게 되고 패키지(10)의 컴파운드(17)된 부위의 내측으로 위치하게 되는 리드(16)를 외측으로 하향경사지게 절곡형성하여 줌으로 패키지의 두께를 최소화 할 수 있음은 물론이고 전기적 저항손실 또한 최소화 할 수 있도록 한 것이다.In addition, the wire bonding process disappears naturally, and the lead 16, which is positioned inside the compound 17 portion of the package 10, may be bent downwardly to the outside to zoom out to minimize the thickness of the package. Of course, the electrical resistance loss is also minimized.
한편 제4a, b도는 본 발명의 다른 실시예를 나타낸 도면으로서 이방성 전도필름(12)으로 이루어진 본딩패드(15)를 일체로 형성하여 리드(16)와 칩(11)을 상호 연결제작하는 것도 바람직할 것이다.Meanwhile, FIGS. 4A and 4B show another embodiment of the present invention, in which bonding pads 15 made of anisotropic conductive films 12 are integrally formed to interconnect the leads 16 and the chips 11. something to do.
또한, 상기 이방성 전도필름(12)으로 이루어진 본딩패드(15)의 기능을 최대화하기 위해서는 칩(11) 상부로 돌출 형성된 범프(13)의 높이를 본딩패드(15) 두께의 약 80% 이하로 형성하는 것이 바람직할 것이다.In addition, in order to maximize the function of the bonding pad 15 made of the anisotropic conductive film 12, the height of the bump 13 protruding from the top of the chip 11 is formed to about 80% or less of the thickness of the bonding pad 15. It would be desirable to.
따라서, 앞에서 설명한 바와 같이 본 발명은 반도체 L. O. C 패키지를 구성하고 있는 본딩패드를 칩 상부의 중심부상에 위치시켜야만 제작이 가능하였던 제작상의 한정적인 제약이 따랐던 문제와 와이어를 상호의 연결매체로 사용하므로 인해 야기되었던 패키지를 얇고 소형화 시키지 못하게 되는 제작상의 한계성 및 전기적인 저항손실등과 같은 문제등을 상기 L. O. C 패키지를 형성하는데 있어 리드와 칩을 상호연결시키는 본딩패드를 이방성 전도필름으로 형성하여 내측으로 위치되는 수개의 리드 하부에 부착시켜 상부에 회로설계에 입각한 수개의 범프를 일체로 형성한 칩에 열압착을 이용하여 상호 연결형성되도록 하여 칩 상부에 설치되는 본딩 패드의 배치를 자유롭게 하여도 하부에 연결설치되는 칩과의 상호회로적 연결이 가능하도록 하여 칩 설계시에 칩 기능을 최대한으로 활용할 수 있는 자유로운 본딩패드의 설계를 할 수 있고, 또한 와이어 본딩공정이 사라지게 되므로 제공공정과 시간이 단축됨으로 생산량을 향상시킬 수 있으며, 또한 전기적인 저항손실등을 최소화 할 수 있는 효과를 가지게 되는 것이다.Therefore, as described above, the present invention uses wires as interconnecting mediums and problems that are limited by manufacturing limitations that could be produced only when the bonding pads constituting the semiconductor LO C package were placed on the center of the upper portion of the chip. Bonding pads that interconnect the leads and chips in forming the LO C package, such as manufacturing limitations and electrical resistive losses, which cannot be made thin and small due to the package, are formed by anisotropic conductive film. It is attached to the lower part of the lead which is located so that the interconnection is formed by thermocompression on the chip integrally formed with several bumps based on the circuit design on the upper part. Chip to enable mutual circuit connection with the chip It is possible to design a free bonding pad that can make full use of the chip function in time, and also because the wire bonding process disappears, the production process and time can be shortened, the production can be improved, and the electrical resistance loss can be minimized. It will have the effect.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950036140A KR100258605B1 (en) | 1995-10-19 | 1995-10-19 | Structure of semiconductor l.o.c package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950036140A KR100258605B1 (en) | 1995-10-19 | 1995-10-19 | Structure of semiconductor l.o.c package |
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| Publication Number | Publication Date |
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| KR970023905A KR970023905A (en) | 1997-05-30 |
| KR100258605B1 true KR100258605B1 (en) | 2000-06-15 |
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| KR1019950036140A KR100258605B1 (en) | 1995-10-19 | 1995-10-19 | Structure of semiconductor l.o.c package |
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