KR100256254B1 - Semiconductor element and manufacturing method having element isolation layer - Google Patents

Semiconductor element and manufacturing method having element isolation layer Download PDF

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KR100256254B1
KR100256254B1 KR1019970077870A KR19970077870A KR100256254B1 KR 100256254 B1 KR100256254 B1 KR 100256254B1 KR 1019970077870 A KR1019970077870 A KR 1019970077870A KR 19970077870 A KR19970077870 A KR 19970077870A KR 100256254 B1 KR100256254 B1 KR 100256254B1
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semiconductor substrate
source
trench
forming
device isolation
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KR1019970077870A
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Korean (ko)
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KR19990057791A (en
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양정윤
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are to remove a floating body effect, to decrease a source/drain junction capacitance, to prevent an occurrence of punch through phenomenon and to discharge a heat generated at the junction. CONSTITUTION: The first semiconductor substrate(201) is selectively etched to form a T-shape trench of which an upper portion is wider than a lower portion. The trench is filled with a field oxide(207). The second semiconductor substrate(208) is bonded to a front surface of the resultant surface of the first semiconductor substrate. A rear surface of the first semiconductor substrate is ground until the lower surface of the field oxide is exposed. A source/drain junction(211) is formed to a certain depth from the ground surface of the first semiconductor substrate. A gate(210) is formed on the ground surface of the first semiconductor substrate between the source and drain.

Description

접합 하부로 확장된 소자분리절연막을 갖는 반도체소자 및 그 제조방법Semiconductor device and device manufacturing method having device isolation insulating film extended to junction

본 발명은 반도체소자에 관한 것으로, 특히 접합 하부로 확장된 소자분리절연막을 갖는 반도체소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a device isolation insulating film extended under a junction and a method of manufacturing the same.

잘 알려진 바와 같이, 반도체 소자가 점차 고집적화 되어감에 따라 소자 특성 향상을 위하여 SOI(Silicon on insulator) 기판을 사용하고 있다. SOI 기판은 기판 지지역할을 하는 제1실리콘층과 활성영역을 제공하는 제2실리콘층을 구비하며, 그 사이에 매몰산화막을 갖는다.As is well known, as semiconductor devices are increasingly integrated, silicon on insulator (SOI) substrates are used to improve device characteristics. The SOI substrate has a first silicon layer serving as the substrate region and a second silicon layer providing the active region, with an buried oxide film therebetween.

도 1은 종래의 반도체소자 구조를 나타내는 단면도로서, 제1실리콘층(11)과 매몰산화막(12) 및 제2실리콘층(13)으로 이루어진 SOI 기판 상에 LOCOS(local oxidation)방법 등의 소자분리 공정에 의해 소자분리절연막(14)을 형성하여 활성영역을 정의한 후, 활성영역을 게이트(15)와 소스/드레인 접합(16)을 형성한 상태로서, 이러한 종래의 반도체소자는 소스/드레인 접합 커패시턴스(source/drain junction capacitance)가 크며 펀치스루(punch through)현상과 차단된 매몰산화막(12)에 의한 열 발생을 방출함에 있어서의 어려움과 실리콘 기판의 플로팅(floating)을 위해 소자분리절연막(14)을 매몰산화막(12)과 떨어지도록(도면부호 17) 형성하여야 한다는 단점이 있다.FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device structure, in which a device such as a local oxidation (LOCOS) method is isolated on an SOI substrate including a first silicon layer 11, an buried oxide film 12, and a second silicon layer 13. After the device isolation insulating film 14 is formed by the process to define the active region, the active region is formed with the gate 15 and the source / drain junction 16. Such a conventional semiconductor device has a source / drain junction capacitance. device isolation insulating film 14 for difficulty in releasing heat generated by the buried oxide film 12 blocked with a punch through phenomenon and having a large source / drain junction capacitance, and for floating the silicon substrate. Has a disadvantage in that it must be formed to be away from the buried oxide film 12 (17).

본 발명은 상기한 문제점을 해결하기 위하여 안출된 것으로서, 플로팅 바디 이펙트(floating body effect)를 없앨 수 있고, 소스/드레인 접합 커패시턴스를 감소시키며, 펀치스루 현상을 방지할 수 있고 소스/드레인 접합에서 발생한 열을 방출할 수 있는, 반도체 소자 및 그 제조 방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can eliminate floating body effects, reduce source / drain junction capacitance, prevent punch-through and occur in source / drain junctions. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can emit heat.

도 1은 종래의 반도체소자 구조를 나타내는 단면도.1 is a cross-sectional view showing a conventional semiconductor device structure.

도 2a 내지 도 2h는 본 발명의 일실시예에 따른 반도체소자 제조 공정도.2A through 2H are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

201, 208 : 반도체기판 202 : 패드 산화막201 and 208: semiconductor substrate 202: pad oxide film

203 : 질화막 204, 206 : 트렌치203: nitride films 204 and 206: trench

205 : 산화막스페이서 207 : 소자분리 산화막205: oxide film spacer 207: device isolation oxide film

210 : 게이트 211 : 소스/드레인 접합210: gate 211: source / drain junction

상기 목적을 달성하기 위한 본 발명의 반도체소자는, 반도체 기판; 각각 서로 고립되어 국부적으로 상기 반도체 기판 표면으로부터 일정 깊이로 형성되어 그 사이에 위치한 상기 반도체기판 영역에 채널을 유기하기 위한 소스 및 드레인 접합; 상기 채널을 유기하기 위한 상기 반도체 기판 영역 상에 형성된 게이트; 및 상기 게이트 및 상기 소스 및 드레인 접합으로 이루어진 트랜지스터를 타 소자와 분리하기 위하여 상기 소스 및 드레인 접합의 각 외측에 국부적으로 형성되며 상기 소스 및 드레인 접합의 하부까지 확장되어 형성된 소자분리절연막을 포함하여 이루어진다.The semiconductor device of the present invention for achieving the above object is a semiconductor substrate; Source and drain junctions each isolated from one another and locally formed to a predetermined depth from the surface of the semiconductor substrate to induce channels in the semiconductor substrate region located therebetween; A gate formed on said semiconductor substrate region for inducing said channel; And a device isolation insulating film formed locally on each outer side of the source and drain junctions and extending to a lower portion of the source and drain junctions to separate the gate and the transistor including the source and drain junctions from other devices. .

또한 본 발명의 반도체소자 제조 방법은, 제1 반도체기판을 선택적으로 식각하여 그 상부를 넓고 그 하부는 좁은 T형 트렌치를 형성하는 단계; 상기 트렌치내를 매립한 소자분리절연막을 형성하는 단계; 전면에 제2 반도체기판을 본딩하는 단계; 상기 소자분리절연막의 탑 표면이 노출되도록 상기 제1 반도체기판 뒷면을 연마하는 단계; 및 상기 연마된 제1 반도체기판 뒷면에 게이트와 소스/드레인 접합을 형성하는 단계를 포함하여 이루어진다.In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of selectively etching the first semiconductor substrate to form a wide T-type trench in the upper portion and the lower portion; Forming a device isolation insulating film filling the trench; Bonding a second semiconductor substrate to the front surface; Polishing a back surface of the first semiconductor substrate to expose the top surface of the device isolation insulating film; And forming a gate and a source / drain junction on the back side of the polished first semiconductor substrate.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Shall be.

도 2h는 본 발명의 일실시예에 따른 반도체 소자 구조를 나타내는 단면도로서, 본 발명의 반도체 소자에서, 소스 및 드레인 접합(211)이 각각 서로 고립되어 국부적으로 상기 반도체 기판 표면으로부터 일정 깊이로 형성되어 그 사이에 위치한 상기 반도체기판에 영역에서 채널을 유기한다. 게이트(210)는 상기 채널을 유기하기 위한 상기 반도체 기판 영역 상에 형성된다. 소자분리절연막(207)은 상기 게이트(210) 및 상기 소스 및 드레인 접합(211)으로 이루어진 트랜지스터를 타 소자(트랜지스터)와 분리하기 위하여 상기 소스 및 드레인 접합의 각 외측에서 국부적으로 형성된다. 그리고, 소자분리절연막(207)은 상기 소스 및 드레인 접합의 하부까지 확장되어 형성되며 상기 채널을 유기하기 위한 상기 반도체 기판 영역의 하부(도면의 212)에서 서로 분리된다. 또한 상기 소자분리절연막의 확장 부위는 상기 소스 및 드레인 접합(211) 하부와 맞닿는다. 기술되지 않은 기타 도면부호는 이후의 제조 공정 설명에서 구체적으로 언급될 것이다.2H is a cross-sectional view showing a semiconductor device structure according to an embodiment of the present invention, in which the source and drain junctions 211 are isolated from each other and are locally formed to a predetermined depth from the surface of the semiconductor substrate. A channel is induced in the region on the semiconductor substrate located between them. A gate 210 is formed on the semiconductor substrate region for inducing the channel. A device isolation insulating layer 207 is formed locally at each outside of the source and drain junctions in order to separate the transistor including the gate 210 and the source and drain junctions 211 from other devices (transistors). In addition, the device isolation insulating layer 207 is formed to extend down to the bottom of the source and drain junctions and is separated from each other at the bottom of the semiconductor substrate region (212 of FIG. 2) to induce the channel. In addition, an extended portion of the device isolation insulating layer may contact a lower portion of the source and drain junction 211. Other reference numerals, which are not described, will be specifically mentioned in the following description of the manufacturing process.

본 발명을 종래기술(도 1)과 비교하여 본다면 본 발명은 소자분리를 위한 산화막(207)이 소스/드레인 접합(211)의 아래까지 확장되어 있으므로, 소스/드레인의 접합 커패시턴스(junction capacitance)가 줄어든다. 또한, 벌크 펀치스루(bulk punch-through)도 막을 수 있다.When comparing the present invention with the prior art (FIG. 1), in the present invention, since the oxide film 207 for device isolation is extended under the source / drain junction 211, the junction capacitance of the source / drain is increased. Decreases. In addition, bulk punch-through can be prevented.

그리고 종래와 같은 매몰산화막은 반도체기판을 플로팅(floating)할 수가 없어서 소자분리절연막을 매몰산화막과 일정 간격으로 띄워야 하는(도 1의 17) 단점이 있으나, 본 발명에서는 이웃하는 소자분리절연막이 서로 분리되어 있으므로, 이 분리된 영역(212)으로 반도체기판을 플로팅(floating)할 수 있으므로 플로팅 바디 이펙트(floating body effect)를 없앨 수 있다. 또한 이 분리된 영역(212)으로 소자구동시 발생되는 열을 방출할 수 있으므로 소자 신뢰성을 향상시킬 수 있다.In addition, the conventional buried oxide film has a disadvantage in that it is not possible to float the semiconductor substrate, so that the device isolation insulating film must be spaced apart from the investment oxide film (17 in FIG. 1). However, in the present invention, adjacent device isolation insulating films are separated from each other. Since the semiconductor substrate can be floated into the separated region 212, the floating body effect can be eliminated. In addition, since the heat generated during driving of the device may be discharged to the separated region 212, device reliability may be improved.

도 2a 내지 도 2h는 본 발명의 일실시예에 따른 반도체소자 제조 공정도이다.2A to 2H are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

도 2a를 참조하면, 반도체기판(201)위에 패드산화막(202)과 질화막(203)을 증착하고, 마스크 작업을 통해 소자분리영역의 상기 질화막, 패드산화막 및 반도체기판의 일부두께를 각각 식각하여 1차 트렌치(trench)(204)를 형성한다.Referring to FIG. 2A, a pad oxide film 202 and a nitride film 203 are deposited on a semiconductor substrate 201, and a partial thickness of the nitride film, the pad oxide film, and the semiconductor substrate in the device isolation region is etched through a mask operation. A tea trench 204 is formed.

이어서, 도 2b와 같이 상기 식각에 의해 형성된 수직구조 측벽에 산화막스페이서(205)를 형성시키고, 도 2c 와 같이 산화막스페이서(205)와 질화막(203)을 마스크로하여 다시 반도체기판(201)을 일부두께로 식각하여 2차 트렌치(206)를 형성한다.Next, as shown in FIG. 2B, an oxide film spacer 205 is formed on the sidewall of the vertical structure formed by the etching, and the semiconductor substrate 201 is partially formed by using the oxide film spacer 205 and the nitride film 203 as masks as shown in FIG. 2C. The second trench 206 is formed by etching to a thickness.

계속해서, 도 2d와 같이 전체구조 상부에 소자분리용 산화막(207)을 증착한 다음, 도 2e와 같이 반도체기판(201)의 탑 표면이 노출되어 1차 및 2차 트렌치 내부에만 산화막(207, 205)이 매립되도록 전면 식각을 실시한다. 예컨대 질화막이 노출될때까지 연마(polishing)하고, 질화막과 패드산화막을 식각하는 방법을 사용한다.Subsequently, as shown in FIG. 2D, the oxide layer 207 for device isolation is deposited on the entire structure. Then, as shown in FIG. 2E, the top surface of the semiconductor substrate 201 is exposed to expose the oxide layer 207 only in the first and second trenches. 205) is subjected to full surface etching. For example, a method of polishing until the nitride film is exposed and etching the nitride film and the pad oxide film is used.

산화막스페이서(205)는 소자분리를 위한 산화막(207)과 같이 소자분리 절연막을 이루므로, 이하부터는 산화막스페이서(205)를 따로 언급하지 않고, 그리고 도면에 도시하지 않고 산화막(207)에 포함시켜 설명하기로 한다.Since the oxide film spacer 205 forms an element isolation insulating film like the oxide film 207 for device isolation, the oxide film spacer 205 will be described below by including the oxide film spacer 205 in the oxide film 207 without referring to the figure and not shown in the drawings. Let's do it.

계속해서, 도 2f와 같이 또다른 반도체기판(208)을 본딩(bonding)공정을 통하여 접합시킨 다음, 도 2g와 같이 반도체기판(201)의 뒷면을 산화막(207)이 노출될때까지 연마한다.Subsequently, another semiconductor substrate 208 is bonded through a bonding process as shown in FIG. 2F, and then the back surface of the semiconductor substrate 201 is polished until the oxide film 207 is exposed as shown in FIG. 2G.

끝으로, 도 2h는 연마된 반도체기판(201) 상에 게이트(210)와 소스/드레인 접합(211)을 형성한 상태이다.Lastly, FIG. 2H shows a gate 210 and a source / drain junction 211 formed on the polished semiconductor substrate 201.

본 실시예에서, T형 트렌치를 형성하는 방법은 여러 가지가 있을 수 있다. 예컨대 서로 다른 사이즈를 갖는 두 번의 마스크 공정을 통해 산화막스페이서(도 2b의 205) 없이 T형 트렌치를 형성할 수 있다.In this embodiment, there may be a variety of methods for forming the T-type trench. For example, a T-type trench may be formed without using an oxide spacer (205 in FIG. 2B) through two mask processes having different sizes.

또한, n채널 모스트랜지스터와 p채널 모스트랜지스터를 갖는 CMOS를 제조하기 위해서는 도 2f 의 상태에서 반도체기판(208)에 이온주입에 의해 N웰 및 P웰을 각각 형성할 수 있고, 다른 방법으로는 본딩하기 전에 미리 이온주입에 의해 N웰 및 P웰을 각각 반도체기판(208)에 형성한 다음 이 반도체기판을 본딩하는 방법이 있다.In addition, in order to fabricate a CMOS having an n-channel morph transistor and a p-channel morph transistor, N wells and P wells may be formed by ion implantation into the semiconductor substrate 208 in the state of FIG. 2F. Prior to this, there is a method of forming N wells and P wells on the semiconductor substrate 208 by ion implantation in advance, and then bonding the semiconductor substrates.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 종래기술의 단점으로 지적되던 플로팅 바디 이펙트(floating body effect)를 없앨 수 있고 소스/드레인 접합 커패시턴스(source/drain junction capacitance)를 줄이며 펀치스루(punch through)현상을 막을 수 있으며 차단된 소스/드레인 아래의 산화막에 의한 열 발생을 방출할 수 있다.The present invention can eliminate the floating body effect, which has been pointed out as a disadvantage of the prior art, can reduce the source / drain junction capacitance, prevent the punch through phenomenon, and the blocked source It is possible to release heat generation by the oxide film under / drain.

Claims (7)

반도체 기판;Semiconductor substrates; 각각 서로 고립되어 국부적으로 상기 반도체 기판 표면으로부터 일정 깊이로 형성되어 그 사이에 위치한 상기 반도체기판 영역에 채널을 유기하기 위한 소스 및 드레인 접합;Source and drain junctions each isolated from one another and locally formed to a predetermined depth from the surface of the semiconductor substrate to induce channels in the semiconductor substrate region located therebetween; 상기 채널을 유기하기 위한 상기 반도체 기판 영역 상에 형성된 게이트; 및A gate formed on said semiconductor substrate region for inducing said channel; And 상기 게이트 및 상기 소스 및 드레인 접합으로 이루어진 트랜지스터를 타 소자와 분리하기 위하여 상기 소스 및 드레인 접합의 각 외측에 국부적으로 형성되며 상기 소스 및 드레인 접합의 하부까지 확장되어 형성된 소자분리절연막A device isolation insulating film is formed locally on each outer side of the source and drain junctions and extends to the bottom of the source and drain junctions so as to separate the transistor including the gate and the source and drain junctions from other devices. 을 포함하여 이루어진 반도체 소자.Semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 소자분리절연막은 상기 채널을 유기하기 위한 상기 반도체 기판 영역의 하부에서 서로 분리된 반도체 소자.And the device isolation insulating layer is separated from each other at a lower portion of the semiconductor substrate region for inducing the channel. 제1항에 있어서,The method of claim 1, 상기 소자분리절연막의 확장 부위는 상기 소스 및 드레인 접합 하부와 맞닿는 반도체 소자.The extended portion of the device isolation insulating film is in contact with the lower portion of the source and drain junction. 제1 반도체기판을 선택적으로 식각하여 그 상부를 넓고 그 하부는 좁은 T형 트렌치를 형성하는 단계;Selectively etching the first semiconductor substrate to form a T-type trench having a wider upper portion and a narrower lower portion thereof; 상기 트렌치내를 매립한 소자분리절연막을 형성하는 단계;Forming a device isolation insulating film filling the trench; 전면에 제2 반도체기판을 본딩하는 단계;Bonding a second semiconductor substrate to the front surface; 상기 소자분리절연막의 탑 표면이 노출되도록 상기 제1 반도체기판 뒷면을 연마하는 단계; 및Polishing a back surface of the first semiconductor substrate to expose the top surface of the device isolation insulating film; And 상기 연마된 제1 반도체기판 뒷면에 게이트와 소스/드레인 접합을 형성하는 단계Forming a gate and a source / drain junction on the back side of the polished first semiconductor substrate 를 포함하여 이루어진 반도체소자 제조방법.Semiconductor device manufacturing method comprising a. 제4항에 있어서,The method of claim 4, wherein 상기 T형 트렌치를 형성하는 단계는,Forming the T-type trench, 상기 제1 반도체기판 상에 패드산화막과 질화막을 증착하고, 마스크 작업을 통해 소자분리영역의 상기 질화막, 패드산화막 및 반도체기판의 일부두께를 각각 식각하여 폭이 넓은 제1 트렌치를 형성하는 단계;Depositing a pad oxide film and a nitride film on the first semiconductor substrate and etching a portion of the nitride film, the pad oxide film, and the semiconductor substrate in the device isolation region through a mask to form a wide first trench; 제1트렌치의 측벽에 산화막스페이서를 형성시하는 단계; 및Forming an oxide spacer on a sidewall of the first trench; And 상기 산화막스페이서와 상기 질화막을 마스크로하여 상기 제1 반도체기판을 일부두께 식각하여 폭이 좁은 제2 트렌치를 형성하는 단계를 포함하여 이루어진 반도체소자 제조방법.And forming a narrow second trench by etching a portion of the first semiconductor substrate using the oxide spacer and the nitride layer as a mask. 제4항에 있어서,The method of claim 4, wherein 상기 T형 트렌치를 형성하는 단계는,Forming the T-type trench, 폭이 좁은 지역을 정의한 제1 마스크 및 식각 공정으로 제1트렌치를 형성하는 단계; 및Forming a first trench with a first mask and an etching process defining a narrow area; And 폭이 넓은 지역을 정의한 제2 마스크 및 식각 공정으로 제2트렌치를 형성하는 단계Forming a second trench with a second mask and an etching process defining a wide area; 를 포함하여 이루어진 반도체소자 제조방법.Semiconductor device manufacturing method comprising a. 제4항에 있어서,The method of claim 4, wherein 상기 제2 반도체 기판을 본딩하기 전에 상기 제2 반도체 기판에 n웰 및 p웰을 각각 형성하는 반도체소자 제조방법.And n-well and p-well are formed in the second semiconductor substrate before bonding the second semiconductor substrate, respectively.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741673B2 (en) 2006-12-13 2010-06-22 Samsung Electronics Co., Ltd. Floating body memory and method of fabricating the same
US7851859B2 (en) 2006-11-01 2010-12-14 Samsung Electronics Co., Ltd. Single transistor memory device having source and drain insulating regions and method of fabricating the same
KR20160084194A (en) * 2015-01-05 2016-07-13 삼성전자주식회사 Semiconductor devices and method of manufacturing the same

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KR100630664B1 (en) * 2000-05-09 2006-10-02 삼성전자주식회사 Integrated circuit device having cooling system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851859B2 (en) 2006-11-01 2010-12-14 Samsung Electronics Co., Ltd. Single transistor memory device having source and drain insulating regions and method of fabricating the same
US7741673B2 (en) 2006-12-13 2010-06-22 Samsung Electronics Co., Ltd. Floating body memory and method of fabricating the same
KR20160084194A (en) * 2015-01-05 2016-07-13 삼성전자주식회사 Semiconductor devices and method of manufacturing the same
KR102232766B1 (en) 2015-01-05 2021-03-26 삼성전자주식회사 Semiconductor devices and method of manufacturing the same

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