KR100256121B1 - Write mode control method and control signal generation circuit of synchronous memory - Google Patents

Abstract

PURPOSE: A method for controlling a record mode by a discontinuous bit of a synchronous memory and a device for generating a control signal of the record mode are provided to increase the efficiency of access time as being capable of performing a mask operation without performing an LMR(Load Write Mask Register) cycle every a recording cycle by all bits. CONSTITUTION: The device includes first through fifth switching portions (MP4,MN15,MN16,MN17,MN18) and outputs a signal for controlling a mask register loading and a signal controlling a bank record from a common node of the first and second switching portions. The first switching portion is connected to a power portion(Vcc) and is controlled by a precharging signal. The second switching portion is in series connected to the first switching portion and is controlled by a bank selecting signal. The third switching portion is in series connected to the second switching portion and is controlled by a row selecting signal. The fourth switching portion is in series connected to the third switching portion and is controlled by a DSF signal which is a control signal. The fifth switching portion is in series connected to the fourth switching portion and other end of the fifth switching portion is connected to a ground potential. Also, the fifth switching portion is controlled by a delay controlling portion outputting a delay controlling signal.

Description

Non-persistent bit-by-bit write mode control method of synchronous memory and control signal generator thereof

FIG. 1 shows a cycle for performing a write operation using a persistent WPB mode in the related art.

Bit-by-bit write mode is a write mode to support this in the memory itself, since general memory performs input / output in word units, whereas graphic memory needs to write bit by bit for accessing each pixel unit.

In Fig. 1, the load register register (Load Mask Register) is an operation of limiting the target bit to select only the bit that is the target of the input and output. The LMR cycle 101 is for performing an existing WPB operation, and the LMR cycle 102 is for storing new mask data in an LMR register for performing an input / output mask cycle for writing the write cycle 106. Action. The column activation cycle 104 is a cycle that must be performed in advance for the WPB operation in the write cycle 106. The column activation cycle 104 performs an operation of activating a row of a target memory. The LMR cycle 103 is also a cycle to be performed when the mask data value is changed to perform the WPB operation to be performed in another bank Bank1. As described above, when the position of the target bit changes frequently in the bit-by-bit write cycle, the input / output mask data frequently changes, and thus the LMR cycles 101, 102, and 103 must be performed every time.

FIG. 2 shows the timing of each signal in the conventional manner of FIG. For the WPB operation, mask data for each input / output must be input first during the LMR cycles 101, 102, and 103, and the WPB operation is performed according to the mask data latched in the LMR cycle during the thermal activation cycles 104, 105. Masking operation is performed on bits having mask data of "0 (low)", and non-masking operation is performed if mask data is "1 (high)".

The specific signal in FIG. 2 will be described with reference to FIG. 5, where the lmr signal and the wpb signal, which are related to the configuration of the present invention, are described first. The lmr 304 signal controls the input of mask data into the register during the LMR cycles 101, 102, and 103. The LMR register signal 305 represents the mask data state input to the register during the LMR cycle in phases. The LMR register signal 305 is non-masking data while the phase is "high" and mask data during the "low" phase. The signals wpb_b0 306 and wpb_b1 309 determine which banks perform the WPB operation and are generated in the thermal activation cycles 104 and 105. A conventional circuit configuration for generating these control signals 'lmr' and 'wpb' is shown in FIG. The non-persistent bit-by-bit write mode control apparatus of the conventional synchronous memory configured as described above has the LMR cycle 101, the thermal activation cycle 104, the thermal activation cycle 104 and the LMR cycle 102 when the mask data is frequently changed in the WPB operation. ), Since the LMR cycle 103 and the thermal activation cycle 105 must operate in pairs, there is a problem that the efficiency is reduced in terms of the actual access time.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to perform a load write mask register cycle to change the value of the mask register every time when the mask data is changed during the bit-by-bit write mode. By providing a mask operation without performing an LMR cycle for each write cycle for each bit, a non-persistent bit-by-bit write mode control method of a synchronous memory having an increased access time efficiency and a control signal generator thereof are provided.

1 is an operation timing diagram of a conventional memory for performing a write operation using a continuous bit-by-bit write mode.

2 is an operation timing diagram between signals in the conventional manner of FIG.

3 is a circuit diagram showing a conventional control signal generator.

4 is an operation timing diagram of a bit-by-bit recording mode used in the present invention.

5 is a circuit diagram showing a data flow of a synchronous memory to which the present invention is applied.

6 is an operation timing diagram between signals in the bit-by-bit recording mode of FIG.

7 is a circuit diagram of a bit-by-bit write mode control signal generator according to a first embodiment of the present invention.

8 is a circuit diagram of a bit-by-bit write mode control signal generator according to a second embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

101, 102, 103: mask register loading cycle (LMR)

104, 105: thermal activation cycle

106, 107: memory bank write cycle

703, 704, 705, 706, 708, 709: fuse

In order to achieve the above object, in the non-persistent bit-by-bit write mode control method of the synchronous memory of the present invention, for each bank of the synchronous memory composed of a plurality of banks: selecting only bits targeted for bit-by-bit recording A mask register loading step of defining a target bit in order to prevent the target bit; A column activation step for activating a row of a target memory; 32. A method for controlling bit by bit comprising writing data to a bit selected by the mask register in the activated column of each bank; The mask data loading step is performed simultaneously at the same clock as the column activation step.

In addition, the non-persistent bit-by-bit write mode control signal generator of the synchronous memory of the present invention for implementing the method comprises: a first switching unit connected to a power supply unit and controlled by a precharge signal; A second switching unit connected in series with the first switching unit and controlled by a bank selection signal bank0,1; A third switching unit connected in series with the second switching unit and controlled by a column select signal ras; A fourth switching unit connected in series with the third switching unit and controlled by a DSF signal which is a control signal; The fourth switching unit is connected in series and the other end is connected to the ground potential, and is composed of a fifth switching unit controlled by a delay control unit for outputting a delay control signal to the common node of the first switching unit and the second switching unit The mask register loading control signal lmr and the bank write control signal wpb are outputted.

The delay control unit may include an inverter having an output connected to a control terminal of a fifth switching unit; A first fuse connected to a first end of the output of the inverter and a second end of the inverter; A second fuse connected to an input terminal of the inverter and a second terminal connected to a power supply unit; The first terminal of the second fuse is connected to the source, the drain is connected to the ground power source, characterized in that it comprises a fifth PMOS switching unit is applied to the output of the inverter as a gate.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is an operation timing diagram of the bit-by-bit write mode used in the present invention. FIG. 5 is a circuit diagram showing the data flow of the synchronous memory to which the present invention is applied. FIG. Fig. 7 is a circuit diagram of a bit-by-bit write mode control signal generator according to a first embodiment of the present invention, and Fig. 8 is a bit-by-bit write mode control according to a second embodiment of the present invention. A circuit diagram of a signal generator.

Referring to FIG. 4, the bit-by-bit recording mode of the present invention is different from that of the LMR cycles 101, 102, and 103 in FIG. 1, which is applied through the thermal activation cycles 104 and 105 performing the WPB operation. That is, in the prior art of FIG. 1, the mask data is latched to the LMR register through the LMR cycles 101, 102, and 103 previously performed, and the write cycles 106 and 107 are determined after determining whether or not the WPB operation for each input / output is performed in the column activation cycles 104 and 105. Determines whether to operate the mask for each input and output. Referring to Fig. 6, the timing according to the present invention is compared with the prior art.

1. No LMR cycles (101, 102, 103),

2. The mask data is not input at the LMR cycles 102, 103, but at the thermal activation cycles 104, 105;

3. The lmr signal 304 is not activated in the LMR cycles 101, 102 and 103 but in the same cycle as the wpb signals 306 and 309 which control the WPB operation of each bank in the column activation cycle 104 and 105.

Next, the operation of the present invention will be described in detail with reference to Figs.

Fig. 5 is a circuit diagram showing the configuration according to the data flow for the bit-by-bit write of the synchronous memory to which the present invention is applied. 7 and 8 show a control signal generator which controls the flow of data by the control sequence as described in FIGS. 4 and 6 within this data flow.

Fig. 7 shows a first embodiment of a circuit for generating the wpb signals 306 and 309 and the lmr 304 which are control signals according to the present invention, which is connected between the power supply potential Vcc and the node N7 and free to the gate. P-MOS MP3 to which a charge signal (piprecharge) is input, and is connected in series between the node N7 and the ground voltage (Vss), and bank selection signals (pibank0, 1), column selection signals (piras), and control signals to respective gates. N-MOS MN12 to MN14 to which the pidsf signal is input, inverters I3 and I4 connected in a latch structure between the node N7 and the node N8, inverter I5 connected between the node N8 and the node N9, and the node. Three inverters I6 to I8 connected in series between the terminal for outputting the signal N9 and wpb, an inverter I9 connected between the node N9 and the node N10, and inverters I11 to I14 connected in series between the node N9 and the node N11. And input potential signals of the node N10 and the node N11. It consists of a logic operation signal to the inverter I10 is connected between the terminal of the NAND gate NA1 and outputs to the node N12, the node N12 and the output signal lmr. The pulse width of the lmr 304 is determined by the delay circuit 604 composed of inverters I11 to I14. The lmr 304 signal has a phase of " low " when the " high " (non-mask) data of the cycle 109 is input through the input buffer, and the LMR register 305 is provided through the lmr signal 304. Hi) is latched so that the node 406 goes low regardless of the phase of the wpb 308, and the DQ record input from the cycle 106 is accepted through the input buffer. Conversely, if the DQ data in cycle 110 is " low " as in cycle 105, DQB 402 has a " high " phase and " low " to LMR register 305 via the signal of lmr 304. When the phase of wpb 308 goes high, the node 406 becomes high and cannot accept the DQ input from the write cycle 107.

In Fig. 6, the area 501 is a recordable area, and in the area 502, a WPB operation is performed to perform an input / output masking operation. In FIG. 6, since the casatv8_b0 307 and the casatv8_b1 310 are two banks in synchronous DRAM or graphics RAM as bank selection information, it is forbidden to decide which bank to write, i.e., perform the WPB operation. . The LCR register 407 is used in the block write mode, which is a special mode of the graphics RAM, and replaces the role of the DQ input from the input buffer during the write operation.

FIG. 8 is a circuit diagram of a control signal generator according to a second embodiment of the present invention, in which a P-MOS MP4 connected between a power supply potential Vcc and a node N13 and into which a precharge signal is input to a gate is shown. And N-MOS MN15 to MN17 connected in series between the node N13 and the ground voltage Vss, and inputting a bank selection signal pibank0,1, a column selection signal piras, and a control signal pidsf signal to respective gates, respectively. A fuse 708 connected between the power supply voltage Vcc and the node N14, a fuse 709 connected between the power supply voltage and the node N15, an inverter I15 connected between the node N14 and the node N15, and a ground with the node N14. N-MOS MN19 connected between the voltage and the gate connected to the node N15, and N-MOS MN18 connected between one terminal of the N-MOS MN17 and the ground voltage and the node N15 is input to the gate.

In the figure, the operation is different from the prior art in that the CSB, RASB, and DSF are in phase as shown in Fig. 4, and if the value of DQ is "low" in the cycles 109 and 110, the data is mask data. Non-mask data. Therefore, in FIG. 4, the first thermal activation cycle 104 may not perform the WPB operation, and the second thermal activation cycle 105 may perform the WPB operation.

The present invention can be used in parallel through a continuous bit-by-bit write mode, which is a specific mode in a synchronous graphics RAM, and a simple fuse option. In case of using the existing continuous mode, the conventional control signal generator of FIG. 3 may cut the fuses 703 and 705, and in FIG. 8 of the present invention, the existing continuous mode may be used by cutting the fuse of the fuse 709. In use, the non-persistent mode can be used by cutting the fuses 704 and 706 in FIG. 8 and cutting the fuse 708 in FIG.

As described above, when the non-persistent bit-by-bit recording mode is used in the synchronous graphics RAM of the present invention, the existing LMR cycle is eliminated, thereby effectively increasing the efficiency of the actual access time. In addition, when the non-persistent bit-by-bit recording mode is used, the previously separated lmr and wpb signal generators can be used as a single generator, which is simplified in a complicated function and the chip area can be reduced, which is more efficient than the conventional area. .

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous graphic RAM. In particular, the mask register is changed every time when the mask data is changed when performing the write per bit mode. In order to change the value of), the mask operation is performed without performing the LMR cycle every WPB write cycle from the load write mask register (LMR) cycle. The present invention relates to a non-persistent bit-by-bit write mode control method of a synchronous memory, which increases the efficiency of access time, and to a control signal generator.

Claims (3)

A mast register loading step of defining a target bit to select only a target bit for bit-by-bit writing for each bank of a synchronous memory composed of a plurality of banks, and a row activation for activating a row of the target memory. And writing data in the bit selected by the mask register in the activated row of each bank; And the mask data loading step is performed simultaneously at the same clock as the row activation step. A control signal generator for a bit-by-bit write mode of a synchronous memory, comprising: a first switching unit connected to a power supply unit and controlled by a precharge signal; A second switching unit connected in series with the first switching unit and controlled by a bank selection signal; A third switching unit connected in series with the second switching unit and controlled by a row selection signal; A fourth switching unit connected directly to the third switching unit and controlled by a DSF signal as a control signal; In the common node of the first switching unit and the second switching unit having a fifth switching unit connected in series with the fourth switching unit and the other end is connected to the ground potential, and controlled by a delay control unit for outputting a delay control signal. A bit-by-bit write control device of a synchronous memory for outputting a mask register loading control signal and a bank write control signal. The inverter of claim 2, wherein the delay control unit has an inverter having an output connected to a control terminal of a fifth switching unit, a second fuse having an output of the inverter connected to a first end, and a second termination connected to a power supply unit. And a fifth PMOS switching unit having a first end of the second fuse connected to the source, a drain connected to the ground power source, and an output of the inverter applied to a gate.

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