KR100255305B1 - Testing switch for atm - Google Patents

Abstract

PURPOSE: A switching apparatus for testing in an ATM exchange is provided to rapidly and exactly test a UTOPIA interface of an interface board by embodying a simple switching board having only a switching function so that it can be operated in any mode between an octet level or a cell level according to an interface mode selection control signal inputted from the external. CONSTITUTION: A switching apparatus for testing in an ATM exchange consists of two LIMs(Line Interface Modules)(10,30) and a switching apparatus(20). The LIMs(10,30) execute the data transmitting/receiving functions of data. The switching apparatus(20) switches the data transmitted through the first LIM(10) or the second LIM(30) and outputs the data to the first LIM(10) or the second LIM(30). The switching apparatus(20) is composed of an EEPROM(21), the first FIFO(23), the second FIFO(24), and a transceiver unit(22). The EEPROM(21) initializes the transceiver unit(22). The first FIFO(23) and the second FIFO(24) temporarily store the data transmitted through the first LIM(10) or the second LIM(30). The transceiver unit(22) switches the data transmitted through the first LIM(10) or the second LIM(30) and outputs the data to the first LIM(10) or the second LIM(30).

Description

Test switching device for asynchronous transfer mode switch

The present invention relates to an octet level when performing a UTOPIA (Universal Test & Operation PHY Interface for ATM) interface with a matching board in a switching board of an asynchronous transfer mode (hereinafter, referred to as 'ATM') switch. Or, it relates to a test switching device of an ATM exchange which enables operation in any of the cell levels and enables quick and accurate testing of the UTOPIA interface portion of the matching board.

In general, a switching board in an ATM exchange is a place where each input packet exchange is substantially performed according to routing information, and performs a function of delivering packets arriving at an input terminal to an output terminal according to each output address.

In addition, the switching board in the ATM exchanger handshaking with the matching board through a UTOPIA interface. In this UTOPIA interface method, an octet level (1 byte) for transmitting / receiving data in byte units and data in cell units is used. There is a cell level (53 bytes) to transmit / receive.

Meanwhile, when the switching board and the matching board interface with UTOPIA and exchange data with each other, a normal switching board performing the matching board and the UTOPIA interface may be used to test whether the matching board operates normally, in particular, the UTOPIA interface portion of the matching board. There is a need, conventionally, there is a problem that it is not easy to test the matching board because there is no separate test switching board for the test of the matching board.

The present invention has been made to solve the above problems, the object of which is to implement a simple switching board having only a switching function when performing the UTOPIA interface with the matching board, according to the control signal for selecting the interface mode input from the outside It is to provide a test switching device for an ATM switch that enables the operation of either the octet level or the cell level to enable fast and accurate testing of the matching board's UTOPIA interface.

Test switching device of the ATM switch of the present invention for achieving this object is connected between the LIM and the LIM performing the transmission / reception function of the data, EPROM for initializing the transmission / reception unit to be described later, the LIM or LIM A first and second FIFO for temporarily storing data transmitted through the LIM and a LIM or a LIM, and a transmitter / receiver for switching the data transmitted through the LIM or the LIM and outputting the LIM or the LIM. And a data latch unit for receiving and latching data transmitted through the LIM, and a SID decoder for finding a my turn time for transmitting / receiving the LIM or the LIM using a turn time transmitted from a clock module. And a write control unit configured to control to store data in the first FIFO within the my turn time, wherein the transmitting unit of the transmitting / receiving unit is the first FF. A data latch unit for receiving and latching data stored in an IFO, a SID decoder for finding a my turn time for transmitting / receiving the LIM or OLIM using a turn time transmitted from a clock module, and control for selecting an interface mode. And a read controller including an interface controller for selecting an octet level or a cell level according to a signal, and controlling to read data stored in the FIFO within the my turn time and output the data to the LIM.

1 is a block diagram of a switching device for a test of an asynchronous transfer mode (ATM) exchange according to the present invention.

2 is a block diagram of a receiver of FIG. 1;

3 is a block diagram of the transmitter of FIG.

* Explanation of symbols for main parts of the drawings

20: switching device 21: EPROM

22: transmitter / receiver 22-A: receiver

22-B: Transmitter 23: First FIFO

24: second FIFO 41, 51: data latch unit

42: light control unit 43, 53: SID decoder

52: lead control unit 54: interface control unit

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the test switching device of the ATM switch according to the present invention.

1 is a block diagram of a switching device for a test switch of an ATM switch according to the present invention, and includes two line interface modules (LIMs) 10 and 30, which are matching boards that perform data transmission / reception functions, and the LIM 10 ) Is configured between the LIM 30 and the switching device 20 for switching the data transmitted through the LIM 10 or the LIM 30 to the LIM 10 or the LIM 30.

The switching device 20 includes an EPROM 21 for initializing a transmitter / receiver, which will be described later, and a first FIFO 23 and a second FIFO for temporarily storing data transmitted through the LIM 10 or the LIM 30. And a transmitter / receiver 22 which switches the data transmitted through the LIM 10 or the LIM 30 and outputs the data to the LIM 10 or the LIM 30.

The transmitter / receiver 22 in the switching device 20 may be simply implemented as a FPGA (Fild Programmable Gate Array) having a 2 × 2 exchange function.

FIG. 2 is a block diagram of the receiver 22-A of the transmitter / receiver 22 of FIG. 1 for receiving and latching 56 bytes of packet data transmitted through the LIM 10. A data latch 41 and a turn time transmitted from a clock module (not shown) may be used to transmit / receive the LIM 10 or the LIM 30. Write Control 42 which controls to store data in the first FIFO 23 within the My Turn time, including a Self Identification Data (SID) Decoder 43 that finds a MY Turn time. It is composed of

FIG. 3 is a block diagram of the transmitter 22-B of the transmitter / receiver 22 of FIG. 1, which includes a data latch 51 for receiving and latching data stored in the first FIFO 23, and a clock module. According to the SID decoder 53 which finds the my turn time which can be transmitted / received to the LIM 10 or the LIM 30 by using the transmitted turn time, and according to a control signal for selecting an interface mode input from the outside. A read control section including an interface control section 54 for selecting an octet level (1 byte) or a cell level (53 bytes) to control the data stored in the first FIFO 23 to be output to the LIM 30 within the my turn time. (Read Control) 52.

Referring to the operation of the switching device for testing the ATM switch according to the present invention configured as described above are as follows.

First, the receiver 22 -A selectively uses an octet level (1 byte) or a cell level (53 bytes) as an interface with the LIM 10, thereby receiving data transmitted through the LIM 10. ) Is stored in the first FIFO 23 within the my turn time in a stable state under the control of the write control unit 42.

In this case, since the SID decoder 43 uses the turn time transmitted from the clock module and finds the my turn time for the LIM 10, the write control unit 42 controls the first FIFO 23 within the corresponding my turn time. This completes saving the data into.

Subsequently, data transmitted through the receiving unit 22 -A and stored in the first FIFO 23 is transmitted to the transmitting unit 22 -B and latched by the data latching unit 51.

Then, when the SID decoder 53 finds the my turn time using the turn time transmitted from the clock module, the read controller 52 reads the data stored in the first FIFO 23 within the corresponding my turn time. It transfers to the LIM 30 which is an output terminal.

At this time, the interface controller 54 selects an interface with the LIM 30 via an octet level (1 byte) or a cell level (via the selection mode control signal according to the same interface mode as that used by the LIM 30). 53 bytes).

That is, the interface control unit 54 uses an octet level (1 byte) to interface with the LIM 30 through a selection mode control signal according to the interface mode when the reception side matching board, that is, the octet level (1 byte) is used in the LIM 30. When the cell level (53 bytes) is used in the LIM 30, the interface with the LIM 30 is performed at the cell level (53 bytes) through a selection mode control signal according to the interface mode.

As described above, the present invention implements a simple switching board with only a switching function, and when performing the UTOPIA interface with the matching board, any mode of octet level or cell level according to a control signal for selecting an interface mode input from the outside is provided. Operation is also possible, as well as the ability to quickly and accurately test the UTOPIA interface of the matching board.

Claims (2)

Connected between the LIM 10 and the LIM 30 that perform data transmission / reception functions, and the EPROM 21 for initializing a transmission / reception unit to be described later, and the LIM 10 or the LIM 30. The LIM 10 or the LIM 30 by switching between the first FIFO 23 and the second FIFO 24 for temporarily storing data transmitted through the LFI 10 and the LIM 30. And a transmitter / receiver 22 for outputting the data, wherein the receiver 22-A of the transmitter / receiver 22 receives and latches data transmitted through the LIM 10. And a SID decoder 43 which finds a my turn time that can be transmitted / received to / from the LIM 10 or the LIM 30 using the turn time transmitted from the clock module. And a write controller 42 for controlling data to be stored in the 1FIFO 23, and the transmitter 22-B of the transmitter / receiver 22 is configured as the first FIFO 2; 3) The data latch unit 51 which receives and latches the data stored in 3) and the turn time transmitted from the clock module to determine the my turn time that can be transmitted / received to or from the LIM 10 or the LIM 30. The SID decoder 53 and an interface controller 54 for selecting an octet level or a cell level according to a control signal for selecting an interface mode, and reading the data stored in the first FIFO 23 within the my turn time. A test switching device for an asynchronous transfer mode (ATM) exchange, characterized by comprising a lead control unit 52 for controlling lead output to the LIM (30). The test switch device of claim 1, wherein the transmitter / receiver is implemented in an FPGA.

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