KR100254393B1 - Dct core capable of multiplying of weighting coefficients architecture - Google Patents

Abstract

PURPOSE: A discrete cosine conversion core structure capable of processing a weighting coefficient is provided to reduce the size of hardware by using memory in which a weighting coefficient is multiplied by a DCT coefficient in a DCT/IDCT core without a special multiplier. CONSTITUTION: An input module(30) outputs data signals of input matrices of 8*1 DCT/IDCT and 2*(4*1) DCT/IDCT mode. A 3*1 multiplexer(32) selects a data signal of the input matrix. A butterfly(34) performs an addition and a subtraction of the input matrix selected by the 3*1 multiplexer(32). A 2*1 multiplexer(36) selects a data signal of the input matrix selected by the 3*1 multiplexer(32). A memory module(50) stores an addition and a subtraction result between cosine coefficients of the data signals and a weighting coefficient. A 4*1 multiplexer(42) selects an output signal of the memory module(50). A bit serial adder(60) outputs an 8*1 DCT, a 2*(4*1) DCT and a 2*(4*1) IDCT result. A butterfly (62) performs an addition and a subtraction of the 8*1 DCT of the bit serial adder(60). A 2*1 multiplexer(64) selects an output of the butterfly(62) or an output of the bit serial adder(60). An output module(66) outputs the signal selected by the multiplexer(64).

Description

Discrete Cosine Transform Core Structure with Weight Coefficient Processing

The present invention relates to a DCT core used in digital image processing, and more particularly, to a DCT core structure capable of weighting coefficient processing.

As is well known, the digitalized video signal can be transmitted as a higher quality video image than the analog signal. When a video signal composed of a series of video frames is represented in a digital form, a considerable amount of data is generated to transmit the digital video signal. However, since the available frequency bandwidth of a typical transmission channel is limited, it is necessary to compress the amount of data to be transmitted in order to transmit a large amount of digital data through the limited channel bandwidth.

Since the video signal has any correlation or redundancy between certain pixels in one frame or in neighboring frames, it is possible to compress the video signal without seriously adversely affecting the whole of the video signal. Therefore, most conventional video signal encoding methods use various compression techniques developed based on the technical idea of using or eliminating the above-described redundancy.

One category of such coding methods relates to a transformation technique that takes advantage of the redundancy that exists within a frame, and includes a diagonal transformation method for transforming a digital image data block into a transform coefficient, for example, a two-dimensional discrete cosine transform (DCT) coefficient. orthogonal transform method).

In particular, in the above-described diagonal conversion method such as DCT, a video signal of one frame is divided into non-overlapping equal sized blocks, for example, 8 * 8 pixel blocks, each pixel block being a frequency in a spatial domain. Is converted to an area. As a result, each pixelblock will have a set of transform coefficients consisting of one DC coefficient and a plurality of (e.g., 63) AC coefficients. These transform coefficients represent the amplitude of the frequency component of each pixel in one block, in particular the DC coefficient of the block has the average brightness of the pixels in the block, while the remaining AC coefficients are the spatial frequency components of each pixel. Indicates the luminance.

In the early days of DCT development in the field of digital image processing such as digital VCRs, DCT and IDCT were mainly implemented by mathematically converting FETs obtained by rearranging input sequences. Among the new algorithms announced after this method, Chen and Lee's high-speed algorithms contributed to the reduction of complex computational loads and implemented DCT / IDCT using multiplier to be suitable for hardware implementation.

The most time-consuming part of the DCT is the multiplication part, and high-speed algorithms have been proposed to improve the execution speed, or two-dimensional DCT using low-column decomposition method. Attempts have been made to facilitate implementation by calculating the dimensional DCT. However, when implementing this in hardware, there is a disadvantage that a multiplier that takes up a large area must be used.

In order to overcome this drawback, the proposed distributed arithmetic (DA) algorithm performs DCT / IDCT multiplication without using multiplier when performing DCT / IDCT. Efficient implementation in area and speed.

The above-described DA scheme is configured to multiply different weighting coefficients W according to frequency components of the DCT coefficient outputs converted in the digital imaging apparatus. These weighting coefficients are listed by way of example below.

In (8 * 8) mode

If h = v = 0, W (h, v) = 1/4

Otherwise, W (h, v) = w (h) w (v) / 2

In (2 * 4 * 8) mode

If h = v = 0, W (h, v) = 1/4

Otherwise, W (h, v) = w (h) w (v) / 2

Where w (0) = 1

w (1) = CS ₄ / (4CS ₇ CS ₂ )

w (2) = CS ₄ / (2CS ₆ )

w (3) = 1 / (2CS ₅ )

w (4) = 7/8

w (5) = CS ₄ / CS ₃

w (6) = CS ₄ / CS ₂

w (7) = CS ₄ / CS ₁

Where CS _i = COS (iπ / 16), h. v is a parameter used in the DCT transform, and is a variable representing the horizontal index (h) and the vertical index (v) of the factors in the source information matrix and the transform coefficient matrix, and those skilled in the art can easily I can understand.

FIG. 1 shows a DCT core using a DA scheme in which a DCT transform coefficient according to the prior art is multiplied by a weighting coefficient (W).

The DCT block 10 processes the input data (x ₀ to x ₇ ) input in the matrix form in 8 * 1 or 2 * 4 * 1 DCT mode and outputs the output data (y ₀ to y ₇ ) in the matrix form. . The weighting coefficient processor 20 including a ROM for storing the multiplication and addition results of the coefficient data performs a function of multiplying the weighting coefficient value W by the output matrix data y ₀ to y ₇ .

For example, the 8 * 1 DCT matrix calculation equation implemented by the DA method may be expressed by Equation 1 below.

In the above formula to be.

In this case, the DCT transform coefficient y ₂ of the 8 * 1 mode may be calculated as shown in Equation 2 below.

The transform coefficient y ₂ calculated in Equation 2 is multiplied by the weighting coefficient W (2) by the weighting coefficient processor 20 to obtain the weighted output matrix Y'2.

However, in the DCT core structure using the DA method of multiplying the DCT transform coefficients by the weighting coefficient W, the scale of the hardware is greatly increased by using a separate multiplier for the multiplication of the weighting coefficients. As a result, there has been a problem that the area and volume of the chip are increased.

The present invention has been made as described above, an object of the present invention is to provide a DC type DCT / IDCT core capable of processing the weighting coefficient without using a separate multiplier.

According to the present invention for achieving the above object, the data signal of the input matrix in the 8 * 1 DCT / IDCT and 2 * 4 * 1 DCT / IDCT mode by processing the image signal of 8 bit unit (x ₀ ~ x ₇ ) And an input module for outputting (y ₀ to y ₇ ) and a first multiplexer for selecting an input matrix signal of an 8 * 1 DCT, 2 * 4 * 1 DCT, or 2 * 4 * 1 IDCT mode output from the input module. And a first butterfly for performing the subtraction of the input matrix selected by the first multiplexer, and a second multiplexer for selecting the data signal of the input matrix in the 8 * 1 IDCT mode as a result of the subtraction of the first butterfly. And the addition and multiplication results of the cosine coefficients of the (x ₀ to x ₇ ) and the (y ₀ to y ₇ ) and the weighting coefficients (W), and storing the added and multiplying results of the signal selected by the second multiplexer. A memory module performing a matrix operation and the memory module Bit serial adder that outputs 8 * 1 DCT 2 * (4 * 1) DCT and 2 * (4 * 1) IDCT results by accumulating the sum of the weighted bit-wise matrix calculation output from the module for all bits. And a second butterfly performing addition and subtraction with respect to a matrix of 8 * 1 DCTs of the bit series adder, and a third multiplexer for selecting the output of the second butterfly or the output of the bit series adder. A DA method DCT / IDCT DCT core capable of counting is provided.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.

1 is a hardware block diagram for weighting coefficient processing performed in the prior art,

2 is a block diagram of a DCT / IDCT core of the DA method used in the present invention.

<Explanation of symbols for main parts of drawing>

30: input module 32, 36, 42, 64: multiplexer

34, 62: butterfly 50: memory module

60 bit serial adder 66 output module

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Referring to FIG. 2, there is shown the configuration of 8 * 1 DCT / IDCT and 2 * (4 * 1) shared DCT / IDCT cores capable of weighting factor processing according to a preferred embodiment of the present invention.

The 8 * 1 DCT / IDCT and 2 * (4 * 1) DCT / IDCT shared DCT cores used in the present invention are the same as the present invention and filed under the name "discrete cosine transform core structure" and assigned to the same assignee. Application No. 96-81068.

The 8 * 1 DCT / IDCT and 2 * (4 * 1) DCT / IDCT shared DCT cores process video signals in 8-bit increments to provide input metrics for 8 * 1 DCT / IDCT and 2 * 4 * 1 DCT / IDCT modes. An input module 30 for outputting data signals x ₀ to x ₇ and (y ₀ to y ₇ ), and 8 * 1 DCT, 2 * 4 * 1 DCT or 2 * 4 output from the input module 30 * 1 In the butterfly 34 and the butterfly 34 performing addition and subtraction of the input matrix selected in the 3 * 1 multiplexer 32 and the 3 * 1 multiplexer 32 to select the data signal of the input matrix in the IDCT mode. Cosine coefficients and weighting coefficients (W) of 2 * 1 multiplexers 36, (x ₀ to x ₇ ), and (y ₀ to y ₇ ) that select the data signal of the additive result or the input matrix in 8 * 1 IDCT mode. The memory module 50 stores the addition and multiplication results of the memory module 50, and performs a matrix operation on the signal selected by the 2 * 1 multiplexer 36 and the stored addition and multiplication result, and an output signal of the memory module 50. 4 * 1 multiplexer 42 and 4 * 1 multiplexer 42 obtain the cumulative sum of the weighted bit-wise matrix calculation results for all the bits, and calculate 8 * 1 DCT, 2 * (4 * 1). Butter that adds and subtracts the matrix of the 8 * 1 DCT of the bit serial adder (BSA) 60 that outputs DCT and 2 * (4 * 1) IDCT results, and the bit serial adder 60. 2 * 1 multiplexer 64 for selecting the fly 62, the output of the butterfly 62, or the output of the bit serial adder 60, and an output module 66 for outputting the signal selected by the multiplexer 64. It includes.

That is, the 3 * 1 multiplexer 32 connected to the input module 30 depends on an 8 * 1 mode selection control signal or a 2 * (4 * 1) mode selection control signal provided by a controller not shown in the figure. It determines whether to perform 8 * 1 DCT / IDCT or 2 * (4 * 1) DCT / IDCT mode on the input signal, and the 2 * 1 multiplexer 36 controls the DCT / IDCT selection control provided from the control unit (not shown). The signal determines whether to perform DCT or IDCT on the subtracted result or the 8 * 1 IDCT output signal output from the butterfly 34.

In this way, the butterfly 34 commonly used in 8 * 1 DCT, 2 * (4 * 1) DCT 2 * (4 * 1) IDCT can be shared. Therefore, the rear 2 * 1 multiplexer 64 selects the output of the rear end butterfly 62 only when performing 8 * 1 IDCT.

The memory module 50 adds and multiplies the cosine coefficient and the weighting coefficient (W) necessary for the calculation of 8 * 1 DCT, 8 * 1 IDCT, 2 * 4 * 1 DCT, and 2 * 4 * 1 IDCT, respectively. Memory 52, 54, 56 and 58, such as a ROM to store.

According to the present invention, the weighting coefficient may be separated in the horizontal (h) direction and the vertical (v) direction except when the horizontal index h and the vertical index v, that is, when h = v = 0. Therefore, if the product of the cosine coefficient and the weighting coefficient is pre-calculated and stored in the ROM for the one-dimensional DCT / IDCT, the weighting coefficient processing as well as the DCT / IDCT will be possible without a separate multiplier. At this time, when h = v = 0, the weighting coefficient processing is possible by adding only one bit right shift circuit (DCT case) and one bit left shift circuit (IDCT case).

For example, referring to Equation 2 above, which calculates the DCT transform coefficient y ₂ in the 8 * 1 mode, since y ' ₂ = W (2) * y ₂ , the memory 52 for the 8 * 1 DCT mode is W. The multiplication and addition results of (2) C ₂ , W (2) C ₆ , -W (2) C ₆ , and -W (2) C ₂ are stored so that the weighting coefficient can be processed without a separate multiplication operation.

Accordingly, the weighted coefficient data output using the respective memory 52, 54, 56 and 58 is selectively transmitted by the multiplexer 42 to the next bit serial adder 60 and butter. It is processed via ply 62.

As described above, in the DA DCT / IDCT core according to the present invention, by using a memory in which the DCT coefficients are multiplied by the weight, it is possible to replace the multiplier used for the weighting coefficient processing, and thus the hardware scale and the chip area. It can provide the advantage that can minimize.

Claims (1)

Inputs to process data signals (x ₀ ~ x ₇ ) and (y ₀ ~ y ₇ ) of input matrix in 8 * 1 DCT / IDCT and 2 * 4 * 1 DCT / IDCT modes by processing 8-bit video signals module; A first multiplexer for selecting an input matrix signal of an 8 * 1 DCT, 2 * 4 * 1 DCT, or 2 * 4 * 1 IDCT mode output from the input module; A butterfly that performs addition and subtraction of the selected input matrix in the first multiplexer; A second multiplexer for selecting a data signal of an input or subtracted result in the butterfly or an input matrix in an 8 * 1 IDCT mode; Add and multiply the cosine coefficients of the (x ₀ to x ₇ ) and (y ₀ to y ₇ ) and the weighting coefficients (W), and store a matrix operation of the selected signal and the stored addition and multiplication result in the second multiplexer A memory module to perform; Bits for outputting 8 * 1 DCT 2 * (4 * 1) DCT and 2 * (4 * 1) IDCT results by accumulating the sum of the weighted bit-metric metrics operation output from the memory module for all bits. Serial adder; A second butterfly performing addition and subtraction on a matrix of 8 * 1 DCTs of the bit serial adder; And a third multiplexer for selecting the output of the second butterfly or the output of the bit serial adder.