KR100253220B1 - Memory control apparatus for digital still camera - Google Patents

Abstract

PURPOSE: An apparatus for controlling a memory of a digital still camera is provided to maximize a using efficiency of a D-ram by giving a right to use a D-ram in a rest state to a central processing apparatus and performing various processes by the central processing apparatus with using a corresponding D-ram. CONSTITUTION: A camera DSP codes image data outputted from the first D-ram(12A) and the second D-ram(12B) and outputs image data to a displaying method in a reproduction mode. The camera DSP processes image data inputted from a CCD and records image data to the first D-ram(12A) and the second D-ram(12b) in a record mode. A memory controller(13) transfers a right to access to one D-ram to a central processing apparatus(14) and outputs several control signals to access to the other D-ram. The central processing apparatus(14) outputs a D-ram selecting signal(SEL1) to receive a right to access to a D-ram to the memory controller(13) and compresses image data inputted from a corresponding D-ram.

Description

Memory control unit of digital still camera

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image signal processing technology of a digital still camera, and more particularly to a digital still camera that employs progressive CCD and uses two DRAMs alternately. The present invention relates to a memory controller of a digital still camera that is suitable for improving use efficiency.

Recently, digital still cameras are widely used as image input devices of personal computers (PCs), and DRAMs are used to process and store video signals output from CDs in real time, and control the DRAMs. Memory controller and a central processing unit (RISC CPU) for compressing and reproducing images already stored in the DRAM are used.

In the case of digital still camera adopting VGA-type CD, one screen is reproduced with the resolution of 640 × 480 pixels in the horizontal and vertical directions. This image information can be stored using only one DRAM. . However, Progressive CDs do not have a separate monitoring mode, so they use two DRAMs to implement moving images.

In this case, when the image information stored in one of the DRAMs is output and displayed on the LCD or the monitor, the other DRAM is in the idle state.

As described above, in the case of using two DRAMs in a digital still camera adopting a progressive CD, when one DRAM is being used, the other DRAM is in an idle state, and thus there is a defect that the utilization efficiency is lowered.

Therefore, the technical problem to be achieved by the present invention is to centralize the right to use one DRAM in the idle state when one DRAM is used when two DRAMs are used in a digital still camera employing progressive CDs. The present invention provides a memory control device for a digital still camera that takes over the device and causes the central processing unit to perform various processes using the corresponding DRAM.

1 is an exemplary block diagram of a memory control apparatus of a digital still camera according to the present invention.

FIG. 2 is a detailed block diagram illustrating an implementation of the memory controller in FIG. 1. FIG.

Figure 3 is a detailed block diagram showing an embodiment of the camera DS in Figure 1;

*** Description of the symbols for the main parts of the drawings ***

11: Camera DS 12A: First DRAM

12B: Second DRAM 13: Memory Controller

14: central processing unit

FIG. 1 is a block diagram showing an embodiment of a memory control apparatus of a digital still camera for achieving the object of the present invention. As shown therein, a DRAM selection signal supplied from the memory controller 13 in a playback mode is shown. According to SEL2, the video data read-out from the first DRAM 12A or the second DRAM 12B is encoded and output to the display means, and in the recording mode, the video data input from the CD is processed to process the video data. A camera DSP 11 for recording to one DRAM 12A and a second DRAM 12B; An access right to one of the first DRAM 12A and the second DRAM 12B is transferred to the CPU 14 according to the DRAM selection signal SEL1 supplied from the CPU 14. A memory controller 13 for outputting various control signals RAS, CAS, RD / WR to access the remaining DRAM; In the playback mode, the DRAM select signal SEL1 is output to the memory controller 13 in order to take over an access right from the first DRAM 12A and the second DRAM 12B, and then access the corresponding DRAM. With reference to Figures 2 and 3 attached to the operation of the present invention configured as a central processing unit 14 for compressing the image data input therefrom, as follows.

When the internal mode of the camera DSP 11 is a playback mode, the camera DS 11 encodes data input from the first DRAM 12A through the bidirectional port 1 and displays the data on the LCD or monitor. In the recording mode, the image data supplied from the progressive CD is stored in the first DRAM 12A and the second DRAM 12B through the bidirectional ports port1 and port2, and the image data of one DRAM is captured. The image data of the other DRAM is used by the central processing unit 14 for compression processing.

However, as described above, when the internal mode of the camera DSP 11 is the playback mode, the DRAM selection signal SEL1 output from the CPU 14 is transmitted to the memory controller 13. The signal SEL1 is a signal that informs the memory controller 13 which of the two DRAMs 12A and 12B is to be accessed by the CPU 14. The memory controller 13 receives the DRAM selection signal SEL1 and transfers the bus access right to any one of the two DRAMs 12A and 12B to the CPU 14, so that the memory controller 13 receives the DRAM selection signal SEL1. Control authority is transferred entirely to the central processing unit 14 side.

In this case, the DRAM, in which the bus access authority of the two DRAMs 12A and 12B is not transferred to the CPU 14, is used to input image data to the camera DS 11, and at this time, the camera DS ( 11) The image data input to the image is encoded by the internal encoder and displayed on the LCD or monitor so that the user can view the image.

For example, when the DRAM selection signal SEL1 output from the CPU 14 to the memory controller 13 is output in a low state, the CPU 14 may select the first DRAM 12A. In this case, the bus access authority for the DRAM 12A is transferred to the central processing unit 14 and the control signal CS generated by the central processing unit 14, that is, the low address strobe signal RAS. ), The column address strobe signal CAS, the out enable / write enable signal RD / WR, the address signal ADD, and the data.

At this time, the DRAM selection signal SEL2 output from the memory controller 13 to the camera DSP 11 is output in a “high” state so that the camera DSP 11 has a second DRAM 12B as image data to be currently input. It is recognized that the image data to be input from, at this time, the mode of the bidirectional port (port2) is switched to the input mode.

Meanwhile, FIG. 2 is a detailed block diagram illustrating an embodiment of the memory controller 13 in FIG. 1 and the operation of the memory controller 13 will be described in detail with reference to the following.

When the memory controller 13 is operating in the regeneration mode PB, one of two DRAMs 12A and 12B may be set according to the DRAM selection signal SEL1 supplied from the CPU 14. When the bus access right is passed to the CPU 14, all the control signals for the corresponding DRAM are used by the CPU 14, and all the control signals for the other DRAM are stored in the memory controller 13. Of the two control signal generators 22A and 22B in the inside, the address generated by the control signal generator and the address generator 21 is used to operate in the normal playback mode. At this time, the data output to the first DRAM 12A or the second DRAM 12B is transferred through the bidirectional buffer 23A or the bidirectional buffer 23B.

For example, when the DRAM selection signal SEL1 is supplied as "low", it is transmitted to the control signal generators 22A and 22B and the bidirectional buffers 23A and 23B, respectively, to determine their operating states. .

Therefore, the control signal generator 22A does not generate a control signal by itself, but the control signal CS supplied from the CPU 14, that is, the control signals RAS, CAS, OE / WE, and the address (Add). Bypassing the data, the data is again transferred to the first DRAM 12A through the bidirectional buffer 23A. At this time, the data read out from the first DRAM 12A is transferred to the central processing unit 14 through the bidirectional buffer 23A and the control signal generator 22A and used for compression processing.

However, since the control authority of the second DRAM 12B remains in the memory controller 13, the control signal generator 22B controls the control signal CS2, that is, the control signal RAS, for controlling the second DRAM 12B. CAS and OE / WE are generated and output, and the address Add generated by the address generator 21 is bypassed. At this time, the data read out from the second DRAM 12B is read out of the camera DSP 11. Is encoded by the encoder and output to the LCD or monitor.

On the other hand, Figure 3 is a detailed block diagram showing an embodiment of the camera DS 11 in Figure 1 with reference to this in more detail the operation of the camera DS 11 as follows.

When the camera DS 11 is in the playback mode (PB), one of the two-way ports port1 and port2 is designated as the image data input port according to the DRAM selection signal SEL2 received from the memory controller 13. The data selector 31 selects image data input through the designated bidirectional port and transmits the image data to the internal NTSC encoder.

For example, when the DRAM selection signal SEL2 is " low ", the mode of the bidirectional port 1 is set to the data input mode, while the bidirectional port 2 is set to the high impedance state, where the data The selector 31 selects data read-out from the first DRAM 12A through the bidirectional port 1 and transfers the data to the NTSC encoder. However, when the DRAM selection signal SEL2 is " high "

However, when the internal mode of the camera DSP 11 is the recording mode, the bidirectional ports port1 and port2 are both set to the output mode so that the image data processed inside the camera DSP 11 is directly the bidirectional port. After being stored in the first DRAM 12A and the second DRAM 12B through port1 and port2, the image data stored in one of the DRAMs on one side is used for the playback mode to immediately check the picture taken. The image data stored in the other DRAM is transferred to the CPU 14 and used for compression processing.

As described in detail above, in the present invention, when two DRAMs are used in a progressive CD-based digital still camera, the present invention centrally processes a license for another DRAM when one DRAM is in use. By taking over the device and causing the central processing unit to perform various processes using the corresponding DRAM, the utilization efficiency of the DRAM is maximized, thereby contributing to cost reduction.

Claims (3)

According to the DRAM selection signal SEL2 input from the memory controller 13 in the playback mode, video data read-out from the first DRAM 12A or the second DRAM 12B is encoded, output to the display means side, and recorded. In the mode, the camera DSP 11 for processing the image data input from the CD to record to the DRAM (12A), (12B); In accordance with the DRAM selection signal SEL1 supplied from the CPU 14, an access right to one of the DRAMs 12A and 12B is transferred to the CPU 14, and the remaining DRAM is transferred. A memory controller 13 for outputting various control signals RAS, CAS, OE / WE for access; In order to take over the access rights of any of the DRAMs 12A and 12B in the playback mode, the DRAM controller 13 outputs a DRAM selection signal SEL1 to the memory controller 13, and then accesses the corresponding DRAM and is input therefrom. A memory controller of a digital still camera, characterized by comprising a central processing unit (14) for compressing image data. The method of claim 1, wherein the camera DSP 11 determines the input and output direction of the data according to the DRAM selection signal SEL2 supplied from the memory controller 13, the first DRAM 12A and the second DRAM 12B. Bidirectional ports (port1) (port2) for inputting read-out data or outputting data processed in the camera DSP 11 to the first DRAM 12A and the second DRAM 12B; A digital selector 31 which selects data output from any one of the first DRAM 12A and the second DRAM 12B according to the DRAM selection signal SEL2 and transfers the data to the NTSC encoder. Memory control of still cameras. The memory controller (13) of claim 1, further comprising: an address generator (21) for generating an address for performing control authority for any of the DRAMs (12A) and (12B); According to the DRAM selection signal SEL1, various control signals RAS, CAS, OE / WE are generated in order to perform a control right for one of the DRAMs 12A and 12B. A control signal generator 22A which outputs together with the address outputted from the control panel) or transmits a corresponding control signal, an address and data supplied from the central processing unit 14; According to the DRAM selection signal SEL1, various control signals RAS, CAS, and OE / WE are generated to perform control of the other one of the DRAMs 12A and 12B and generate the address generator ( A control signal generator 22B which outputs together with the address output from 21) or transfers the corresponding control signal and address and data supplied from the central processing unit 14; A bidirectional buffer 23A for transferring data output from the control signal generator 22A to the corresponding DRAM side according to the DRAM selection signal SEL1; And a bidirectional buffer (23B) for transferring data output from the control signal generator (22B) to the corresponding DRAM side according to the DRAM selection signal (SEL1).

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