KR100253196B1 - Interrupt control method and apparatus of hipi+ bus - Google Patents

Abstract

PURPOSE: A method and apparatus for controlling an interrupt on a HIPI+ bus are provided to reduce a capacity of a controller through an arbitration device and use one set of a BTL transmitter-receiver and adapt a prior order at a round-robin in an internal arbitration of an interrupt handler by providing the arbitration device between internal processors when an interrupt controller is designed. CONSTITUTION: A HiPi+bus(10) is selected at a main calculator and applies the BTL standard. An MPIR(41) drives the HiPi+bus(10) in order that a selected interrupt transmission requesting signal may be processed by an interrupt handler in a system after performing an interrupt arbitration function when the interrupt transmission requesting signal is generated from processors(45A¯45D) in a module. An MPIH(42) confirms whether the interrupt transmission requesting signal is directly requested to one's module when the interrupt transmission requesting signal is inputted through the HiPi+bus(10), and if a condition is formed, the MPIH(42) performs the arbitration function, and stores an interrupt requesting responding signal of the selected processor in the internal register. A plurality of IRACs(43A¯43D) collect the interrupt transmission requesting signals generated from the MPIH(42) and the other interrupt sources and interrupt the processors(45A¯45D) in a module and request the process of the signals. An SBIB(44) provides a BTL transmitter-receiver and transmits an interrupt requesting signal between an interrupt control device(40) and the HiPi+bus(10).

Description

Interrupt control method and device on HiPi + bus

The present invention relates to a design technique of an interrupt controller that supports a plurality of processors on a HiPi + bus adopted by a main computer. In particular, the design of an interrupt controller overcomes the increase in capacity and implementation difficulties, and the specificity of signals due to the distance between buses. The present invention relates to an interrupt control method and apparatus on a HiPi + bus which prevents the deterioration and ensures fairness of an arbitrator in an interrupt handler.

HiPi + bus is a system bus adopted in main computer III system. Data transfer bus (DTB) for data transfer, interrupt bus (IB) for interrupt transfer, and utility bus (UB) for other additional functions. : Utility Bus). Among them, it supports communication between processors as a path of asynchronous signal exchange between bus modules connected to Interrupt bus HiPi + bus.

Typically, the main computer III system is a multiple processing unit (MPU) module 11, a memory module 12, an input / output processor (IOP) module 13 using the HiPi + bus 10 as an interconnect medium as shown in FIG. SCM (System Control Module) module 14, wherein the interrupt is used for asynchronous communication between the MPU, IOP, SCM.

Each module 11-14 has one or more processors, each of which sends an interrupt signal to another processor in the system or processes an interrupt requested by the module 11-14. As such, a controller that serves to transfer interrupts between processors using the HiPi + bus 10 as a transmission medium is defined as an interrupt controller.

A typical interrupt controller supporting one processor is shown in FIG.

In FIG. 2, MPIR (MPIR: Multi-Processor Interrupt Requester) 21 performs a function of transmitting an interrupt transmission request signal requested from a processor in a module to the HiPi + bus 10 side, and MPIH (MPIH: Multi-). Processor Interrupt Handler) 22 serves to accept the interrupt transfer request from the HiPi + bus 10. In addition, IRAC (Interrupt Acknowledge Controller) 23 collects interrupt processing request signals generated by the MPIH 22 and other interrupt sources, interrupts the processor in the module, and requests processing thereof.

In this case, the HiPi + bus 10 supports a BTL (Bus Transfer Logic) standard. Therefore, the SBIB (SBIB: System Bus Interface Block), which is a HiPi + bus interface block, includes BTL transceivers.

When there are several processors in one module, the above-mentioned interrupt controller is required as many as the number of processors mentioned above. Some problems arise when the existing interrupt controller is used as it is. Figure 3 shows an embodiment for such a case. Here, what cannot be overlooked is that the capacity of the controller is very large, which makes it difficult to implement and causes a load problem on the HiPi + bus.

However, in such a conventional interrupt control technique, when there are several processors in one module and using as many interrupt controllers as the number of processors, the interrupt controller needs relatively large capacity, thereby reducing the capacity of the entire controller. As it becomes very large, it is difficult to implement, and in addition, since the number of BTL transceivers is increased by the number of processors, the number of transceivers to which one signal is connected on the bus is greatly increased, thereby increasing the overall load and the distance between the bus and the transmission / reception period. Increase) the signal characteristics are very bad.

Therefore, the technical problem of the present invention is to place an arbiter between internal processors when designing an interrupt controller to reduce the capacity of the controller through the arbiter, use only one set of BTL transceivers, and round robin during internal arbitration of an interrupt handler. The present invention provides a method and apparatus for controlling interrupts on a HiPi + bus.

1 is an overall block diagram of a typical main computer.

2 is a block diagram of a typical interrupt controller supporting one processor.

3 is a block diagram of a typical interrupt controller supporting four processors.

4 is a block diagram of one embodiment of an interrupt device on a HiPi + bus in accordance with the present invention;

5 is a table of transmission information for each arbitration interrupt processing step in the present invention.

6 is a diagram illustrating an arbitration step in the main state machine of the interrupt handler according to the present invention;

7 is an arbitration flag control algorithm of an interrupt handler according to the present invention.

8 is a signal flow diagram for direct interrupt transmission / processing in the present invention.

9 is a signal flow diagram for arbitration interrupt transmission / processing in the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: HiPi + bus 41: MPIR

42: MPIH 43A-43D: IRAC

44: SBIB 45A-45D: Processor

In the interrupt control method on the HiPi + bus to achieve the object of the present invention, in the direct interrupt transfer / process mode, the MPIR generates an interrupt request signal by each processor, participates in HiPi + bus arbitration, selects an interrupt request signal, and then selects a target module. A first step (SA1-SA10) of requesting interrupt processing by the selected processor by sequentially transmitting the ID, its ID, and the vector of the ID, its ID, and the vector; In the moderation interrupt transmission / processing mode, the MPIR informs the MPIH that it has participated in arbitration of the interrupt transmission section, and when the interrupt request signal is selected, the ID, its ID, and the vector of the target module are transmitted to the MPIH side via the HiPi + bus. A second process (SB1-SB7); In the moderation interrupt transmission / processing mode, the MPIH internally arbitrates between processors after confirming that the current interrupt is an arbitration interrupt, and if MPIR is selected, the interrupt processing request generated on the HiPi + bus is the group to which it belongs. In the mediation between MPIHs, a third process (SC1-SC8) is performed to receive a vector from the MPIR and send a response signal when the condition is established.

4 is a block diagram of an exemplary embodiment of an interrupt control apparatus on a HiPi + bus for achieving another object of the present invention. As shown therein, a HiPi + bus 10 that is adopted by a main computer and supports a BTL standard; When the interrupt transfer request signal is generated from the processors 45A to 45D in the module, the HiPi + bus 10 is operated so that the selected interrupt request signal can be processed by the interrupt handler in the system after performing the interrupt arbitration function. A driving MPIR 41; When the interrupt transmission request signal is input through the HiPi + bus 10, it checks whether it is a direct interrupt request signal to its own module, and when the condition is established, performs an arbitration function and then internalizes the interrupt response request signal of the selected processor. MPIH 42 for storing in the register of; A plurality of IRACs 43A to 43D for collecting interrupt processing request signals generated from the MPIH 42 and other interrupt sources and interrupting each processor 45A to 45D in the module to request processing thereof; A SBIB 44 having a BTL transmitter and receiver for transmitting an interrupt request signal between the interrupt controller 40 and the HiPi + bus 10 is constructed.

The MPIR 41 has a separate interrupt response request register 41A to 41D for each interrupt 45A to 45D, but is a kind of controller for generating an interrupt request signal on the HiPi + bus 10. And a round-robin arbiter 42E for internally arbitrating the demands of the processors 45A to 45D.

The MPIH 42 is composed of one controller that responds to the occurrence of an interrupt request signal on the HiPi + bus 10 and separately holds the interrupt response request registers 42A to 42D required for an interrupt request for each processor 45A to 45D. The interrupt required for processing on the HiPi + bus 10 is, in principle, processed in a round robin manner between the processors 45A to 45D, and has a configuration having an arbiter 42E for this purpose. Here, the arbiter 42E is an arbiter to which priority checking function is given in order to ensure fairness in the interruption of arbitration.

When described in detail with reference to Figures 4 to 9 attached to the operation of the present invention configured as described above are as follows.

When each processor 45A to 45D writes interrupt request information to the interrupt response request registers 41A to 41D in the MPIR 41, the arbiter 41E in the MPIR 41 is based on a round robin method. After the arbitration is performed, the selected interrupt request signal is sent on the HiPi + bus 10, whereby the interrupt handler in the system is required to interrupt processing.

The types of interrupts defined on the HiPi + bus 10 are direct interrupts transmitted to a specific processor and arbitration interrupts transmitted through arbitration between interrupt handlers in a group by transmitting to an arbitrary group.

5 is a table showing transmission information for each step of an arbitration interrupt. The MPIR 41 finishes the role of confirming the processing acceptance result in the acknowledgment phase after transmitting the vector.

When an interrupt processing request signal is generated on the HiPi + bus 10 by the interrupt requester, the MPIH 42 checks whether it is a direct interrupt to its module. As a result of the above confirmation, the MPIH 42 internally attempts to arbitrate by the round robin method between the processors 45A to 45D, and receives the information of the selected processor from the interrupt response request register 42A. To 42D).

When the interrupt processing request signal activated on the HiPi + bus 10 is an arbitration interrupt signal and its own module belongs to the group, the MPIH 42 internally performs round robin between the processors 45A to 45D. As an ID of a processor selected by arbitration, the processor participates in mediation between the interrupt handlers IH of steps 2 through 16 in FIG. 5. Information is stored in its own interrupt register from among the interrupt response request registers 42A to 42D.

In performing the internal arbitration among the processors 45A to 45D during the arbitration interrupt, if only the round robin method is used, the processor that is masked may be selected even though there is a processor that does not mask the interrupt service. Additional mediation methods are needed to resolve.

That is, in the period from -5 to -1 in FIG. 5, if the processor selected by the internal arbitration among the processors 45A to 45D is interrupt masked and found to be masked, priority is given to the next processor. Pass it over. This is represented by the state machine of the interrupt handler IH, as shown in FIG. 6.

In other words, this priority check is performed between the ARB1 state and the ARB5 state in FIG. 6 to ensure fairness in internal arbitration. At this time, when the ID of the processor selected during arbitration between the internal processors 45A to 45D for arbitration interrupt is ai_flag, a control algorithm thereof is shown in FIG. 7.

That is, as shown in Fig. 7, when the interrupt signal is transferred to the next processor by round robin at the end of transmission of the interrupt signal, the MPIH (42) responsible for the arbitration state and the responsible state on the HiPi + bus 10 can infer the interrupt. Each time the clock passes the interrupt responsibility to the next processor by round robin, in other cases it is held by the responsible processor.

The interrupt response request stored in the interrupt response request registers 42A to 42D in the IPIH 42 is sent to the IRACs 43A to 43D. When the processing by the IRACs 43A to 43D ends, the interrupt response request is canceled. do.

When the interrupt response request signal stored in the interrupt response request registers 42A to 42D in the MPIH 42 is sent to the IRACs 43A to 43D, the IRACs 43A to 43D are all interrupt sources associated with the corresponding processor. In response to the priority, interrupt the corresponding processor among the processors 45A to 45D and send the corresponding vector in response to the interrupt of the corresponding processor.

The IRACs 43A to 43D exist for each processor, and they are implemented in the same structure as an interrupt controller supporting a single processor.

Meanwhile, FIG. 8 shows a signal flow diagram for direct interrupt transmission / processing in the interrupt control method according to the present invention. The transmission / processing process will be described in detail with reference to the following.

The MPIR 41 generates an interrupt request signal by each of the processors 45A to 45D, and arbitrates the transmission section (between processors). (SA1, SA2)

The MPIR 41 selects an interrupt request signal by participating in the HiPi + bus 10 arbitration. In this manner, the MPIR 41 informs the MPIH 42 whether the current interrupt is a direct interrupt or an arbitration interrupt. SA4)

Thereafter, the MPIR 41 transmits the ID of the target module and its ID to the HiPi + bus 10 side, and then transmits a vector to the HiPi + bus 10. (SA5 to SA7)

Thereafter, the MPIH 42 checks whether the response has been successfully transmitted to the HiPi + bus 10 side, and returns to the third step SA3 if the condition is not satisfied. Request interrupt processing (SA8 ~ SA10).

Meanwhile, FIG. 9 shows a signal flow diagram for an arbitration interrupt transmission / process in the interrupt control method according to the present invention. Referring to this, the transmission / process described above will be described in detail as follows.

When the MPIR 41 participates in interrupt transmission interval arbitration (SB1), it informs the MPIH 42 that the current interrupt is an arbitration interrupt (SB2), and the MPIH 42 confirms the fact (SC1) and then executes internal arbitration. In this case, the MPIR 41 and the MPIH 42 simultaneously handle interrupts. That is, the steps SB to SB7 and the steps SC1 to SC8 proceed simultaneously.

When the MPIR 41 participates in interrupt arbitration and selects an interrupt request signal (SB3), it transmits the ID of the target module to the HiPi + bus 10 side (SB4), waits for a predetermined time, and then transmits its ID and vector. (SB5).

Subsequently, when the response is received from the MPIH 42 side and the response state is "good", the process ends. Otherwise, the above processes (SB2 to SB6) are repeated.

On the other hand, the MPIH 42 confirms that the current interrupt is an arbitration interrupt, and internally performs arbitration between processors (SC1), and if the MPIR 41 is selected in the arbitration (SC2), the HiPi + bus 10 It is checked whether the interrupt processing request generated in the image is a group to which it belongs (SC3), and if the condition is established, it is checked whether it is selected in arbitration between MPIH 42 (SC4).

If it is determined that the self is selected as a result of the above check, it receives the vector from the MPIR 41 side (SC5) and sends a response signal to the path (SC6). Request and exit (SC7, SC8).

As described in detail above, the present invention can be easily implemented by reducing the capacity of the controller through the arbiter between internal processors when designing an interrupt controller supporting a plurality of processors on the HiPi + bus adopted in the host computer III system. In particular, by using only a set using a BTL transceiver, electrical instability on the bus is eliminated and stability is ensured. In addition, fairness is ensured by using a method that reinforces the priority of round robin during internal arbitration of an interrupt handler. It is effective to secure as much as possible.

Claims (5)

In the direct interrupt transmission / processing mode, the MPIR generates an interrupt request signal by each processor, participates in HiPi + bus arbitration, selects an interrupt request signal, and sequentially transmits the ID, its ID, and the vector of the target module. A first step of performing arbitration to request interrupt processing from a selected processor; In the moderation interrupt transmission / processing mode, the MPIR informs the MPIH that it has participated in arbitration of the interrupt transmission section, and when the interrupt request signal is selected, the ID, its ID, and the vector of the target module are transmitted to the MPIH side via the HiPi + bus. A second process of doing; In the moderation interrupt transmission / processing mode, the MPIH internally arbitrates between processors after confirming that the current interrupt is an arbitration interrupt, and if MPIR is selected, the interrupt processing request generated on the HiPi + bus is the group to which it belongs. And a third step of receiving a vector from the MPIR and transmitting a response signal when the condition is established by confirming that the user is selected in arbitration between MPIHs. The method of claim 1, wherein the second process and the third process are performed at the same time. HiPi + bus 10 is adopted to the host computer supporting the BTL standard; When an interrupt transfer request signal is generated from the processors 45A to 45D in the module, an MPIR for driving the HiPi + bus 10 so that the interrupt request signal selected through the interrupt arbitration process can be processed by the interrupt handler in the system. (41); When the interrupt transmission request signal is input through the HiPi + bus 10, it checks whether it is a direct interrupt request signal to its own module, and when the condition is established, performs an arbitration function and then internalizes the interrupt response request signal of the selected processor. MPIH 42 for storing in the register of; After collecting the interrupt processing request signals generated from the MPIH 42 and the other interrupt sources, a plurality of IRACs 43A to 43D which interrupt the respective processors 45A to 45D in the module and request processing thereof. Wow; And an SBIB (44) for transmitting an interrupt request signal between the interrupt controller (40) and the HiPi + bus (10), comprising a BTL transmitter and receiver. 4. The MPIR device according to claim 3, further comprising: a plurality of registers for separately storing interrupt request signals required for each processor; A controller for sending an interrupt request signal on the HiPi + bus 10; An interrupt control device on a HiPi + bus, comprising a round-robin arbitrator for internally mediating interrupt requests for each processor. 4. The MPIH 42 further comprises: an arbiter for processing an interrupt requested for processing on a HiPi + bus 10 in a round robin manner to select an interrupt response request signal of a processor; And a plurality of registers for storing the interrupt response request signal selected by the arbiter for each processor.

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