KR100253175B1 - Method for wafer alignment - Google Patents

Abstract

PURPOSE: A method for wafer alignment is provided to present oxide composite to easily align upper/lower wafers without using an expensive alignment device by inserting an alignment jig into nozzle parts of the upper/lower wafers. CONSTITUTION: First, an insulating layer(8) is deposited on back sides of at least two Si-wafers having circuit patterns formed on their front surfaces and then etched to form patterns. Then, the Si-wafers are etched in anisotropic solution to form a membrane(9) and a nozzle(10). Next, an alignment jig having uneven parts of same shape and size as those of the nozzle(10) are manufactured, and the jig is inserted into the Si-wafer to align a plurality of Si-wafers.

Description

Wafer Alignment

1 is a partial perspective view of a conventional wafer alignment method.

2 is a relationship between the silicon wafer and the alignment pins in FIG.

3 is a wafer alignment structure diagram of the present invention.

Figure 4 (a) or (b) is a wafer alignment process diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: upper wafer 2: lower wafer

3: V-groove 4: Alignment pin

5: alignment jig 6: transparent electrode

7: protective film 8: insulating film

9: membrane 10: nozzle

11: etch stop layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer alignment method, and more particularly, to a wafer alignment method that enables easy and quick alignment of two or more wafers without expensive equipment such as a double or an IR aligner. It is about.

FIG. 1 is a partial perspective view of a conventional wafer alignment method, in which an alignment pin 4, which is an optical fiber, is inserted into an upper and lower wafers 1 and 2 on which a V-groove 3 is formed. Four V-grooves 3 are formed in the upper and lower wafers 1 and 2, and alignment pins 4 are inserted into the V-grooves 3, respectively.

Referring to the conventional wafer alignment method configured as described above is as follows.

In general, anisotropic etching of the silicon wafer in the (100) direction forms a V-groove 3 in the (111) direction on the silicon wafer surface. It is known that the angle θ in the thus formed V-groove 3 is 57.74 ° by the crystallographic side of the single crystal silicon as shown in FIG. Therefore, when the alignment pin 4 is inserted into the V-groove 3, considering the size of the alignment pin 4 and the surface width 2L of the V-groove 3 in advance, the V-groove 3 The surface width (2L) of can be calculated as follows.

2L = 2R / Sinθ

As an example, an optical fiber having a diameter of 125 μm is used as the material of the alignment pin 4, and the width 2L of the V-groove 3 is 154 μm.

Four V-grooves 3 are formed on the upper and lower wafers 1 and 2, and alignment pins 4 having a diameter of 125 μm are formed on the V-grooves 3 formed on the lower wafers 2. Two or more wafer alignments were performed while rotating the upper wafer 1, respectively.

However, in the conventional wafer alignment method, when bonding two wafers due to manufacturing difficulties or necessity of manufacturing a three-dimensional structure when fabricating a sensor or an actuator, the wafers are aligned at a precision of 2 μm or less and then a high temperature of 500-1000 ° C. The process must be done before the alignment pins are removed. In this case, the wafer alignment may be disturbed, and if the alignment pin is not removed, a problem of manufacturing an alignment pin made of a material having a thermal expansion coefficient similar to that of silicon is required. There was a damaging problem.

In order to solve this problem, the present invention is to form an alignment jig having an unevenness in the upper and lower wafers by boiling etching at the alignment position, and to produce an alignment jig having irregularities of the nozzle dimension. The wafer alignment method of the upper and lower wafers is inserted into the nozzle portion of the upper and lower wafers so that the upper and lower wafers can be easily aligned without an expensive sorter, which will be described in detail with reference to the accompanying drawings.

3 is a wafer alignment configuration diagram of the present invention, in which an alignment jig 5 having an unevenness of nozzle dimensions is inserted through a nozzle in the upper and lower wafers 1 and 2, in which nozzles are formed and matched. do.

Referring to Figure 4 attached to the wafer alignment method of the present invention configured as described above is as follows.

4 is a process drawing of the wafer alignment method of the present invention. As shown in FIG. 4A, a transparent electrode 6 is formed on the front surface, and a protective film 7 is deposited thereon to form a circuit. After the insulating film 8 is deposited on the back surface of the formed wafer, the insulating film 8 is etched using a photolithography process.

At this time, the width (2L) of the etching window (Etch Window) of the portion where the nozzle is to be located should be the thickness (t) of the wafer, so the width (2L) when etching the insulating film 8 should be 2L> 2t / Sinθ. .

Here, the position of the etching window is determined by referring to the existing alignment position.

For example, in order to form a nozzle on a 400 μm silicon wafer, the etching window should have a dimension of at least one side of at least 566 μm.

Subsequently, when the wafer formed as described above is etched into the anisotropic etching solution, the membrane 9 and the nozzle 10 are formed while being enclosed in the (111) direction as shown in FIG.

At this time, the nozzle 10 should penetrate the wafer, and the membrane 9 should not penetrate the wafer.

Therefore, the etch stop layer 11 doped with boron thick is formed in advance on the surface on which the membrane 9 is to be formed.

Alternatively, the membrane 9 may be formed using an etching delay method.

The alignment jig 5 having the upper and lower wafers manufactured as described above and matching the nozzle 10 of the upper and lower wafers and the unevenness of the etching window dimensions are fabricated, and the alignment jig 5 is replaced by the upper and lower wafers ( When mechanically inserted into 1) (2), the upper and lower wafers 1 and 2 can be aligned as shown in FIG.

As described above, the present invention can easily align the upper and lower silicon wafers without an expensive sorter, and also reduce the labor and cost required for fabrication and removal without the need for alignment pins between wafers. In addition, there is an effect that can directly bond the wafer and the wafer.

Claims (3)

Depositing an insulating film 8 on the back surface of two or more silicon wafers having a circuit pattern formed on the front surface, and then forming a pattern, and etching the silicon wafer in an anisotropic solution to remove the membrane 9 and the nozzle 10. Forming the alignment jig 5 having the same size, shape, and position as the nozzle 10, and inserting the alignment jig 5 into the silicon wafer to align the plurality of silicon wafers. Wafer alignment method. The method of claim 1, wherein the width of the etching window (2L) for forming the nozzle (10) is larger than 2t / Sin θ. The wafer alignment method according to claim 1, wherein the membrane (9) is formed in advance on the front surface of the silicon wafer or by a visual delay method.