KR100252060B1 - Self-refresh mode controller - Google Patents

Abstract

PURPOSE: A controller for controlling a self-refresh mode of a DRAM(Dynamic Random Access Memory) is provided to perform a self-refresh mode when a power source is not applied to the DRAM or when a user selects the self-refresh mode. CONSTITUTION: The controller includes a reset signal delayer(211), an enable signal generator(221), a logic gate(231), a controller(241), an initial signal generator(251) and a strobe signal generator(261). The reset signal delayer(211) delays the first reset signal(NRESET). The enable signal generator(221) generates a refresh enable signal(NDISABLED) according to the first reset signal(NRESET) and the second reset signal(REN) which is activated by a user. The logic gate(231) generates a pulse signal according to the first reset signal(NRESET), an output signal from the reset signal delayer(211), and the refresh enable signal(NDISABLED). The controller(241) sequentially generates a column-address-strobe reset signal(NresetCAS) and a row-address-strobe reset signal(NresetRAS) according to the pulse signal from the logic gate(231) or the refresh enable signal(NDISABLED). The initial signal generator(251) generates an address-strobe initializing signal(ADDCLR) according to the row-address-strobe reset signal(NresetRAS). The strobe signal generator(261) sequentially generates a column-address-strobe signal(nCAS) and a row-address-strobe signal(nRAS) according to the column-address-strobe reset signal(NresetCAS) and a row-address-strobe reset signal(NresetRAS).

Description

Self-Refresh Mode Controller of DRAM Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a self refresh mode controller for controlling a self refresh mode of a DRAM (DRAM).

Microcontrollers are used to control the system electronically, and large-capacity DRAMs are used together with the microcontroller for more diverse control of the system. Microcontrollers store data in the DRAM and read the stored data. In the data storage and reading process, the power supply voltage may be interrupted at an unexpected moment. If the power supply voltage is interrupted, the data stored in the DRAM will be instantly destroyed. To prevent this, a backup power source, such as a battery, is used. However, if the backup power is not immediately connected when the power supply is interrupted, all data stored in the DRAM will be lost. If the data stored in the DRAM is destroyed, the microcontroller will not be able to play its original role, causing the system to malfunction.

Therefore, there is an urgent need for a method of preserving data stored in the DRAM in the event of an unexpected power supply interruption as described above. One way to preserve the data stored in the DRAM in case of power supply interruption is to allow the DRAM to enter the self-refresh mode. This is because the data stored in the DRAM can be preserved as long as the DRAM can enter the self refresh mode.

An object of the present invention is to provide a self-refresh mode controller of a DRAM semiconductor device capable of entering the DRAM semiconductor device into a self-refresh mode when the power supply voltage is momentarily interrupted or according to a user's selection.

1 is a schematic diagram of a substrate having a microcontroller and a DRAM semiconductor device for explaining the present invention.

2 is a circuit diagram of a self refresh mode controller of a DRAM semiconductor device according to a preferred embodiment of the present invention.

3 is a timing diagram of the self-refresh mode controller shown in FIG.

The present invention to achieve the above technical problem,

A self-refresh mode controller of a DRAM semiconductor device including a reset signal delay unit, a refresh enable signal generator, a logic gate, a controller, an address strobe initialization signal generator, and a strobe signal generator is provided.

The reset signal delay unit delays the first reset signal that is activated when the power supply voltage is interrupted for a predetermined time.

The refresh enable signal generator generates a refresh enable signal in response to the first reset signal or a second reset signal activated according to a user's selection.

The logic gate generates a pulse signal in response to an output of the first reset signal, the reset signal delay unit, and the refresh enable signal.

The controller sequentially generates a column address strobe reset signal and a row address strobe reset signal in response to a pulse signal output from the logic gate or the refresh enable signal.

The address strobe initialization signal generator generates an address strobe initialization signal in response to the row address strobe reset signal.

The strobe signal generator is initialized in response to the address strobe initialization signal and sequentially generates a column address strobe signal and a row address strobe signal in response to the column address strobe reset signal and the row address strobe reset signal.

According to the present invention, even if the power supply voltage is momentarily interrupted, the data embedded in the DRAM semiconductor device is preserved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a substrate having a microcontroller and a DRAM semiconductor device for explaining the present invention. Referring to FIG. 1, a DRAM semiconductor device 111, a microcontroller 121, a self-refresh mode controller 131, a power supply 141, a reset signal generator 151 of a DRAM semiconductor device may be disposed on a substrate 101. The battery 161 and the switch 171 are provided.

The power supply 141 receives a power supply voltage Vcc from an external source and supplies a power supply voltage for operating the microcontroller 121 and the DRAM semiconductor device 111.

The microcontroller 121 receives a power voltage from the power supply 141 to store data in the DRAM semiconductor device 111 or read data stored in the DRAM semiconductor device 111.

When the supply of the power voltage by the power supply 141 is stopped, the reset signal generator 151 detects this and generates a first reset signal NRESET and transmits it to the microcontroller 121.

When the supply voltage of the battery 161 is stopped from the power supply 141, the battery 161 supplies a power voltage to the DRAM semiconductor device 111 instead of the power supply 141 to cause the DRAM semiconductor device 111. Keep the data stored inside.

The switch 171 connects the power supply 141 and the DRAM semiconductor device 111 while the power supply 141 supplies a power voltage, and stops supplying power voltage from the power supply 141. In this case, the battery 161 is connected to the DRAM semiconductor device 111.

The self-refresh mode controller 131 of the DRAM semiconductor device enters the DRAM semiconductor device 111 into a self-refresh mode when the power voltage supplied from the power supply 141 is stopped, thereby allowing the DRAM semiconductor device 111 to enter the self-refresh mode. This ensures that the data stored in the file is not destroyed but still preserved. The self refresh mode controller 131 of the DRAM semiconductor device may be connected between the DRAM semiconductor device 111 and the microcontroller 121 or may be embedded in the microcontroller 121.

As soon as the supply of the power voltage from the power supply 141 is stopped, the column address strobe signal and the row address strobe signal should be sequentially activated to the low level in order to enter the DRAM semiconductor device 111 into the self refresh mode. . At this time, the row address strobe signal should be kept active for more than 100 [ms]. Thus, the DRAM semiconductor device 111 may enter the self refresh mode. As described above, the entry of the DRAM semiconductor device 111 into the refresh mode as the column address strobe signal is activated to the logic low before the row address strobe signal is referred to as a column address strobe before row address strobe (CBR) refresh mode. In order to maintain the row address strobe signal in an active state of 100 [ms] or more, a pull down or pull up is performed between the self-refresh mode controller 111 of the DRAM semiconductor device and the DRAM semiconductor device 111. The circuit 181 is connected. By providing the pull-down or pull-up circuit 181, not only the row address strobe signal but also the column address strobe signal are kept active. It is also necessary to connect a tri-state buffer (not shown) to prevent any glitch from being applied to the row address strobe signal and the column address strobe signal.

2 is a circuit diagram of a self refresh mode controller 131 of a DRAM semiconductor device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the self refresh mode controller 131 of the DRAM semiconductor device may include a reset signal delay unit 211, a refresh enable signal generator 221, a logic gate 231, a controller 241, and an address strobe initialization. The signal generator 251 and the strobe signal generator 261 are provided.

The reset signal delay unit 211 receives a first reset signal NRESET and outputs the first reset signal NRESET by a predetermined time in synchronization with a clock signal SCLK. The reset signal delay unit 211 includes first and second flip-flops 271 and 272. The first flip-flop 271 receives the first reset signal NRESET and transmits the first reset signal NRESET in synchronization with a clock signal SCLK. In this case, the first flip-flop 271 transmits the first reset signal NRESET when the clock signal SCLK falls to a low level. The second flip-flop 272 receives a first reset signal NRESET output from the first flip-flop 271 and is output from the first flip-flop 271 in synchronization with the clock signal SCLK. The first reset signal NRESET is transmitted. At this time, the second flip-flop 272 is a first reset signal (NRESET) output from the first flip-flop 271 when the clock signal (SCLK) rises from a low level to a high level (high level) Send it. The first reset signal NRESET output from the reset signal delay unit 211 is input to the logic gate 231. As such, the first reset signal NRESET input to the reset signal delay unit 211 is delayed by one period of the clock signal SCLK by the first and second flip-flops 271 and 272.

The refresh enable signal generator 221 inputs the first reset signal NRESET and a second reset signal REN that is activated according to a user's selection and is synchronized with the clock signal SCLK to enable the refresh enable signal. Issue (NDISABLED). The refresh enable signal NDISABLED is reset to a logic low when the first reset signal NRESET is active as a logic low, and the refresh in when the first reset signal NRESET is inactive as a logic high. The enable signal NDISABLED does not respond to the first reset signal NRESET. Instead, the refresh enable signal NDISABLED responds to the second reset signal REN in synchronization with the clock signal SCLK. The refresh enable signal NDISABLED outputs the second reset signal REN as the refresh enable signal NDISABLED whenever the clock signal SCLK rises from a low level to a high level. That is, each time the clock signal SCLK rises from a low level to a high level, when the second reset signal REN is at a high level, the refresh enable signal NDISABLED is generated as a logic high and the second reset is performed. If the signal REN is at a low level, the refresh enable signal NDISABLED is generated as a logic low.

The logic gate 231 generates a pulse signal in response to the output of the first reset signal NRESET and the reset signal delay unit 211 and the refresh enable signal NDISABLED. The logic gate 231 includes an AND product 233 and an AND logic unit 235. The logical product means 233 inputs the output of the reset signal delay unit 211 and the first reset signal NRESET, and the output of the reset signal delay unit 211 is logic high, 1 Logic high is output only when the reset signal (NRESET) is logic low. The negative OR means 235 inputs the output of the AND product 233 and the refresh enable signal NDISABLED, and both the output of the AND product 233 and the refresh enable signal NDISABLED are logic. Logic high is output only when low.

The controller 241 sequentially generates a column address strobe reset signal NresetCAS and a row address strobe reset signal NresetRAS in response to a pulse signal output from the logic gate 231 or the refresh enable signal NDISABLED. do. The controller 241 includes third to eighth flip-flops 273 to 278.

The third flip-flop 273 receives an output of the logic gate 231 and the refresh enable signal NDISABLED. When the output of the logic gate 231 is logic low, the third flip-flop 273 is set to logic high regardless of the refresh enable signal NDISABLED, and the logic gate 231 If the output of is a logic high, the output responds to the refresh enable signal NDISABLED. When the output of the logic gate 231 is at a high level, the third flip-flop 273 transmits the refresh enable signal NDISABLED in synchronization with the clock signal SCLK. That is, whenever the refresh enable signal NDISABLED is high level, the third flip-flop 273 is generated as a logic high whenever the clock signal SCLK rises from a logic low to a logic high. If the refresh enable signal NDISABLED is low, its output is generated as a logic low.

The fourth flip-flop 274 inputs the output of the logic gate 231 and the output of the third flip-flop 273. If the output of the logic gate 231 is a logic low, the fourth flip-flop 274 is set to a logic high regardless of the output of the third flip-flop 273, and the output of the logic gate 231 If the output is logic high, the output is responsive to the output of the third flip-flop 273. When the output of the logic gate 231 is at a high level, the fourth flip-flop 274 transmits the output of the third flip-flop 273 in synchronization with the clock signal SCLK. That is, the fourth flip-flop 274 is generated as logic high when the output of the third flip-flop 273 is high level whenever the clock signal SCLK goes from logic high to logic low. If the output of the third flip-flop 273 is at a low level, the output is generated as a logic low.

The refresh enable signal NDISABLED is delayed by one period of the clock signal SCLK while passing through the third and fourth flip-flops 273 and 274.

The fifth flip-flop 275 receives an output of the logic gate 231 and an output of the fourth flip-flop 274. If the output of the logic gate 231 is a logic low, the fifth flip-flop 275 is set to a logic high regardless of the output of the fourth flip-flop 274, and the output of the logic gate 231 If the output is logic high, the output is responsive to the output of the fourth flip-flop 274. When the output of the logic gate 231 is at the high level, the fifth flip-flop 275 transmits the output of the fourth flip-flop 274 in synchronization with the clock signal SCLK. That is, the fifth flip-flop 275 is generated as logic high when the output of the fourth flip-flop 274 is high level whenever the clock signal SCLK rises from a logic low to a logic high. If the output of the fourth flip-flop 274 is at a low level, the output is generated as a logic low.

The sixth flip-flop 276 inputs the output of the logic gate 231 and the output of the fifth flip-flop 275 and generates the column address strobe reset signal NresetCAS. The column address strobe reset signal NresetCAS is set to a logic high regardless of an output when the output of the logic gate 231 is logic low, and the fifth flip-flop when the output of the logic gate 231 is logic high. 275). When the output of the logic gate 231 is at the high level, the sixth flip-flop 276 inputs the output of the fifth flip-flop 275 in synchronization with the clock signal SCLK to input the column address strobe reset signal. Generate (NresetCAS). That is, the sixth flip-flop 276 generates the column address strobe reset signal NresetCAS when the output of the fifth flip-flop 275 is at a high level whenever the clock signal SCLK falls from a logic high to a logic low. ) Is generated as a logic high, and when the output of the fifth flip-flop 275 is at a low level, the column address strobe reset signal NresetCAS is generated as a logic low.

The output of the fourth flip-flop 274 is generated as the column address strobe reset signal NresetCAS after being delayed by one period of the clock signal SCLK while passing through the fifth and sixth flip-flops 275 and 276. .

The seventh flip-flop 277 receives the output of the logic gate 231 and the column address strobe reset signal NresetCAS. The output of the seventh flip-flop 277 is set to logic high regardless of the column address strobe reset signal NresetCAS when the output of the logic gate 231 is logic low, and the output of the logic gate 231 If it is logic high, it responds to the column address strobe reset signal NresetCAS. The seventh flip-flop 277 inputs the column address strobe reset signal NresetCAS in synchronization with the clock signal SCLK when the output of the logic gate 231 is at a high level. That is, the seventh flip-flop 277 is generated as a logic high whenever the column address strobe reset signal NresetCAS is at a high level whenever the clock signal SCLK rises from a logic low to a logic high. If the column address strobe reset signal NresetCAS is at a low level, its output is generated as a logic low.

The eighth flip-flop 278 receives the output of the logic gate 231 and the output of the seventh flip-flop 277 and generates the row address strobe reset signal NresetRAS. The row address strobe reset signal NresetRAS is set to logic high regardless of the output of the seventh flip-flop 277 when the output of the logic gate 231 is logic low, and the output of the logic gate 231 If logic high, the row address strobe reset signal NresetRAS responds to the output of the seventh flip-flop 277. When the output of the logic gate 231 is at a high level, the eighth flip-flop 278 transmits the output of the seventh flip-flop 277 in synchronization with the clock signal SCLK. That is, the eighth flip-flop 278 generates the row address strobe reset signal NresetRAS when the output of the seventh flip-flop 277 is at a high level whenever the clock signal SCLK falls from a logic high to a logic low. ) Is generated as a logic high, and when the output of the seventh flip-flop 277 is at a low level, the row address strobe reset signal NresetRAS is generated as a logic low.

The column address strobe reset signal NresetCAS is delayed by one period of the clock signal SCLK while passing through the seventh and eighth flip-flops 277 and 278. Therefore, the row address strobe reset signal NresetRAS is generated one cycle after the clock signal SCLK than the column address strobe reset signal NresetCAS.

The address strobe initialization signal generator 251 generates an address strobe initialization signal ADDCLR in response to the row address strobe reset signal NresetRAS. The address strobe initialization signal generator 251 generates the address strobe initialization signal ADDCLR as a logic low when the row address strobe reset signal NresetRAS is a logic high to generate a row generated from the strobe signal generator 261. Initialize the address strobe signal nRAS and the column address strobe signal nCAS to a logic high, and if the row address strobe reset signal NresetRAS is a logic low, generate the address strobe initialization signal ADDRC as a logic high to generate the row. This does not affect the address strobe signal nRAS and the column address strobe signal nCAS.

The strobe signal generator 261 is initialized in response to the address strobe initialization signal ADDCLR and in response to the column address strobe reset signal NresetCAS and the row address strobe reset signal NresetRAS, the column address strobe signal nCAS. ) And the row address strobe signal nRAS are sequentially generated. The strobe signal generator 261 includes ninth to twelfth flip-flops 279 to 282.

The ninth flip-flop 279 receives the address strobe initialization signal ADDCLR, the row address strobe reset signal NresetRAS, and a control signal and generates a row address strobe signal nRAS. The row address strobe signal nRAS is set to a logic high when the address strobe initialization signal ADDRLR is logic low, and the row address strobe reset signal NresetRAS or the value when the address strobe initialization signal ADDRLR is logic high. Respond to the control signal. The row address strobe signal nRAS is reset to a logic low when the row address strobe reset signal NresetRAS is logic low, and the address strobe initialization signal ADDRLR when the row address strobe reset signal NresetRAS is logic high. In response to the control signal.

The row address strobe signal nRAS responds to the control signal when both the address strobe initialization signal ADDCLR and the row address strobe reset signal NresetRAS are logic high. The ninth flip-flop 279 may input the control signal in synchronization with the clock signal SCLK when the address strobe initialization signal ADDCLR and the row address strobe reset signal NresetRAS are at a high level to input the control signal. Generates a strobe signal nRAS. That is, the ninth flip-flop 279 generates the row address strobe signal nRAS as logic high whenever the control signal is high level whenever the clock signal SCLK rises from a logic low to a logic high, When the control signal is at a low level, the row address strobe signal nRAS is generated as a logic low.

The tenth flip-flop 280 receives the address strobe initialization signal ADDCLR, the column address strobe reset signal NresetCAS and a control signal, and generates a column address strobe signal nCAS. The column address strobe signal nCAS is set to a logic high when the address strobe initialization signal ADDCLR is logic low, and the column address strobe reset signal NresetCAS or the value when the address strobe initialization signal ADDCLR is logic high. Respond to the control signal. The column address strobe signal nCAS is reset to a logic low when the column address strobe reset signal NresetCAS is a logic low, and the address strobe initialization signal ADDRLR when the column address strobe reset signal NresetCAS is a logic high or In response to the control signal.

The column address strobe signal nCAS responds to the control signal when both the address strobe initialization signal ADDCLR and the column address strobe reset signal NresetCAS are logic high. The tenth flip-flop 280 may input the control signal in synchronization with the clock signal SCLK when the address strobe initialization signal ADDCLR and the column address strobe reset signal NresetCAS are at a high level to input the control signal. Generates a strobe signal nCAS. That is, each time the clock signal SCLK rises from a logic low to a logic high, the tenth flip-flop 280 generates the column address strobe signal nCAS as a logic high when the control signal is at a high level. When the control signal is at a low level, the column address strobe signal nCAS is generated as a logic low.

The eleventh flip-flop 281 receives the first reset signal NRESET and the control signal and generates an output enable signal. The output enable signal is set to a logic high when the first reset signal NRESET is logic low, and responds to the control signal when the first reset signal NRESET is logic high. The eleventh flip-flop 281 generates the output enable signal by inputting the control signal in synchronization with the clock signal SCLK when the first reset signal NRESET is at a high level. That is, the eleventh flip-flop 281 generates the output enable signal as a logic high whenever the control signal is at a high level whenever the clock signal SCLK rises from a logic low to a logic high, and the control signal. Is a low level, generating the output enable signal as a logic low.

The twelfth flip-flop 282 inputs the first reset signal NRESET and the control signal and generates a write enable signal. The write enable signal is set to a logic high when the first reset signal NRESET is logic low, and responds to the control signal when the first reset signal NRESET is logic high. The twelfth flip-flop 282 generates the write enable signal by inputting the control signal in synchronization with the clock signal SCLK when the first reset signal NRESET is at a high level. That is, the twelfth flip-flop 282 generates the write enable signal as a logic high whenever the control signal is at a high level whenever the clock signal SCLK rises from a logic low to a logic high, and the control signal. Is a low level, the write enable signal is generated as a logic low.

FIG. 3 is a timing diagram of the self refresh mode controller shown in FIG. 2. Referring to FIG. 3, when the supply voltage starts to be stopped, the first reset signal NRESET is activated as a logic low. As a result, the address strobe initialization signal ADDCLR is activated to a logic low. When the first reset signal NRESET and the address strobe initialization signal ADDCLR are activated as logic low, the column address strobe signal nCAS and the row address strobe signal nRAS are sequentially activated as logic low. At this time, when the column address strobe signal nCAS and the row address strobe signal nRAS are in a logic low state, they are first initialized to a logic high and then activated to a logic low. Since the column address strobe signal nCAS and the row address strobe signal nRAS are sequentially activated as logic lows, the DRAM semiconductor device 111 enters the self refresh mode. The self refresh mode of the DRAM semiconductor device 111 is continued while the power supply voltage is interrupted.

Then, when the supply voltage is resumed, the first reset signal NRESET is inactive at a logic high, whereby the address strobe initialization signal ADDCLR is also inactive at a logic high. As the address strobe initialization signal ADDCLR is inactive as logic high, the row address strobe signal nRAS and the column address strobe signal nCAS are initialized as logic high.

An operation of the circuit illustrated in FIGS. 1 and 2 will be described with reference to FIG. 3.

The DRAM semiconductor device 211 continuously stores data stored therein while power is supplied from the power supply 141, but loses data stored therein when the power supply is stopped from the power supply 141. Accordingly, the DRAM semiconductor device 111 receives a power voltage through the battery 161 to keep data stored therein even when the power voltage is interrupted from the power supply 141. However, when the power supply voltage is stopped from the power supply 141 while the microcontroller 121 writes data to the DRAM semiconductor device 111, the data written in the DRAM semiconductor device 111 may be partially lost. Can be destroyed. As such, even if the supply of the power voltage from the power supply 141 is stopped, the DRAM semiconductor device 111 may be put into the self-refresh mode in order to preserve data stored in the DRAM semiconductor device 111.

When the supply of the power voltage from the power supply 141 is stopped, the first reset signal NRESET generated from the reset signal generator is activated from logic high to logic low. The first reset signal NRESET is maintained at a high level while the power supply voltage is supplied. When the first reset signal NRESET is activated to a logic low, the output enable signal nOE and the write enable signal nWE are first initialized to a logic high.

When the first reset signal NRESET is activated, the output of the AND product 233 of the logic gate 231 is immediately logic high. The output of the reset signal delay unit 211 is maintained at a logic high state until the first reset signal NRESET is activated. If the output of the AND product 233 is logic high, the negation AND means 235 of the logic gate 231 goes to the logic low regardless of the second reset signal REN. Since the output of the logic gate 231 is a logic low, the outputs of the third to eighth flip-flops 273 to 278 of the controller 241 are all set to logic high. Therefore, both the column address strobe reset signal NresetCAS and the row address strobe reset signal NresetRAS are set to logic high. By the set row address strobe reset signal NresetRAS, the address strobe initialization signal generator 251 sets the address strobe initialization signal ADDCLR to a logic low level and applies it to the strobe signal generator 261. Then, both the row address strobe signal nRAS and the column address strobe signal nCAS are initialized to logic high.

While the column address strobe signal nCAS and the row address strobe signal nRAS are initialized, the active first reset signal NRESET is logic of the logic gate 231 through the reset signal delay unit 211. It is input to the product means 233. The output of the AND product 233 then transitions from logic high to logic low and is input to the negation logic means 235 of the logic gate 231. In this case, the refresh enable signal generator 221 generates the refresh enable signal NDISABLED as a logic low in response to the activated first reset signal NRESET. Since the output of the AND product 233 and the output of the refresh enable signal generator 221 are both logic lows, the output of the NOR 235 transitions from a logic low to a logic high. That is, the logic gate 231 generates a low pulse signal as the first reset signal NRESET is activated.

When the output of the logic gate 231 becomes logic high, the third to eighth flip-flops 273 to 278 of the controller 241 respond to the refresh enable signal NDISABLED. The refresh enable signal NDISABLED is transmitted through third to eighth flip-flops 273 to 278 in synchronization with the clock signal SCLK. Since the refresh enable signal NDISABLED is a logic low, the column address strobe reset signal NresetCAS and the row address strobe reset signal NresetRAS are respectively activated as logic lows, so that the ninth and the strobe signal generation unit 261 are applied. The column address strobe signal nCAS and the row address strobe signal nRAS are both activated to a logic low level by being applied to the tenth flip-flops 279 and 280. In this case, since the column address strobe reset signal NresetCAS is activated by one cycle of the clock signal SCLK before the row address strobe reset signal NresetRAS, the column address strobe signal nCAS is also the row address strobe signal. It is activated before (nRAS). Both the column address strobe signal nCAS and the row address strobe signal nRAS are activated, but the column address strobe signal nCAS is activated before the row address strobe signal nRAS, ie, the CBR mode is used. The semiconductor device 111 enters the self refresh mode.

According to a user's selection, the DRAM semiconductor device 111 enters the self refresh mode even when the second reset signal REN is activated to a logic low level. The operation will be described. The first reset signal NRESET is maintained at a logic high while a power supply voltage is supplied from the power supply 141. Thus, the output of the AND product 233 of the logic gate 231 is maintained as a logic low. When the first reset signal NRESET is logic high, the refresh enable signal generator 221 responds to the second reset signal REN. Since the second reset signal REN is logic low, the refresh enable signal NDISABLED becomes logic low. Since the refresh enable signal NDISABLED and the output of the AND product 233 are both logic lows, the output of the logic gate 231, that is, the output of the negating logic means 235, is logic high. Since the output of the logic gate 231 is logic high, the third to eighth flip-flops 273 to 278 of the controller 241 respond to the refresh enable signal NDISABLED. If the refresh enable signal NDISABLED is logic low, the column address strobe reset signal NresetCAS and the row address strobe reset signal NresetRAS are logic low, and the ninth and tenth operations of the strobe signal generator 261 are performed. Flip-flops 279 and 280 are reset. That is, the column address strobe signal nCAS and the row address strobe signal nRAS are both activated as logic lows. At this time, since the column address strobe reset signal NresetCAS is generated one cycle earlier than the row address strobe reset signal NresetRAS by one cycle of the clock signal SCLK, the column address strobe signal nCAS is also the row address strobe signal. It is activated before (nRAS). Therefore, the DRAM semiconductor device 111 enters the self refresh mode.

When the power supply is supplied again from the power supply 141, the first reset signal NRESET transitions to a logic high. When the first reset signal NRESET becomes logic high, the refresh enable signal NDISABLED becomes logic high. The second reset signal REN is maintained at a logic high state during normal operation. When the first reset signal NRESET is logic high, the refresh enable signal NDISABLED becomes logic high because it responds to the second reset signal REN. Since the refresh enable signal NDISABLED is logic, the output of the logic gate 231 is logic low. The row address strobe reset signal NresetRAS is then logic high, and the address strobe initialization signal ADDCLR is also logic low. Therefore, the column address strobe signal nCAS and the row address strobe signal nRAS are set to logic high. Since the column address strobe signal nCAS and the row address strobe signal nRAS are logic high, the DRAM semiconductor device 111 no longer enters the self refresh mode.

The best embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the self-refresh mode controller 131 of the DRAM semiconductor device according to the present invention, when the power supply voltage is interrupted, the DRAM semiconductor device 111 enters the self-refresh mode to enter the internal structure of the DRAM semiconductor device 111. Data stored in can be saved. In addition, power consumption is reduced by operating only the DRAM semiconductor device 111 without operating the microcontroller 121 according to a user's selection.

Claims (8)

A reset signal delay unit configured to delay a first reset signal that is activated when a power supply voltage is stopped for a predetermined time; A refresh enable signal generator configured to generate a refresh enable signal in response to the first reset signal or a second reset signal activated according to a user's selection; A logic gate configured to generate a pulse signal in response to an output of the first reset signal, the reset signal delay unit, and the refresh enable signal; A controller configured to sequentially generate a column address strobe reset signal and a row address strobe reset signal in response to a pulse signal output from the logic gate or the refresh enable signal; An address strobe initialization signal generator configured to generate an address strobe initialization signal in response to the row address strobe reset signal; And And a strobe signal generation unit initialized in response to the address strobe initialization signal and sequentially generating a column address strobe signal and a row address strobe signal in response to the column address strobe reset signal and the row address strobe reset signal. Self-refresh mode controller of DRAM semiconductor device. The self-refresh mode controller of claim 1, wherein the reset signal delay unit comprises a flip-flop to transmit the first reset signal in synchronization with a clock signal. The display device of claim 1, wherein the refresh enable signal generator resets the refresh enable signal when the first reset signal is activated, and synchronizes the second reset signal with a clock signal when the first reset signal is in an inactive state. And a flip-flop for inputting the refresh enable signal to generate the refresh enable signal. 2. The logic gate of claim 1 wherein the logic gate is Logical multiplication means for inputting the output of the reset signal delay unit and the first reset signal and outputting a logic high only when the output of the reset signal delay unit is logic high and the first reset signal is logic low; And And a negative logic OR means for inputting the output of the AND product and the refresh enable signal and outputting a logic high only when the output of the AND product and the refresh enable signal are both logic low. Self-refresh mode controller of semiconductor device. 2. The control circuit according to claim 1, wherein the control unit sets the column address strobe reset signal and the row address strobe reset signal to a logic high when the output of the logic gate is active, and synchronizes to a clock signal when the output of the logic gate is inactive. And a plurality of flip-flops for inputting the refresh enable signal to sequentially generate the column address strobe reset signal and the row address strobe reset signal. The address strobe initialization signal generator of claim 1, wherein the address strobe initialization signal generator generates the address strobe initialization signal as a logic low when the row address strobe reset signal is a logic high, and generates the address strobe initialization signal when the row address strobe reset signal is a logic low. Self refresh mode controller for a DRAM semiconductor device, characterized in that it occurs as a logic high. The strobe signal generator of claim 1, wherein the strobe signal generator inputs the column address strobe reset signal, the row address strobe reset signal, the address strobe initialization signal, and control signals generated during normal operation, and the address strobe initialization signal is a logic low signal. In this case, the column address strobe signal and the column address strobe signal are initialized to logic high. If the column address strobe reset signal and the row address strobe reset signal are logic low, the column address strobe signal and the row address strobe signal are logic low. If the address strobe initialization signal, the column address strobe reset signal, and the row address strobe reset signal are both logic high, the clock is generated sequentially. And a plurality of flip-flops for generating the column address strobe signal and the row address strobe signal in synchronization with a signal to generate the column address strobe signal. The DRAM semiconductor device of claim 7, wherein the strobe signal generator further comprises flip-flops for generating an output enable signal and a write enable signal in response to the first reset signal or the control signals. Self refresh mode controller.