KR100250221B1 - Method for forming an aluminum schottky juction in p-type silicon board - Google Patents

Method for forming an aluminum schottky juction in p-type silicon board Download PDF

Info

Publication number
KR100250221B1
KR100250221B1 KR1019950042285A KR19950042285A KR100250221B1 KR 100250221 B1 KR100250221 B1 KR 100250221B1 KR 1019950042285 A KR1019950042285 A KR 1019950042285A KR 19950042285 A KR19950042285 A KR 19950042285A KR 100250221 B1 KR100250221 B1 KR 100250221B1
Authority
KR
South Korea
Prior art keywords
silicon substrate
type silicon
hydrogen peroxide
hydrochloric acid
aluminum
Prior art date
Application number
KR1019950042285A
Other languages
Korean (ko)
Other versions
KR970030559A (en
Inventor
류근걸
김홍락
이성호
서광
Original Assignee
이구택
포항종합제철주식회사
신현준
재단법인포항산업과학연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이구택, 포항종합제철주식회사, 신현준, 재단법인포항산업과학연구원 filed Critical 이구택
Priority to KR1019950042285A priority Critical patent/KR100250221B1/en
Publication of KR970030559A publication Critical patent/KR970030559A/en
Application granted granted Critical
Publication of KR100250221B1 publication Critical patent/KR100250221B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE: A preparing method of a Schottky junction on a P-type silicon plate is provided to prevent yield due to a high leakage current by increasing a Schottky barrier. CONSTITUTION: A natural oxide film on a P-type silicon plate(5) is removed by treating it with fluoric acid and ion-removed pure water. The surface of the silicon plate(5) is activated by treating with 1:3-1:4(volume ratio) mixture solution of dense hydrochloric acid and hydrogen peroxide. Then, a high-purity aluminum film is deposited on the silicon plate(5). The treatment of hydrochloric acid and hydrogen peroxide changes the surface nature of the P-type silicon plate(5) and a Schottky junction with improved electric barrier is formed.

Description

P-형 실리콘 기판 표면의 알루미늄 쇼트키접합 형성방법Method of forming aluminum schottky junction on P-type silicon substrate surface

제1도는 P-형 실리콘 기판 표면의 알루미늄 쇼트키(Schottky)접합을 설명하기 위한 TEM 관찰도로서,1 is a TEM observation diagram for explaining an aluminum Schottky junction of a P-type silicon substrate surface.

(a)도는 종래 방법에 의한 접합시 TEM 관찰도.(a) is a TEM observation at the time of joining by the conventional method.

(b)도는 본 발명의 방법에 의한 접합시 TEM 관찰도.(b) is a diagram of TEM observation at the time of bonding by the method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 고착제 2 : 고순도 알루미늄 전극1: fixing agent 2: high purity aluminum electrode

3 : 알루미늄/ P-형 실리콘 기판과의 합금층3: alloy layer with aluminum / P-type silicon substrate

4 : 계면 활성층 5 : P-형 실리콘 기판층4: surfactant layer 5: P-type silicon substrate layer

본 발명은 P-형 실리콘 기판 표면의 알루미늄 쇼트키(Schottky)접합 형성방법에 관한 것으로, 더욱 상세하게는 불산과 초순수 탈이온수로 기판 표면의 자연 산화막을 제거하고 염산과 과산화수소수의 혼합용액으로 기판 표면을 활성화시킨 후 고순도 알루미늄을 증착시키는 것으로 구성되는 것을 특징으로 하는 P-형 실리콘 기판 표면의 알루미늄 쇼트키 접합 형성방법에 관한 것이다.The present invention relates to a method of forming an aluminum Schottky junction on a surface of a P-type silicon substrate, and more particularly, to remove a natural oxide film on the surface of a substrate with hydrofluoric acid and ultrapure deionized water, and to prepare a substrate with a mixed solution of hydrochloric acid and hydrogen peroxide. A method of forming an aluminum Schottky junction on a surface of a P-type silicon substrate, comprising activating the surface and then depositing high purity aluminum.

반도체 소자의 전기적 특성 평가를 위해서 주로 사용되는 방향성 전류흐름을 가지는 쇼트키 장벽 다이오드의 제작을 위해서 P-형 실리콘 기판 표면에 쇼트키 접합을 형성하게 된다. 일반적으로 P-형 실리콘 기판 표면의 쇼트키 접합은 알루미늄이나 티타늄등을 진공스퍼터나 진공 열분해 증착기를 이용하여 증착시키는 것으로 형성한다. 종래, P-형 실리콘 기판 표면에 알루미늄 쇼트키 접합의 형성방법은, 먼저 자연산화막을 불산계통의 반도체용 화학약품을 사용하여 제거하고, 그 위에 수천Å의 고순도 알루미늄을 제1(a)도와 같이 증착시키는 것으로 구성되어 있다. 그러나, 순수 실리콘 표면과의 알루미늄 쇼트키 접합을 이룬 시편은 하기 표 1에서와 같이 역방향 인가전압에 따른 누설전류가 크기때문에 측정시편으로는 부적합하며, 측정에 사용하고자 하여도 인가되는 외부온도에 의해 측정시편의 온도가 올라갈 경우 급격히 누설전류가 증가하여 항복이 일어나는 단점을 가지고 있다.A Schottky junction is formed on the surface of a P-type silicon substrate to fabricate a Schottky barrier diode having a directional current flow, which is mainly used to evaluate electrical characteristics of semiconductor devices. In general, a Schottky junction on a surface of a P-type silicon substrate is formed by depositing aluminum or titanium using a vacuum sputter or a vacuum pyrolysis evaporator. Conventionally, in the method of forming an aluminum Schottky junction on the surface of a P-type silicon substrate, first, a natural oxide film is removed using a chemical agent for semiconductors of hydrofluoric acid, and thousands of Å of high purity aluminum is removed thereon as shown in FIG. It consists of depositing. However, the test specimen made of aluminum Schottky junction with the pure silicon surface is not suitable as the test specimen because the leakage current according to the reverse applied voltage is large as shown in Table 1 below. When the temperature of the test specimen rises, the leakage current rapidly increases, causing a breakdown.

따라서, 본 발명의 목적은, 상기 종래 기술의 단점을 극복하는 것으로, 염산과 과산화수소수의 혼합용액으로 실리콘 기판을 활성화시킴으로써 쇼트키 전위장벽을 증가시켜 -6V의 역인가 전압하에서도 10㎂ 이하의 누설전류를 갖는 쇼트키 접합을 형성하는 방법을 제공하는 것이다.Accordingly, an object of the present invention is to overcome the disadvantages of the prior art, by activating the silicon substrate with a mixed solution of hydrochloric acid and hydrogen peroxide solution to increase the Schottky potential barrier to 10 kΩ or less even under a reverse applied voltage of -6V. It is to provide a method of forming a Schottky junction having a leakage current.

본 발명의 P-형 실리콘 기판 표면의 알루미늄 쇼트키 접합 형성방법은 가)불산과 초순수 탈이온수로 실리콘 기판 표면의 자연산화막을 제거하는 단계; 나)진한 염산과 과산화수소수를 1-3:1-4의 부피비로 혼합한 혼합용액으로 실리콘 기판 표면을 활성화시키는 단계; 및 다) 고순도 알루미늄을 증착시키는 단계로 구성되는 것을 특징으로 한다.A method of forming an aluminum Schottky junction on a surface of a P-type silicon substrate of the present invention comprises the steps of: a) removing the native oxide film on the surface of the silicon substrate with hydrofluoric acid and ultrapure deionized water; B) activating the surface of the silicon substrate with a mixed solution of concentrated hydrochloric acid and hydrogen peroxide in a volume ratio of 1-3: 1-4; And c) depositing high purity aluminum.

자연산화막을 제거하는 데 사용되는 불산과 초순수 탈이온수는 일반적으로 1:10의 부피비로 사용되고, 상온에서 30초의 처리로 실리콘 기판 표면의 자연 산화막을 제거하게 된다.Hydrofluoric acid and ultrapure deionized water used to remove the natural oxide film are generally used in a volume ratio of 1:10, and the natural oxide film on the surface of the silicon substrate is removed by 30 seconds of treatment at room temperature.

실리콘 기판의 표면을 세정하고 활성화시키는데 사용되는 염산과 과산화수소수는 반도체용으로 사용되는 진한 염산용액과 과산화수소수를 사용하며 부피비로 1-3:1-4로 혼합하여 사용하되, 가장 바람직한 부피비는 1:2이다. 바람직한 활성화 온도는 90-l10℃이고, 가장 바람직한 활성화 온도는 100℃이며, P-형 실리콘 기판의 표면을 활성화시키는 데 필요한 처리시간은 3-15분으로, 가장 바람직한 처리시간은 10분이다.The hydrochloric acid and hydrogen peroxide solution used to clean and activate the surface of the silicon substrate are concentrated hydrochloric acid solution and hydrogen peroxide solution used for semiconductors, mixed 1-3: 1-4 by volume, but the most preferable volume ratio is 1 : 2. Preferred activation temperature is 90-10 [deg.] C., most preferred activation temperature is 100 [deg.] C., the treatment time required to activate the surface of the P-type silicon substrate is 3-15 minutes and the most preferred treatment time is 10 minutes.

이하 실시예에 의해 본 발명의 특징인 표면 활성화 단계의 수치 한정 이유를 보다 상세히 설명한다.The reason for limiting the numerical value of the surface activation step, which is a feature of the present invention, is explained in more detail by the following examples.

[실시예 1]Example 1

P-형 실리콘 기판의 표면을 불산과 초순수 탈이온수(부피비 1:10)로 30초간 처리하여 실리콘 기판 표면의 자연산화막을 제거하고, 시약급의 진한 염산과 과산화수소수의 부피비를 0-4:0-5로 변화시켜 가면서 염산과 과산화수소수의 혼합용액으로 100℃에서 10분간 처리하여 P-형 실리콘 기판의 표면을 활성화시킨 후, 알루미늄을 열분해 증착기를 이용하여 200Å 증착시킨 후, -6V의 역전압을 인가하여 누설전류를 관찰하였다. 결과를 하기 표 1에 기재하였다.The surface of the P-type silicon substrate was treated with hydrofluoric acid and ultrapure deionized water (volume ratio 1:10) for 30 seconds to remove the native oxide film on the surface of the silicon substrate, and the volume ratio of reagent grade concentrated hydrochloric acid and hydrogen peroxide solution was 0-4: 0. After changing to -5, the mixture of hydrochloric acid and hydrogen peroxide solution was treated at 100 ° C for 10 minutes to activate the surface of the P-type silicon substrate, and then aluminum was deposited at 200 kV using a pyrolysis evaporator, followed by a reverse voltage of -6V. Was applied to observe the leakage current. The results are shown in Table 1 below.

[표 1]TABLE 1

* 누설전류의 측정단위는 ㎂이다.* The measurement unit of leakage current is ㎂.

상기 표 1에서 알 수 있는 바와 같이 종래 기술의 불산과 초순수 탈이온수만을 사용하여 표면처리한 후 P-형 실리콘 기판의 표면에 알루미늄 쇼트키 접합을 형성한 경우 누설전류가 136㎂로 높아 측정시편의 항복이 일어나며, 자연산화막제거후 염산과 과산화수소수의 혼합용액으로 표면을 활성화시키는 경우 혼합비가 부피비로 1-3:1-4일 때 누설전류가 10㎂ 이하로 떨어졌으며, 가장 바람직한 혼합비는 부피비로 1:2였다. 이 때의 누설전류는 1.4㎂로 측정되었다.As can be seen from Table 1, when the aluminum Schottky junction was formed on the surface of the P-type silicon substrate after surface treatment using only hydrofluoric acid and ultrapure deionized water of the prior art, the leakage current was high at 136 의. Yield occurs and when the surface is activated with a mixed solution of hydrochloric acid and hydrogen peroxide after removal of the natural oxide film, the leakage current drops below 10 mA when the mixing ratio is 1-3: 1-4 in volume ratio, and the most preferable mixing ratio is volume ratio. 1: 2. The leakage current at this time was measured at 1.4 mA.

[실시예 2]Example 2

P-형 실리콘 기판의 표면을 불산과 초순수 탈이온수(부피비 1:10)로 30초간 처리하여 실리콘 기판 표면의 자연산화막을 제거하고, 시약급의 진한 염산과 과산화수소수를 부피비로 1:2로 혼합한 혼합용액으로 처리온도와 시간을 변화시켜가면서 처리하여 P-형 실리콘 기판의 표면을 활성화시킨 후, 알루미늄을 열분해 증착기를 이용하여 2000Å 증착시킨 후, -6V의 역전압을 인가하여 누설전류를 관찰하였다. 결과를 하기 표 2에 기재하였다.The surface of the P-type silicon substrate is treated with hydrofluoric acid and ultrapure deionized water (volume ratio 1:10) for 30 seconds to remove the native oxide film on the surface of the silicon substrate, and the reagent grade concentrated hydrochloric acid and hydrogen peroxide solution are mixed at a volume ratio of 1: 2. The mixture was treated with varying treatment temperature and time to activate the surface of the P-type silicon substrate, and aluminum was deposited at 2000 mA using a pyrolysis evaporator, and then a reverse voltage of -6V was applied to observe the leakage current. It was. The results are shown in Table 2 below.

[표 2]TABLE 2

* 누설전류의 측정단위는 ㎂이다.* The measurement unit of leakage current is ㎂.

상기 표 2에서 알 수 있는 바와 같이 처리온도 90-110℃ 사이에서 5-15분간 처리했을 때 가장 낮은 누설전류 값을 나타낸다. 처리온도가 80℃이하와 125℃ 이상일 때는 염산과 과산화수소수의 혼합용액의 활성화정도가 약해서 충분히 실리콘 표면을 활성화시킬 수 없으며, 처리시간이 5분 이하인 경우 염산과 과산화수소수의 초기 열적 활성화반응이 약하고, 15분 이상 처리시간이 소요되는 경우 염산과 과산화수소수의 화학반응이 충분히 일어난 후 반응이 끝난 상태에서 염산과 과산화수소수에 의한 실리콘 기판 표면의 활성화 반응보다 용액속에 용해되어 있던 오염물질에 의한 부반응 및 활성화층을 변형시키는 표면반응이 일어나 양질의 활성화층을 형성시키지 못하게 된다.As can be seen in Table 2, the lowest leakage current value is obtained when the treatment is performed for 5-15 minutes at a processing temperature of 90-110 ° C. When the treatment temperature is below 80 ℃ and above 125 ℃, the activation degree of the mixed solution of hydrochloric acid and hydrogen peroxide solution is weak enough to activate the silicon surface. If the treatment time is less than 5 minutes, the initial thermal activation reaction of hydrochloric acid and hydrogen peroxide solution is weak. In case the treatment time is over 15 minutes, after the chemical reaction between hydrochloric acid and hydrogen peroxide is enough, side reaction by contaminants dissolved in solution rather than activation reaction of silicon substrate surface by hydrochloric acid and hydrogen peroxide solution and Surface reactions that deform the activation layer occur, preventing the formation of a good quality activation layer.

[실시예 3]Example 3

P-형 실리콘 기판의 표면을 불산과 초순수 탈이온수(부피비 1:10)로 30초간 처리하여 실리콘 기판 표면의 자연산화막을 제거하고, 알루미늄 열분해 증착기를 이용하여 2000Å 증착시킨 후 TEM시편을 만들어 관찰하였다. 결과는 제1(a)도에 나타내었다.The surface of the P-type silicon substrate was treated with hydrofluoric acid and ultrapure deionized water (volume ratio 1:10) for 30 seconds to remove the native oxide film on the surface of the silicon substrate, and then deposited at 2000Å using an aluminum pyrolysis evaporator to make a TEM specimen. . The results are shown in Figure 1 (a).

P-형 실리콘 기판의 표면을 불산과 초순수 탈이온수(부피비 1:10)로 30초간 처리하여 실리콘 기판 표면의 자연산화막을 제거하고, 시약급의 진한 염산과 과산화수소수를 부피비로 1:2로 혼합한 염산과 과산화수소수의 혼합용액으로 100℃에서 10분간 처리하여 P-형 실리콘 기판의 표면을 활성화시킨 후, 알루미늄을 열분해 증착기를 이용하여 2000Å 증착시킨 후 TEM시편을 만들어 관찰하였다. 결과는 제1(b)도에 나타내었다.The surface of the P-type silicon substrate is treated with hydrofluoric acid and ultrapure deionized water (volume ratio 1:10) for 30 seconds to remove the native oxide film on the surface of the silicon substrate, and the reagent grade concentrated hydrochloric acid and hydrogen peroxide solution are mixed at a volume ratio of 1: 2. After activating the surface of the P-type silicon substrate by treating the mixture with hydrochloric acid and hydrogen peroxide solution for 10 minutes at 100 ° C., aluminum was deposited using a pyrolysis evaporator for 2000 Å and the TEM specimen was observed. The results are shown in Figure 1 (b).

도면에서 알 수 있는 바와 같이, (a)도의 종래 기술의 TEM결과와 달리 (b)도의 본 발명의 실시예의 TEM은 알루미늄/P-형 실리콘 기판의 합금과 함께 실리콘 기판쪽으로 얇은 산화막이 형성되어 있다. 이것은 염산-과산화수소수 처리로부터 P-형 실리콘 기판의 표면의 성질이 변화하여 이러한 계면 활성층을 이루어 전기적 장벽이 향상된 쇼트키 접합을 형성하였음을 나타내는 것이다.As can be seen in the figure, unlike the conventional TEM results of (a), the TEM of the embodiment of the present invention of (b) has a thin oxide film formed toward the silicon substrate together with the alloy of the aluminum / P-type silicon substrate. . This indicates that the properties of the surface of the P-type silicon substrate were changed from hydrochloric acid-hydrogen peroxide treatment to form such a surfactant layer to form a Schottky junction with improved electrical barrier.

염산-과산화수소수 처리로 P-형 실리콘 기판의 표면을 활성화시키는, 본 발명의 P-형 실리콘 기판 표면의 알루미늄 쇼트키 접합 형성방법에 의해 쇼트키 전위장벽을 증가시켜 -6V의 역인가 전압하에서도 10㎂ 이하의 누설전류를 발생시키게 된다. 따라서, 높은 누설전류에 의한 항복이 일어나는 등의 현상없이 쇼트키 장벽 다이오드 제작에 이용할 수 있다.The Schottky potential barrier is increased by the method of forming an aluminum Schottky junction on the surface of a P-type silicon substrate of the present invention, which is activated by hydrochloric acid-hydrogen peroxide treatment, even under a negative applied voltage of -6V. A leakage current of 10 mA or less is generated. Therefore, it can be used for the production of Schottky barrier diodes without the occurrence of breakdown due to high leakage current.

Claims (2)

가) 불산과 초순수 탈이온수로 처리하여 실리콘 기판 표면의 자연산화막을 제거하는 단계, 나) 진한 염산과 과산화수소수를 1-3:1-4의 부피비로 혼합한 혼합용액으로 처리하여 실리콘 기판 표면을 활성화시키는 단계; 및 다) 고순도 알루미늄을 증착시키는 단계로 구성되는 것을 특징으로 하는 P-형 실리콘 기판 표면의 알루미늄 쇼트키 접합 형성방법.A) removing the native oxide film on the surface of the silicon substrate by treating with hydrofluoric acid and ultrapure deionized water, b) treating the surface of the silicon substrate with a mixed solution of concentrated hydrochloric acid and hydrogen peroxide in a volume ratio of 1-3: 1-4. Activating; And c) depositing high purity aluminum. 제1항에 있어서, 상기 나) 진한 염산과 과산화수소수의 혼합용액으로 실리콘 기판의 표면을 처리하는 단계는 90-110℃의 온도에서 5-15분간 행해지는 것을 특징으로 하는 P-형 실리콘 기판 표면의 알루미늄 쇼트키 접합 형성 방법.The surface of the P-type silicon substrate according to claim 1, wherein b) treating the surface of the silicon substrate with a mixed solution of concentrated hydrochloric acid and hydrogen peroxide solution is performed at a temperature of 90-110 ° C for 5-15 minutes. Method of forming aluminum Schottky junction.
KR1019950042285A 1995-11-20 1995-11-20 Method for forming an aluminum schottky juction in p-type silicon board KR100250221B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950042285A KR100250221B1 (en) 1995-11-20 1995-11-20 Method for forming an aluminum schottky juction in p-type silicon board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950042285A KR100250221B1 (en) 1995-11-20 1995-11-20 Method for forming an aluminum schottky juction in p-type silicon board

Publications (2)

Publication Number Publication Date
KR970030559A KR970030559A (en) 1997-06-26
KR100250221B1 true KR100250221B1 (en) 2000-06-01

Family

ID=19434733

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950042285A KR100250221B1 (en) 1995-11-20 1995-11-20 Method for forming an aluminum schottky juction in p-type silicon board

Country Status (1)

Country Link
KR (1) KR100250221B1 (en)

Also Published As

Publication number Publication date
KR970030559A (en) 1997-06-26

Similar Documents

Publication Publication Date Title
Kern The evolution of silicon wafer cleaning technology
EP2629319B1 (en) Process for cleaning compound semiconductor wafer
US5883060A (en) Cleaning compositions for wafers used in semiconductor devices
JP2006352075A (en) Cleaning method and manufacturing method for nitride compound semiconductor, and compound semiconductor, and board
DE102017112644A1 (en) PLASMA SHARPENING OF SILICON CARBIDE
KR100250221B1 (en) Method for forming an aluminum schottky juction in p-type silicon board
US5919715A (en) Method for cleaning a semiconductor surface
KR20200102617A (en) Method of surface treatment of gallium oxide
Jastrzebski et al. The Effect of Heavy Metal Contamination on Defects in CCD Imagers: Contamination Monitoring by Surface Photovoltage
US4597825A (en) Intermediate passivation and cleaning of compound semiconductor surfaces
JPH11274143A (en) Dry etching method and manufacture of thin film transistor
EP0108910B1 (en) Method of forming a passivated compound semiconductor substrate
US5094964A (en) Method for manufacturing a bipolar semiconductor device
EP4194592A1 (en) Semiconductor laminate, semiconductor element, and method for producing semiconductor element
US11798807B2 (en) Process for producing an electrical contact on a silicon carbide substrate
Muthuvel et al. Surface chemistry of InP (100) after wet and electrochemical etching: Is digital etching possible?
JPH0837173A (en) Forming apparatus
KR20160114544A (en) Method for reducing the metal contamination on a surface of a substrate
DE10111761A1 (en) Arrangement and method for contacting a semiconductor substrate from the rear
KR100417646B1 (en) Method for cleaning interlayer dielectric of semiconductor device
JPH07165499A (en) Gaas single crystal wafer and its production and method for sorting the same
JPS5897826A (en) Semiconductor manufacturing device and washing method therefor
JPH07174677A (en) Method for manufacturing sample for observation by transmission electronic microscope
WO2006085670A1 (en) Electrode and compound semiconductor element
Chuah et al. Nanoporous InN Films Synthesized using Photoelectrochemical (PEC) Wet Etching

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021220

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee