KR100247279B1 - Lcd panel and its fabrication method - Google Patents

Abstract

The present invention relates to a method for manufacturing a liquid crystal display panel. The pixel structure is newly designed to simultaneously etch a field silicon nitride (A-Si) to etch a field, thereby reducing a mask field and simplifying a process. , Cost reduction, etc., and also reduces parasitic capacitance, which reduces cross-talk phenomenon and improves aperture ratio by forming desired storage capacitor with small area. A liquid crystal display panel can be manufactured.

Description

Liquid display panel and manufacturing method

1 is a plan view showing a unit pixel of a liquid crystal panel according to a manufacturing method of the present invention,

Figure 1a is a cross-sectional view taken along the line A-A of Figure 1,

2 is a cross-sectional view showing the TFT portion and the storage capacitor portion of FIG.

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly, to a high definition liquid crystal display panel having a switching element composed of a thin film transistor and a method of manufacturing the same.

[Prior Art and Problem]

Recently, with the spread of OA devices and portable small TVs, liquid crystal displays (LCD), electro-luminescence sensor (EL) devices, plasma displays (PDP), fluorescent display tubes (VFD) instead of CRTs have been used as electronic display devices. Research is being actively promoted, and some have been put into practical use.

Among them, the liquid crystal display device is extremely lightweight, thin, inexpensive, and low power consumption, so that it can be easily matched with an integrated circuit. The color for loading a vehicle in addition to the display of a laptop computer or a pocket computer is shown. Its use is rapidly expanding for TV images.

Such a color LCD has been spotlighted as a promising child of a flat panel device as an interface of human-machine according to the development of civilization.

Currently, this technology is the most powerful display device comparable to the CRT, and it was mass-produced in the second half of 1991. The technology is an active matrix LCD technology that combines semiconductor technology and liquid crystal technology. It consists of a TFT panel of a lower board, and consists of the liquid crystal which has dielectric anisotropy in between.

The active matrix LCD adds a thin film transistor (TFT) as a switching element to each of hundreds of thousands of pixels arranged in a matrix form, which are integrated on a glass substrate together with a pixel selection address wiring to form a matrix circuit. In addition, an active matrix type liquid crystal display device using a thin film transistor using amorphous silicon or polycrystalline silicon as a switching element is widely used as a liquid crystal display device.

In particular, an array of thin film transistors using the amorphous silicon on the transparent glass substrate because the amorphous silicon has good coherence with a large-area transparent glass substrate and has no particular difficulty in large screen correspondence, reproducibility, low temperature deposition, and film quality. Forming a can realize a cheap display panel having high quality and high definition of a large screen.

First, a conventional liquid crystal display panel forming method will be described.

First, pads are formed on the transparent glass substrate using chromium (Cr), and then Al, Ta / Al, Mo-Ta, α-Ta, and the like are used for gate electrodes, gate bus lines, and storage capacitors. Pattern the metal.

Anodization is then performed, and three layers are deposited after the anodization. That is, first, a gate insulating layer of SiNx is formed on the patterned metal to form a gate insulating layer of aluminum oxide / silicon nitride (Al ₂ O ₃ / SiNx). Then, silicon nitride, which is an amorphous silicon (a-Si) and an etch-stopper, which is not implanted with impurities, is deposited, and then the etch-stopper is patterned.

Subsequently, n ⁺ -type amorphous silicon (n ⁺ a-Si) is formed on the patterned etch stopper, followed by an a-Si island pattern. Then, a transparent electrode for each pixel, that is, a pixel electrode, is formed of an ITO (Indum Thin Oxide) film.

In order to continuously form the source electrode and the drain electrode in the resultant structure of the process, a chromium / aluminum (Cr / Al) film is laminated and patterned, and then the stacked n ⁺ type amorphous silicon is etched.

In this case, the source electrode is integrally formed with the data line, and the drain electrode is connected to the pixel electrode and spaced apart from the source electrode.

The final process is then completed with a passivation layer to protect the resulting structure. In the conventional TFT panel fabrication, since the gate insulating layer is used as a storage capacitor, a subcutaneous silicon nitride and a selective etching must be etched when forming an amorphous silicon island. Not only is the selective etching difficult, but also because the silicon nitride layer is used as the dielectric layer of the storage capacitor, the capacitance of the storage capacitor changes according to the degree of etching, which is an unstable factor of display characteristics.

In addition, as the resolution becomes higher, it is difficult to secure the aperture ratio, and as the pixel pitch becomes smaller, the cross-talk phenomenon due to the parasitic capacitance of the pixel electrode ITO and the data line is intensifying. .

In addition, the silicon nitride must be etched to open the gate insulator on the pad, which requires one more mask, resulting in higher defect rates and higher manufacturing costs.

In addition, ITO etchant (Etchant) seeps into the gate bus line when the ITO etching of the pixel electrode, the gate bus line is open.

[Purpose of invention]

Accordingly, the present invention has been made in view of the above, and in manufacturing a liquid crystal display panel having a thin film transistor, it is necessary to design and form a pixel structure so as to achieve high definition and high yield. It is an object of the present invention to provide a liquid crystal display panel and a method for manufacturing the same, which exhibits stable display characteristics while eliminating the problem.

[Configuration of Invention]

In order to achieve the above object, a liquid crystal display panel according to the present invention includes a plurality of gate bus lines made of aluminum on a substrate, a first anode oxide film formed by anodizing part of the gate bus lines, and the gate lines intersecting with each other. A plurality of data lines arranged at an intersection of the plurality of data lines and the plurality of gate bus lines and the plurality of data lines, a gate electrode made of tantalum is connected to each of the gate bus lines, and a source electrode is connected to each of the data lines. A plurality of connected thin film transistors, an accumulation capacitor made of tantalum and connected to a gate electrode of the adjacent thin film transistor, a second anode oxide film formed by anodizing a portion of the accumulation capacitor, and connected to a drain electrode of each thin film transistor. Part of which is superimposed on the second anode oxide layer Each thin film transistor includes a plurality of pixel electrodes formed on the gate electrode, a third anode oxide film formed by partially anodizing the gate electrode, a gate insulating layer formed on the anode oxide film, and a gate insulating layer. The formed semiconductor layer, an etch stopper layer formed on the channel forming portion of the semiconductor layer, an n ⁺ -type amorphous silicon layer formed on the semiconductor layer other than the etch stopper layer, and the left and right sides of the n ⁺ -type amorphous silicon layer. A source and drain electrode are formed, and the gate insulating layer, the semiconductor layer, the etch stopper layer and the n ⁺ -type amorphous silicon layer are formed on the plurality of gate bus lines and under the plurality of data lines.

Forming a gate electrode / accumulating capacitor on a substrate to a predetermined thickness; Forming a gate bus line connected to the gate electrode / accumulation capacitor to a predetermined thickness after the process; Depositing a gate insulating layer, an amorphous silicon layer, and an etch stopper layer on the substrate on which the gate electrode / accumulation capacitor and the gate bus line are formed, and sequentially depositing the gate insulating layer, the amorphous silicon layer, and the etch stopper layer to a predetermined thickness; After patterning the etch stopper, depositing an n ⁺ type amorphous silicon layer to a predetermined thickness; Next, forming an amorphous silicon island and etching the gate insulating layer to form a pattern on the gate electrode line and the portion where the data line is to be formed, and forming a pixel electrode on the pixel portion including the storage capacitor; Forming a source / drain and a data line on the n ⁺ type amorphous silicon layer; Thereafter, after etching the n ⁺ -type amorphous silicon layer, a protective film is coated.

[Action of invention]

According to the present invention, the pixel structure is newly designed and the field silicon nitride etching is performed at the same time during the amorphous silicon etching, so that one mask can be reduced, the process is simplified, and the parasitic capacitance is reduced. In addition, the aperture ratio can be improved by forming a desired storage capacitor with a small area.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a plan view showing a unit pixel of a liquid crystal panel according to the manufacturing method of the present invention, Figure 1a is a cross-sectional view showing the line AA line of Figure 1, Figure 2 is a cross-sectional view showing the TFT portion and the storage capacitor portion of FIG. It is shown.

As shown in FIGS. 1 and 2, a method of manufacturing a liquid crystal display panel according to an exemplary embodiment of the present invention may include a pad and a gate / storage capacitor 11 on a glass substrate 21. Is formed to a thickness of 2500 kPa using tantalum (Ta).

After that, the gate bus line 12 is made of aluminum (Al) to a thickness of 4000Å.

At this time, the portion where the gate bus line 12 and the gate / accumulation capacitor 11 intersect is not a problem since tantalum Ta can taper etching.

Thereafter, anodization film 23 is formed on the substrate on which the pad, the gate / accumulation capacitor 11, and the gate bus line 12 are formed to form an anodization film 23, and the gate insulating layer 24 and the semiconductor layer 25 are formed. And the etch stopper layer 26 are sequentially deposited on the entire surface of the panel at a predetermined thickness.

The gate insulating layer 24, the semiconductor layer 25, and the etch stopper layer 26 may be formed of silicon nitride, amorphous silicon, or silicon nitride (SiNx, a-Si, SiNx), each about 2000 μs, It is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) at a thickness of 1000 kPa and 2000 kPa.

After that, the etch stopper layer 14 is patterned, and then n ⁺ type amorphous silicon (n ⁺ a-Si) is deposited to a thickness of 500 kW to form an ohmic contact layer. Next, when forming the amorphous silicon (a-Si) island 13, the gate insulator 24, which is a subcutaneous film, is also etched at the same time.

Thereafter, the pixel electrodes 15 and 27 are formed to a thickness of 500 mV using ITO, and the source / drain electrodes 29 and 30 made of Cr / Al and the data line 16 are formed. ). In other words, it can be seen that the data line 16 has a structure formed on the gate insulating layer 24, the semiconductor layer 25 and the etch stopper layer 26 of the TFT formed previously.

Since the thickness of the amorphous silicon island is 3000 Å, step coverage is not a problem.

Next, after the n ⁺ -type amorphous silicon is etched, a silicon nitride serving as a passivation layer 31 is applied to a thickness of 4000 kPa to complete the manufacture of the TFT panel.

In this structure, the pad and the gate / accumulation capacitor 11 are formed of tantalum. The tantalum is tapered by using RIE equipment using SFe + O ₂ mixed gas (taper angle up to 18 °). Even if ITO, which is the electrode 27, is thinned to 500 mW, there is no problem in the step coverage of the accumulation capacitor portion.

In addition, since the amorphous island 13 is formed along the data line 16 as shown in FIG. 1, the step coverage at the point where the gate bus line 12 and the data line 16 cross each other is good. In addition, as shown in FIG. 1A, which is a cross-sectional view along line AA of FIG. 1, the distance between the data line 16 and the pixel electrodes 15 and 27 is reduced, thereby reducing parasitic capacitance between them. Cross-talk phenomenon can be reduced.

The pixel structure of the present invention is also formed along the gate busline 12 when forming the amorphous silicon island 13 so that the ITO etchant penetrates into the gate busline 12 when the pixel ITO is etched. It is possible to exclude the failure that 12) is disconnected.

Since the accumulator capacitor is tantalum, it does not dissolve in the ITO etchant (even if the amorphous silicon island is not covered) and can be protected.

When forming amorphous islands, silicon nitride, which is a subcutaneous film, is also etched at the same time so that the etching can be performed by increasing the power density without considering the selectivity. By doing this, a fine pattern is possible.

In addition, since the dielectric layer of the accumulation capacitor is formed of TaOx, a large capacitance can be made with a small area, so that the area occupied by the accumulation capacitor in the pixel is relatively small, thereby improving the aperture ratio.

[Effects of the Invention]

As described above, according to the present invention, by designing a new pixel structure by simultaneously etching the field silicon nitride (SiNx) during the amorphous silicon (a-Si) etching,

i) Reduce the cost of one mask for pad open

ii) When etching amorphous silicon, it can be etched without considering the selectivity with the silicon nitride, which is a subcutaneous film, thereby improving the yield due to stabilization of the process,

iii) Cross-talk phenomenon is reduced by reducing the parasitic capacitance between the data line and the pixel electrode,

iv) Covering the amorphous silicon islands along the gate bus line to prevent disconnection of the gate bus line due to post-processing,

v) By using only the TaOx dielectric layer in the storage capacitor, a large storage capacitor can be formed with a small area, thereby improving the aperture ratio.

Claims (17)

A plurality of gate bus lines made of aluminum on the substrate, a first anode oxide film formed by anodizing a portion of the gate bus lines, a plurality of data lines arranged to intersect the gate lines, and the plurality of gate bus lines A plurality of thin film transistors disposed at respective intersections between the plurality of data lines, a gate electrode made of tantalum, connected to the respective gate bus lines, and a source electrode connected to each of the data lines, and a gate electrode of the adjacent thin film transistors. A storage capacitor formed of tantalum, a second anode oxide film formed by a portion of the storage capacitor being anodized, and a plurality of pixels connected to a drain electrode of each of the thin film transistors and partially stacked on the second anode oxide film. It consists of an electrode, each thin film transistor And a third anode oxide film formed by anodizing the gate electrode, a portion of the gate electrode, a gate insulating layer formed on the anodization film, a semiconductor layer formed on the gate insulating layer, and a channel forming portion of the semiconductor layer. An etch stopper layer formed, an n ⁺ type amorphous silicon layer formed on the semiconductor layer other than the etch stepper layer, and the source and drain electrodes formed on the left and right sides of the n ⁺ type amorphous silicon layer; And a gate insulating layer, a semiconductor layer, an etch stopper layer and an n ⁺ -type amorphous silicon layer formed on a line and under a plurality of data lines. The method of claim 1, And wherein the semiconductor layer is made of amorphous silicon, and the amorphous silicon island formed on the gate bus line has selective etching with the gate bus line. The method of claim 1, And a gate electrode / capacitor formed at a portion crossing the gate bus line has a tapered structure. The method of claim 1, The gate insulating layer, the semiconductor layer and the etch stopper layer is formed of SiNx, a-Si, SiNx. Forming a gate electrode / accumulating capacitor on a substrate to a predetermined thickness; Forming a gate bus line connected to the gate electrode / accumulation capacitor to a predetermined thickness after the process; Depositing a gate insulating layer, an amorphous silicon layer, and an etch stopper layer on the substrate on which the gate electrode / accumulation capacitor and the gate bus line are formed, and sequentially depositing the gate insulating layer, the amorphous silicon layer, and the etch stopper layer to a predetermined thickness; After patterning the etch stopper, depositing an n ⁺ type amorphous silicon layer to a predetermined thickness; Next, forming an amorphous silicon island and simultaneously etching the gate insulating layer to form a pattern on the gate electrode line and the portion where the data line is to be formed, and forming a pixel electrode on the pixel portion including the storage capacitor; Forming a source / drain and a data line on the n ⁺ type amorphous silicon layer; And then applying a protective film after etching the n ⁺ type amorphous silicon layer. The method of claim 5, And the gate electrode / capacitor is formed of tantalum and has a thickness of 2500 kPa. The method of claim 5, And the gate bus line is made of aluminum, and the aluminum has a thickness of 4000 kPa. The method of claim 5, The tantalum is tapered etched by the SF ₆ + O ₂ mixed gas in the portion where the gate bus line and the gate electrode / accumulation capacitor cross each other, and the taper angle used during the taper etching is up to 18 °. Manufacturing method. The method of claim 5, And the gate insulating layer, the amorphous silicon layer, and the etch stopper layer are formed by PECVD, and the thicknesses of the gate insulating layer, the amorphous silicon layer, and the etch stopper layer are 2000 mW, 1000 mW and 2000 mW. The method of claim 5, And the pixel electrode is formed of ITO having a thickness of 500 mW. The method of claim 5, And the island of amorphous silicon is formed to have a thickness of 3000 kPa. The method of claim 5, And a dielectric layer of the storage capacitor is formed of TaOx. A gate bus line formed on the transparent substrate, A data line formed on the substrate and crossing the gate bus line; A gate electrode connected to the gate bus line, a source electrode connected to the data line, a drain electrode isolated from the source electrode, and a first amorphous silicon pattern connected to the source electrode and the drain electrode, respectively; Including thin film transistor, A pixel electrode connected to an electrode of the drain electrode In the liquid crystal display device comprising: And a gate insulating layer, a second amorphous silicon pattern, and a first doped amorphous silicon layer are sequentially formed between the gate bus line and the data line. In claim 13, And an anodization film formed between the gate bus line and the gate insulating film. In claim 13, And the first amorphous silicon pattern and the second amorphous silicon pattern are formed of the same layer. In claim 13, And further comprising a second doped amorphous silicon pattern and a third doped amorphous silicon pattern formed between the first amorphous silicon pattern, the source electrode, and the drain electrode, respectively. And the doped amorphous silicon pattern is formed of the same layer. The method of claim 16, And an etch stopper layer formed between the source electrode and the drain electrode on the first amorphous silicon pattern.