KR100243754B1 - Parameter changing apparatus of convolution interlever - Google Patents

Abstract

According to the present invention, a memory for storing and retrieving input data according to a predetermined row / column selection address and a clock inputted from an external device are counted to improve data rate and expandability by efficiently controlling the memory. A counter for generating an address for selection, a clock switching unit for switching and outputting an input clock according to the column selection signal generated by the counter, and a factor for interleaving depth according to the clock output from the clock switching unit A factor generation unit including a plurality of factor generators, and an address for selecting one of factors output from the plurality of factor generators in the factor generator according to the column selection signal output from the counter and outputting the selected row as the row selection address signal of the memory Par of Convolution Interleaver with Selection It provides a meter change device.

Description

Parameter Changer of Convolutional Interleaver

The present invention relates to a parameter changing technique of a convolution interleaver, and more particularly, to an apparatus for changing a parameter of a convolution interleaver to improve data rate and scalability.

In general, a conventional interleaver generates an address using a digital signal processor (DSP) or a microprocessor, and writes or reads data into memory according to the address.

Such a conventional interleaver is as shown in FIG.

As shown, it is composed of a microprocessor 1 which writes input data to a memory 2 such as an SRAM or generates an address for reading and outputting the data recorded in the memory 2. .

The operation of the conventional interleaver configured as described above is as follows.

First, when M bits of data are input as input data, the microprocessor 1 designates an address for sequentially writing the input data in the memory 2 in the vertical direction.

When the address is designated in this way, the memory 2 sequentially writes the input data in the vertical direction according to the designated address.

Here, M in the figure represents the bit width of the input data, and N is the address width of the memory 2 for configuring the interleaver.

On the other hand, in order to read the data recorded in the memory 2, the microprocessor 1 designates an address as described above, and the memory 2 draws out the data by the designated address.

At this time, since a method of calculating an address in the memory 2 is complicated, several clocks are consumed to calculate one address.

2 is a configuration of a delay memory in the memory 2 as an example of convolutional interleaving when writing or reading data according to an address as described above.

Here, K is a factor for adjusting the depth of interleaving.

However, such a conventional interleaver requires a large number of clocks to calculate an address when the address is calculated using a microprocessor or a digital signal processor in a high data rate device. There was a problem.

Accordingly, an object of the present invention is to provide a convolution interleaver parameter changing device capable of efficiently accessing memory and data to increase data rate and scalability in order to solve the problems of the prior art.

The apparatus of the present invention for achieving the object of the present invention comprises a memory for storing and retrieving input data according to a predetermined row, column selection address; A counter for counting a clock input from an outside to generate an address for selecting a column of the memory; A clock switching unit for switching and outputting an input clock according to the column selection signal generated by the counter; A factor generator comprising a plurality of factor generators for generating a factor for an interleaving depth according to a clock output from the clock switching unit; And an address selector configured to select one of factors output from a plurality of factor generators in the factor generator according to the column select signal output from the counter and output the selected row as a row select address signal of the memory.

1 is a block diagram showing the configuration of a convolutional interleaver according to the prior art,

FIG. 2 is a diagram showing the configuration of a delay memory in the memory of FIG.

3 is a diagram illustrating a parameter changing apparatus of a convolutional interleaver according to the present invention,

4 is a diagram showing the detailed configuration of the address adjusting section of FIG.

<Explanation of symbols for main parts of drawing>

10: programmable gate array portion 11: address generator

11a: counter 11b: clock switching unit

11c: factor generator 11d: address selector

20: Memory

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a diagram illustrating a configuration of an apparatus for changing a parameter of a convolutional interleaver according to the present invention.

A programmable gate array unit 10 including an address generator 11 for generating an address to perform a read operation on the rising edge of the input clock and a write operation on the rising edge of the inverted input clock as shown, RAM is configured to store and retrieve input data according to the address generated by the programmable gate array unit 10.

In this case, the address generator 11 counts an input clock to generate an address for selecting a column of a RAM, and switches an input clock according to a column selection signal generated by the counter 11a. A factor generator consisting of a clock switching unit 11b for outputting and a plurality of factor generators 11c-1 to 11c-n for generating a factor for interleaving depth according to a clock output from the clock switching unit 11b ( 11c) and one of the factors output from the plurality of factor generators in the factor generator 11c according to the column selection signal output from the counter 11a to output to the address for selecting the row of the RAM. It consists of the address selection part 11d.

The operation and effects of the parameter change device of the convolutional interleaver according to the present invention configured as described above are as follows.

First, when the input data M is applied to the programmable gate array unit 10, the programmable gate array unit 10 generates an address for writing data to the RAM 20 through the internal address generator 11. .

That is, the address generator 11 counts the rising edge to the falling edge of the input clock CLK with the counter, and outputs the count value as the column selection signal of the RAM 20.

The counting size here is determined by the parameters K and M.

The clock switching unit 11b switches the input clock to the factor generator 11c based on the output count value.

The factor generator 11c generates factors for respective interleaving depths using the internal factor generators 11c-1, 11c-2, ..., 11c-n according to the input clock, and applies them to the address selector 11d. The address selector 11d uses the count value output from the counter 11a as a selection signal to select one of a plurality of factors to be applied to select a row of the RAM 20. The RAM 20 is applied to the address.

Then, the RAM 20 stores the input data M according to the applied column and row selection signals, and in order to retrieve the stored data again, the clock in which the address generator 11 phase-inverts the input clock The stored data is retrieved by counting at the rising edge of to generate the column and row addresses of the RAM 20.

By doing so, the addressing of the RAM 20 is determined at the rising edge of every clock, so that addressing is performed within one clock.

On the other hand, only one counter needs to be added to increase the interleaving depth.

In other words, the column counter can be used as it is, and simply adding a counter for designating the row of the added column enables simple interleaving depth increase.

Therefore, in the present invention, by accessing data after designating an address at a high clock speed using an interleaving address, there is an effect applicable to the configuration of the interleaver of high-speed data, and the scalability to accommodate the change of the configuration of the interleaver is changed. Excellent effect

Claims (1)

A memory for storing and retrieving input data according to predetermined row and column selection addresses; A counter for counting a clock input from an outside to generate an address for selecting a column of the memory; A clock switching unit for switching and outputting an input clock according to the column selection signal generated by the counter; A factor generator comprising a plurality of factor generators for generating a factor for an interleaving depth according to a clock output from the clock switching unit; And an address selector configured to select one of the factors output from the plurality of factor generators in the factor generator and output the selected row signal as a row select address signal of the memory according to the column select signal outputted from the counter. Parameter change device.