KR100243293B1 - Method for fabricating transistor having high ruggedness - Google Patents

Abstract

A method of manufacturing a high breakdown voltage transistor of the present invention includes forming a rectangular active region defined by a device isolation region on a semiconductor substrate, and forming a gate electrode on the semiconductor substrate through a gate insulating film, wherein the gate electrode and the active region are formed. Forming an impurity implantation region for device isolation using an ion implantation mask using a mask pattern having openings formed to completely expose portions other than the region where the active region and the gate electrode overlap each other; And forming a source region and a drain region respectively on both sides of the gate electrode in the active region, and forming a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively.

Description

Method for fabricating a high breakdown transistor {Method for fabricating transistor having high ruggedness}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high breakdown voltage transistor.

Noah was developed for high-speed operation, unlike the large-capacity NAND-type flash memory that replaces magnetic disks to perform write and erase operations using Fowler-Nordheim tunneling. The (NOR) type flash memory performs a program operation using a channel hot electron injectiojn method and an erase operation through bulk or source using a Fowler-Nordheim tunneling method.

In addition, while NAND flash memory requires a voltage of about 20V to perform a program operation or an erase operation, a NOR flash memory has about 14 to 15V to perform a program and erase operation. It requires an internal and external voltage.

1A to 1C show a conventional high breakdown voltage transistor having a double doped drain (DDD) structure.

Here, reference numerals 100, 101, 103, and 105 denote semiconductor substrates, field oxide films, active regions, and gate electrodes, respectively, and reference numerals 107, 109, and 111 denote high concentration P-type impurities (hereinafter referred to as P + ions), respectively. The region, the low concentration N-type impurity (hereinafter referred to as N-ion) implantation region, and the high concentration of N-type impurity (hereinafter referred to as N + ion) implantation region are shown.

FIG. 1A is a plan view illustrating a state in which the gate electrode 105 is formed on the active region 103.

FIG. 1B is a longitudinal cross-sectional view of the high breakdown voltage transistor shown in FIG. 1A taken along the X-X 'direction. In this case, P + ions for device isolation are implanted into the lower portion of the field oxide film 101 and then diffused into the active region 103. Therefore, the P + ion implantation region 107 is formed not only under the field oxide film 101 but also under the gate electrode 105.

However, in the subsequent N-type impurity implantation process, since the N-type impurity is not implanted in the lower portion of the gate electrode 105, the P + ions introduced into the lower portion of the gate electrode 105 remain after the transistor fabrication process is completed. do.

FIG. 1C is a cross-sectional view of the transistor shown in FIG. 1A taken along the Y-Y 'direction. The active region 103 has a shallow N + ion implantation region 107 and a deep N-ion implantation region 109 for forming a source / drain.

A transistor of this structure has the advantage of having a high breakdown voltage due to the N-ion implantation region 109 present between the N + ion implantation region 111 and the semiconductor substrate, as shown in FIG. 1C, while as shown in FIG. 1B. The gate isolation breakdown voltage (GIBV) is low due to the P + ion implantation region 107 for device isolation under the gate electrode 105.

2A-2C show another conventional high voltage withstand transistor employing a modified lightly doped drain (MLDD) structure.

Here, reference numerals 200, 201, 203, and 205 denote semiconductor substrates, field oxide films, active regions and gate electrodes, respectively, and reference numerals 207, 209, and 211 denote P + ion implantation regions, N-ion implantation regions, and N + ion implantation, respectively. Represents an area.

2A is a plan view illustrating a state in which the gate electrode 205 is formed on the active region 203.

FIG. 2B is a longitudinal cross-sectional view of the transistor illustrated in FIG. 2A taken along the line X-X '. As in FIG. 1B, the P + ions for device isolation are implanted into the lower portion of the field oxide film 201 and then diffused into the lower portion of the gate electrode 205.

FIG. 2C is a cross-sectional view of the transistor shown in FIG. 2A taken along the Y-Y 'direction. In this case, since the transistor has an MLDD structure, the N + ion implantation region 211 is formed to be spaced apart from the field oxide film 201 and the gate electrode 205 by a predetermined distance.

In this structure, as shown in FIG. 2C, the N-ion implantation region 209 separates the P + ion implantation region 207 and the N + ion implantation region 211 by a suitable distance to increase the breakdown voltage and channel length. There is an advantage to reduce.

However, the N-ion implanted region 209 is difficult to be accurately formed between the N + ion implanted region 211 and the gate electrode 205 due to the misalignment of the mask in the actual manufacturing process. Therefore, a difference in sheet resistance occurs on the active region 203, and thus, a drain current is changed.

3A-3D show another conventional high withstand voltage transistor, illustrating an NMOS transistor with a modified-field oxide junction structure. Here, reference numerals 300, 301, 303 and 305 denote a semiconductor substrate, a field oxide film, an active region and a gate electrode, respectively. Further, reference numerals 307, 309 and 311 show a mask pattern for device isolation, a P + ion implantation region for device isolation, and an N + ion implantation region for source / drain formation, respectively.

3A is a plan view illustrating a state in which the gate electrode 305 is formed on the active region 303. In this case, the mask pattern 307 is used in a P + ion implantation process for device isolation, and is formed to have an area enough to mask the entire active region 303.

FIG. 3B is a longitudinal cross-sectional view of the NMOS transistor shown in FIG. 3A taken along the line X-X '. Since the device isolation mask pattern 307 masks the entirety of the active region 303, the P + ion implantation region 309 is formed only under the field oxide layer 301, and under the gate electrode 305. Is not formed.

3C is a cross-sectional view of the transistor illustrated in FIG. 3A taken along the line Y-Y '. As in FIG. 3B, the P + ion implantation region 309 is formed only below the field oxide layer 301 and is not formed below the active region 303.

FIG. 3D shows the layout of the NMOS transistor shown in FIG. 3A. Here, reference numeral L1 denotes the separation distance between the active regions 303, that is, the length of the device isolation region, and reference numeral L2 denotes the separation distance between the device isolation mask patterns 307.

In order to use the mask pattern 307, the length L1 of the isolation region must be greater than or equal to a predetermined value. That is, since the mask pattern 307 is larger than the area of the active region 203, the length L1 of the device isolation region is greater than the minimum design rule in order to secure the separation distance L2 between the mask patterns 307. It must be large.

As shown in FIG. 3C, the transistor having such a structure is formed only under the field oxide layer 301 while the P + ion implantation region 309 for device isolation is spaced apart from the N + ion implantation region 311. 309 and the breakdown voltage may be adjusted according to the separation distance between the N + ion implantation regions 311.

On the other hand, as shown in FIG. 3D, the mask pattern 307 having a large area masking the entire active region 303 must be used in the P + ion implantation process for device isolation, so that the length L1 of the device isolation region is increased. There are disadvantages.

The technical problem of the present invention is to provide a method of manufacturing a high breakdown voltage transistor having a reduced length of the device isolation region.

1A-1C show a conventional transistor with a DDD structure.

2A-2C show another conventional transistor with an MLDD structure.

3A-3D show another conventional transistor in which the modified field oxide junction structure is employed.

4A-4C show the sites vulnerable to high voltages in the conventional transistors shown in FIGS. 1A-1C.

5 shows high breakdown voltage characteristics for various types of transistors.

6A to 6B show transistors in which element isolation impurities are formed under the field oxide film and the gate electrode, and the DDD structure is not employed.

7A to 7B show transistors in which element isolation impurities are formed only under the field oxide film, and the DDD structure is not employed.

8A to 8B show transistors in which element isolation impurities are formed only under the field oxide film, and employ a DDD structure.

9A to 9E are views illustrating a method of manufacturing a high breakdown voltage transistor according to an exemplary embodiment of the present invention.

10A to 10B are views illustrating a method of manufacturing a high breakdown voltage transistor according to another exemplary embodiment of the present invention.

In order to achieve the technical problem of the present invention, a method of manufacturing a high breakdown voltage transistor according to the present invention, (A) forming a rectangular active region in the semiconductor substrate defined by the device isolation region; (B) forming a gate electrode on the semiconductor substrate with a gate insulating layer interposed therebetween so that the gate electrode and the active region intersect at a predetermined portion; (C) forming an impurity implantation region for device isolation using a mask pattern having an opening formed to completely expose portions except for the region where the active region and the gate electrode overlap, as an ion implantation mask; (D) forming source and drain regions on both sides of the gate electrode in the active region, respectively; And (e) forming a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively.

According to the manufacturing method of the high breakdown voltage transistor according to the present invention, the length of the device isolation region is reduced by selectively using a mask pattern only for a portion vulnerable to high voltage when implanting impurities for device isolation.

First, the weak part of the MOS transistor against high voltage was investigated.

4A is an NMOS transistor having a DDD structure, in which the same reference numerals as used in FIG. 1A denote the same elements, and the reference numeral 400 denotes a high voltage vulnerable region having characteristics vulnerable to high voltage.

As shown in FIG. 4A, the high voltage vulnerable region 400 is represented as a rectangular vertex portion formed by the active region 103 and the gate electrode 105 overlapping each other.

FIG. 4B is a longitudinal cross-sectional view of the high breakdown transistor illustrated in FIG. 4A taken along line X-X ′, and the high voltage vulnerable region 400 becomes a lower portion of the active region 103 into which the P + ions are introduced.

FIG. 4C is a cross-sectional view of the high breakdown transistor shown in FIG. 4A taken along the line Y-Y ', and the high voltage weak spot 400 does not appear here.

As described above, the reason that each vertex portion of the quadrangle formed by overlapping the active region 101 and the gate electrode 105 is vulnerable to high voltage is because P + ions remain in the region.

Therefore, the high breakdown voltage characteristic can be maintained even if only the high voltage weak region 400 is blocked by the mask pattern without the masking of the entire active region 103 and the implantation process of P + ions for device isolation is performed.

5 shows breakdown voltage characteristics of several kinds of transistors. Here, A, B and C represent breakdown voltage characteristics of the transistors shown in FIGS. 6A to 6B, 7A to 7B, and 8A to 8B, respectively.

6A and 6B are cross-sectional and longitudinal cross-sectional views, respectively, of the NMOS transistor in which the P + ion implantation region 507 for device isolation flows into the lower portion of the gate electrode 505 and does not adopt a DDD structure. Here, reference numerals 500, 501 and 509 show N + ion implanted regions for forming a semiconductor substrate, a field oxide film and a source / drain, respectively.

7A and 7B show a cross-sectional view and a longitudinal cross-sectional view of an NMOS transistor in which a P + ion implantation region 607 for device isolation is formed only under the field oxide film 601, and without a DDD structure. Here, reference numerals 600, 605, and 609 denote N + ion implantation regions for forming a semiconductor substrate, a gate electrode, and a source / drain, respectively.

8A and 8B show a cross-sectional view and a longitudinal cross-sectional view of an NMOS transistor in which a device isolation P + ion implantation region 707 is formed only below the field oxide film 701, and employs a DDD structure. Here, reference numerals 700 and 705 denote semiconductor substrates and gate electrodes, respectively.

When comparing A and B with reference to FIG. 5, it can be seen that higher breakdown voltage characteristics can be obtained when the P + ion implantation region for device isolation does not flow into the lower portion of the gate electrode. In comparison with B and C, it can be seen that a transistor having a DDD structure has a larger breakdown voltage characteristic, and that a DDD structure is preferably adopted to obtain a transistor operating at a high voltage of about 15V or more.

9A to 9E are views illustrating a method of manufacturing a high breakdown voltage transistor according to an exemplary embodiment of the present invention. Here, reference numerals 802, 803, 805, and 807 denote a semiconductor substrate, an active region, a gate electrode, and a mask pattern for device isolation, respectively. Further, reference numerals 809, 811, and 813 show P + ion implantation regions for device isolation, N + ion implantation regions, and N-ion implantation regions for source / drain formation, respectively.

9A is a plan view of an NMOS transistor having a DDD structure, and shows a state in which a gate electrode 805 is formed on the active region 803.

The mask pattern 807 may be formed to be slightly larger than a rectangle formed by overlapping the gate electrode 805 and the active region 503 so as to mask the region 800 vulnerable to high voltage. That is, the mask pattern 807 may be formed such that each side is positioned about 0.1 to 1.0 μm from each side of a rectangular side formed by the active region 803 and the gate electrode 805 overlapping each other.

9B and 9C are longitudinal cross-sectional views of the high breakdown voltage transistor shown in FIG. 9A taken along lines X-X 'and Z-Z', respectively.

9B, since the device isolation mask pattern 807 is larger than a rectangle formed by overlapping the gate electrode 805 and the active region 803, the P + ion implanted region 809 may be formed in the field oxide layer. It is formed only in the lower portion of the 801, it is not formed in the lower portion of the gate electrode 805.

Meanwhile, referring to FIG. 9C, the mask pattern 807 may not mask the active region 803 as a whole but only a rectangle 805 overlapping the active region 803 and the gate electrode 805. Therefore, the P + ion implantation region 809 is formed under the active region 803.

FIG. 9D is a cross-sectional view of the high withstand voltage transistor illustrated in FIG. 9A taken along the line Y-Y '. Here, the high concentration P-type impurities present in the lower portion of the active region 803 are offset by the N-type impurities implanted in the subsequent process.

FIG. 9E shows the layout of the high breakdown transistor shown in FIG. 9A. Reference numerals M1 and M2 denote the length of the device isolation region and the separation distance between the mask patterns 807, respectively.

As shown in FIG. 9E, the mask pattern 807 selectively masks only a part of the active region 803, so that the length M1 of the device isolation region is not limited by the separation distance between the mask patterns 807. Therefore, the length M1 of the device isolation region may be maintained at a minimum design rule.

Meanwhile, the present invention can also be performed using two or more mask patterns which respectively mask a part of a region vulnerable to high voltage.

9A to 9E are views illustrating a method of manufacturing a high breakdown voltage transistor according to an exemplary embodiment of the present invention.

10A to 10B are diagrams for describing a method of manufacturing a high breakdown voltage transistor according to another exemplary embodiment of the present invention, wherein two mask patterns respectively masking two vertices of a rectangle formed by overlapping an active region and a gate electrode are illustrated. That is, the implantation process of the element separation impurity is performed using the 1st each piece 907a and the 2nd each piece 907b. In this case, the first corner piece 907a masks the first vertex 900a and the second vertex 900b among the vertices of the quadrangle, and the second corner piece 907b is the third vertex 900c and the fourth vertex. Mask 900d.

Also in the second embodiment, the length M1 'of the device isolation region is not limited by the distance M2' between the respective pieces 907a or 907b, so that the length M1 'of the device isolation region is the minimum design rule. I can keep it.

The present invention can be applied not only to NMOS transistors, but also to PMOS transistors, and the portions having characteristics vulnerable to high voltages are not necessarily limited to the rectangular vertex portions because they may vary depending on the shape of the gate electrode or the active region.

In addition, the present invention can be variously modified by those skilled in the art within the technical scope of the present invention.

According to the present invention, since the separation distance between the active regions is not limited by the distance between the element isolation masks, it is possible to manufacture a semiconductor device having a high breakdown voltage characteristic while reducing the length of the element isolation regions.

Claims (2)

(A) forming a rectangular active region in the semiconductor substrate defined by the device isolation region; (B) forming a gate electrode on the semiconductor substrate with a gate insulating layer interposed therebetween so that the gate electrode and the active region intersect at a predetermined portion; (C) forming an impurity implantation region for device isolation using a mask pattern having an opening formed to completely expose portions except for the region where the active region and the gate electrode overlap, as an ion implantation mask; (D) forming source and drain regions on both sides of the gate electrode in the active region, respectively; And (E) forming a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively. The method of claim 1, The mask pattern may have a quadrangular shape, and a distance from each side of the rectangular region where the active region and the gate electrode overlap each other to each side of the mask pattern corresponding to each side may be 0.1 to 1.0 μm apart. Method for manufacturing a transistor of a semiconductor device.

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