KR100243258B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a bend conductor memory device and a method of manufacturing the same.

According to the present invention, there is provided a semiconductor memory device including a plurality of memory cells including one transistor and one capacitor, wherein the capacitor is the active and field of the semiconductor substrate separated into an active region and a field region by a field oxide film. A first trench formed in a predetermined portion of the region and a second trench formed in the active region side of the first trench; A storage electrode formed on an inner wall of the first trench, an inner wall and an outer wall of the second trench, and connected to a source region of the transistor in a predetermined portion; A dielectric film formed on a surface of the storage electrode; And a plate electrode formed on the dielectric film and filling the inside of the first and second trenches and formed on the dielectric film.

As a result, a highly integrated semiconductor memory device can be realized.

Description

Semiconductor memory device and manufacturing method

1 is a simplified layout showing a conventional trench cell.

2 is a simplified layout showing a conventional AST cell.

3 is a simplified layout for explaining a conventional semiconductor memory device having an AST cell.

4 through 8 are cross-sectional views illustrating a method of manufacturing a conventional semiconductor memory device having an AST cell.

9 is a simplified layout showing the trench cells of the semiconductor memory device of the present invention.

10 is a cross-sectional view taken along the line AA ′ of FIG. 9.

11 through 17 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device of the present invention.

18 is a simplified layout showing a trench cell of a semiconductor memory device according to an embodiment of the present invention.

19 is a three-dimensional simplified diagram of a trench cell in a semiconductor memory device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device and a method of manufacturing the same that enable the manufacture of a highly integrated memory device.

Recently, as the development of semiconductor manufacturing technology and the application field of memory devices are expanded, the development of large-capacity memory devices is actively progressed. In particular, one memory cell is composed of one capacitor and one transistor for high integration. Significant advances have been made in advantageous Dynamic Random Access Memory (DRAM).

The development of DRAM has achieved 4 times higher integration in three years. Currently, the density of DRAM is in the mass production stage of 4Mb DRAM, 16Mb is rapidly developing toward mass production, and 64Mb and 256Mb are for development. Active research is in progress.

Such a semiconductor memory device must have a large capacitance for reading and storing information. When the density increases by 4 times, the chip area increases only 1.4 times, so that the area of the memory cell is relatively 1/3. As a result, the conventional capacitor structure cannot secure sufficiently large cell capacitance within a limited area.

Therefore, a study of a method for obtaining larger capacitance in a limited area has been required. In particular, in order to realize a DRAM of 64 Mb or more, it is necessary to develop a structure capable of ensuring sufficient storage capacity in a memory cell area of about 1.5 mu m. To this end, a method of miniaturizing a memory cell having a conventional trench capacitor used in 4Mb and 16Mb DRAM is being studied. The biggest problem to be solved in this study is a problem of leakage current between memory cells due to miniaturization. The leakage current has two paths, one of which is a leakage current between adjacent trenches, and the other is a leakage current between the storage electrode and the adjacent element formation region (active region).

The leakage current between the adjacent trenches can be solved by proposing a so-called Burried Stacked Capacitor Cell (BSCC) structure in which an oxide film for preventing leakage current is formed before the storage electrode is formed in the trench. The problem of leakage between the contact portion of the storage electrode and the adjacent element formation region due to the effect of the diffusion of impurities from the contact portion of is still pointed out as a problem, which hinders miniaturization.

Accordingly, a new memory cell that can prevent leakage current as described above and can be applied to DRAM of 64 Mb or more has been proposed. Toshiba Corporation has proposed a "Process Integration for 64M DRAM using An Asymmetrical Stacked Trench Capacitor (AST) cell" (K. Sunouchi, F. Horiguchi, A. Nitayama, K. Hieda, H. Takato, N. Okabe, T. Yamada, T. Ozaki, K. Hashimoto, S.Takedai, A. Yagishita, A. Kumagae, Y. Takahashi and F. Masuoka, IEDM 90, pp. 647-650).

Figure 1 is a simplified layout showing a conventional trench cell, Figure 2 is a simplified layout showing the AST cell.

Comparing FIGS. 1 and 2, first, in the trench cell illustrated in FIG. 1, the trench T1 constituting the capacitor is symmetrically disposed with respect to the element formation region D1, whereas the second trench 2 is disposed in the trench cell. In the AST cell illustrated in FIG. 1, the trench T1 is asymmetrically disposed with respect to the element formation region D1, and in the AST cell, the contact portion C1 of the storage electrode used as the first electrode of the capacitor. Is completely contained in the element formation region D1, and an oxide film OX1 is formed on the inner wall of the trench T1 of the AST cell to insulate and separate the substrate from the trench. Accordingly, the AST cell can sufficiently secure the distance between the contact portion of the storage electrode and the adjacent device formation region due to the asymmetrical arrangement of the trenches, thereby suppressing the leakage current between the storage electrode and the adjacent device formation region. Can be. Further, due to the oxide film OX1 formed on the inner wall of the trench, leakage current between adjacent trenches can also be suppressed, thereby enabling miniaturization of the memory cell.

Therefore, in the AST cell, the trench diameter can be increased without being limited by the separation characteristics around the trench, so that sufficient accumulation capacity can be easily secured. Here, reference numeral A denotes a distance between adjacent element formation regions, B denotes a distance between adjacent trenches, and C denotes a distance between the element formation regions and the trenches.

3 is a simplified layout diagram illustrating a conventional method of manufacturing a semiconductor memory device including the AST cell, wherein a connection portion for connecting a region of a transistor and a storage electrode, which is a first electrode of a capacitor, is a trench defined by a double-dot chain line. A dotted line is defined between the pattern P1 and the active region M defined by a solid line, and a photoresist is formed in a region other than the pattern P2 for forming the connection portion. Therefore, in the subsequent etching process, only the N region is etched according to the pattern P2 for forming the connection portion, thereby forming the connection portion.

4 through 8 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device including the AST cell, and illustrate a cross-sectional view taken along line a-a 'of the layout of FIG.

4 is a cross-sectional view showing a state in which a trench is formed in a semiconductor substrate. For example, an oxide film and a nitride film are sequentially stacked on the semiconductor substrate 100 on which the device isolation film 101 is formed, whereby the first insulating film 1 and The second insulating film 2 is formed. Subsequently, the second insulating layer 2 is patterned, and then a third insulating layer 3 is formed by stacking, for example, HTO (High Temperature Oxide) on the entire surface of the resultant product. Subsequently, after the photoresist is applied on the third insulating film 3, P1, which is a mask pattern for forming trenches in FIG. 2, is applied to form the first photoresist pattern 4 through exposure and development processes. Next, a trench is formed in the semiconductor substrate 100 at a predetermined depth using the first photoresist pattern 4 as a mask.

5 is a cross-sectional view of a leakage current prevention film formed therein, and after the first photoresist pattern is removed, the trench 10 is thermally oxidized to prevent leakage current between adjacent trenches on the inner wall of the trench. The current blocking film 11 is formed.

FIG. 6 illustrates a process of forming a contact portion CA. In order to form a contact portion between a storage electrode of a capacitor to be formed in the trench and a source region of a transistor, FIG. After the photoresist is applied, the mask pattern P2 of FIG. 2 is applied to form a second photoresist pattern 5 as shown in FIG. Subsequently, a part of the leakage current prevention film is removed using the second photoresist pattern 5 as a mask to form a contact portion CA of the storage electrode serving as the capacitor first electrode. As a result, the contact portion of the storage electrode can be completely enclosed in the element region by the forming step of the contact portion, thereby sufficiently securing the distance to the adjacent element region.

FIG. 7 illustrates a process of forming a first electrode and a dielectric film of a capacitor. First, the second photoresist pattern is removed, and then the first conductive layer is deposited on the entire surface of the resultant material, for example, doped with polycrystalline silicon doped with impurities. And, by patterning this, the storage electrode 13 used as the first electrode of the capacitor is formed. Subsequently, a dielectric material is coated on the storage electrode 13 to form the dielectric film 15 of the capacitor.

FIG. 8 illustrates a process of forming a second electrode and a transistor of a capacitor, and depositing and patterning polycrystalline silicon doped with impurities, for example, with a second conductive layer on the entire surface of the dielectric film formed thereon. The plate electrode 17 used as the second electrode is formed. In this way, a capacitor including the storage electrode 13, the dielectric film 15, and the plate electrode 17 is completed. After the capacitor is formed, the transistor is completed by forming the gate electrode G, the source 20 and the drain region (not shown) as shown.

In the conventional method of manufacturing a semiconductor memory device having an AST cell as described above, the leakage problem between the adjacent trenches and between the contact portion of the capacitor storage electrode and the adjacent element formation region is solved by forming a leakage current prevention film. As shown in FIG. 6, the photolithography process of removing part of the leakage current layer 11 is added to form a contact portion CA for connecting the source of the transistor and the storage electrode of the capacitor. There are disadvantages. In addition, due to the limitation of the photolithography process when forming the contact portion between the source of the transistor and the storage electrode of the capacitor, it is difficult to apply the actual process in manufacturing a device that is highly integrated, and to secure the capacitor capacity according to the size reduction of the device. Although the trench depth is required to be deeper or the surface area in the chip occupied by the trench is required to be increased, the conventional method has a problem in that a process limitation exists.

An object of the present invention is to provide a semiconductor memory device capable of ensuring a sufficient capacitor capacity.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device which can be highly integrated by an easy process and ensures sufficient capacitor capacity.

In order to achieve the above object, the present invention provides a semiconductor memory device including a plurality of memory cells including one transistor and one capacitor, wherein the capacitor is divided into an active region and a field region by a field oxide film. A first trench formed in predetermined portions of the active and field regions, a second trench formed in the active region side of the first trench, an inner wall of the first trench, and an inner wall and an outer wall of the second trench; A storage electrode connected at a predetermined portion of the source region, a dielectric film formed on a surface of the storage electrode, and a plate electrode formed on the dielectric film and filling the inside of the first and second trenches and formed on the dielectric film. A semiconductor memory device is provided.

In order to achieve the above another object, the method of the present invention comprises a first step of forming a field oxide film on a semiconductor substrate by recessing the substrate and then forming a multilayer mask layer on the resultant; A second process of patterning the mask layers into a first trench pattern by a photolithography process; A third process of first etching the semiconductor substrate by using the patterned mask layers and the field oxide layer as a mask to form a second trench; Forming an anti-oxidation insulating film spacer on the patterned mask layer and the sidewalls of the second trench; A fifth step of exposing a predetermined portion of the semiconductor substrate by removing the field oxide film exposed in the second step; A sixth step of etching the first formed second trench and the semiconductor substrate exposed in the fifth step to a predetermined depth to complete the second trench and to form the first trench; A seventh step of oxidizing the first and second trench wall surfaces to form a leakage current prevention film; An eighth step of removing the antioxidant insulating film spacer; A ninth step of forming a capacitor by sequentially forming a storage electrode, a dielectric film, and a plate electrode on the resultant product; And forming a insulating film on the plate electrode, and then forming a gate insulating film, a gate electrode, a source, and a drain region in a predetermined region of the active region in order to complete a transistor. Provide a method.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

9 is a simplified layout showing a memory cell portion of the semiconductor memory device of the present invention, in which adjacent trenches are formed facing both sides of a field oxide film (not shown), and the trenches are formed at predetermined portions of the active and field regions. A first trench T20 and a second trench T10 formed in the active region inside the first trench are formed. A leakage current blocking film 39 is formed on an inner wall of the first trench T20, an inner wall of the second trench, and an outer wall (which may correspond to an inner wall of the first trench).

In addition, a conductive layer 40 serving as a storage electrode of the capacitor is formed on the leakage current blocking layer 39. As shown in FIG. 9, the trench sidewalls of the active region are shared with the first and second trenches. In the portion, the conductive layer 40 is connected to form one storage electrode.

FIG. 10 is a cross-sectional view taken along the line A-A 'of FIG. 9, and the same parts as those of FIG. 9 are designated by the same reference numerals. Reference numeral 30 denotes a semiconductor substrate, 31 a field oxide film, 41 a dielectric film, 42 a plate electrode, 43 a source region of a transistor, 44 an insulating film, 45 a gate insulating film, and 46 a gate electrode. .

As shown in FIGS. 9 and 10, the semiconductor memory device of the present invention has a double trench consisting of a first trench and a second trench, thereby increasing the area of the trench sidewalls and thus the surface area of the capacitor storage electrode. As a result, the capacitance of the capacitor can be sufficiently secured.

Next, a manufacturing method of the semiconductor memory device of the present invention will be described with reference to FIGS.

First, FIG. 11 shows a process of forming the field oxide film and the mask layers. The field oxide film 31 of about 5000 kW is recessed and formed into the substrate on the semiconductor substrate 30, followed by the pad oxide film. (32) is formed, and then a silicon nitride film 33 and a high temperature oxide 34 (HTO) 34 are sequentially stacked as a mask layer to be used in the subsequent trench formation.

FIG. 12 illustrates a process of patterning the mask layers into a first trench pattern. The HTO 34 and the silicon nitride layer 33 are formed in a predetermined first trench pattern through a photolithography process using a photoresist 35. Pattern. At this time, a part of the semiconductor substrate and a part of the field oxide film of the active region are exposed.

FIG. 13 illustrates a process of first forming a second trench, and after removing the photoresist used in the photolithography process, using the patterned HTO 34 and the silicon nitride film 33 as a mask, the active region. The exposed semiconductor substrate of is etched to form a second trench 36. At this time, the depth of the second trench to be formed is formed to be equal to or shallower than the depth of the field oxide film 31 recessed into the semiconductor substrate, that is, the depth of about 3000 ~ 5000Å. Subsequently, a silicon nitride film is deposited as a thermal oxidation prevention film on the resultant, and then, the silicon nitride film spacer 37 is formed on the HTO 34 and the silicon nitride film 33 and the first sidewalls of the second trench formed thereon.

FIG. 14 illustrates a process of removing a portion of the field oxide layer to form a first trench, wherein the silicon nitride layer spacer 37 masks the exposed field oxide layer during patterning of the mask layers 33 and 34. Remove it selectively.

FIG. 15 illustrates a process of forming the first trench and simultaneously forming the first trench, wherein the patterned mask layers 33 and 34 and the silicon nitride film spacer 37 formed in the above process are formed. The first and second trenches 38 are formed by etching the semiconductor substrate to a predetermined depth using the mask.

FIG. 16 illustrates a process of forming a leakage current prevention film for separating leakage between trenches to prevent leakage current between trenches, and oxidizing a resultant in which the first and second trenches are formed to form an oxide film having a thickness of 500 mV to 1000 mW on the trench wall surface. Form 39. In this case, since the silicon nitride film spacer 37 is formed in the contact portion CA to which the source region of the transistor and the storage electrode of the capacitor are to be connected, that is, the upper portion of the sidewall of the active region of the formed second trench. Not oxidized.

FIG. 17 is a step of forming a transistor and a capacitor of a semiconductor memory device. After removing the silicon nitride film spacer, a conductive material is deposited on the sidewalls of the trench to form a capacitor storage electrode 40, and then the surface of the storage electrode 40. After the dielectric film 41 is formed, the capacitor is completed by a conventional process of filling the inside of the trench to form the plate electrode 42 of the capacitor on the dielectric film 41. Subsequently, after the insulating film 44 is formed on the plate electrode 42, a gate insulating film 45, a gate electrode 46 and a source / drain region 43 are formed in predetermined portions through a predetermined process to form a transistor. Complete

As described above, in the present invention, the contact portion between the source of the transistor and the storage electrode of the capacitor is used in the oxide film forming process for insulating between the thermal oxidation film forming process and the trench without using an additional process such as a photolithography process as in the prior art. Because of the self-consistent formation, the process is simplified and the limitation of the integration density due to the photolithography process is overcome.

Further, by forming a double trench using the field oxide film recessed in the semiconductor substrate as described above, the capacity of the capacitor that can be secured in the same chip area is increased.

Next, FIG. 18 shows an embodiment of the layout of the semiconductor memory device of the present invention, and FIG. 20 is a schematic three-dimensional view of the trench cell of the semiconductor memory device formed by applying the layout of FIG. In the drawings, the same parts as those of FIGS. 9 and 10 are designated by the same reference numerals. As shown in FIG. 19, the semiconductor memory device of the present invention is very advantageous for securing the capacitor capacity by increasing the three-dimensional area.

As described above, according to the present invention, a semiconductor memory device having a sufficient capacitor capacity can be manufactured by a simple process, thereby contributing to the realization of a highly integrated semiconductor memory device.

Claims (13)

A semiconductor memory device comprising a plurality of memory cells comprising one transistor and one capacitor, wherein the capacitor is a predetermined portion of the active region and the field region of the semiconductor substrate separated by the field oxide layer into an active region and a field region. A first trench formed in the second trench and a second trench formed in the active region side of the first trench; A storage electrode formed on an inner wall of the first trench, an inner wall and an outer wall of the second trench, and connected to a source region of the transistor in a predetermined portion; A dielectric film formed on a surface of the storage electrode; And a plate electrode formed on the dielectric film and filling the inside of the first and second trenches and formed on the dielectric film. 2. The semiconductor memory device according to claim 1, wherein a leakage current prevention film is further formed on the trench wall under the storage electrode. 3. The semiconductor memory device according to claim 2, wherein the leakage current prevention film is an oxide film. The semiconductor memory device of claim 1, wherein a source region of the transistor is formed on an upper sidewall of an active region side of the second trench. The semiconductor memory device of claim 1, wherein the first trench and the second trench share sidewalls of the active region. The semiconductor memory device of claim 1, wherein a depth of the second trench is lower than a depth of the first trench. A first step of forming a field oxide film on the semiconductor substrate by recessing it into the substrate and then forming a multilayer mask layer on the resultant; A second process of patterning the mask layers into a first trench pattern by a photolithography process; A third process of first etching the semiconductor substrate by using the patterned mask layers and the field oxide layer as a mask to form a second trench; Forming an anti-oxidation insulating film spacer on the patterned mask layer and first sidewalls of the second trenches; A fifth step of exposing a predetermined portion of the semiconductor substrate by removing the field oxide film exposed in the second step; A sixth step of etching the first formed second trench and the semiconductor substrate exposed in the fifth step to a predetermined depth to complete the second trench and to form the first trench; A seventh step of oxidizing the first and second trench wall surfaces to form a leakage current prevention film; An eighth step of removing the antioxidant insulating film spacer; A ninth step of forming a capacitor by sequentially forming a storage electrode, a dielectric film, and a plate electrode on the resultant product; And forming a insulating film on the plate electrode, and then forming a gate insulating film, a gate electrode, a source, and a drain region in a predetermined region of the active region in order to complete a transistor. Way. The method of claim 7, wherein the multilayer mask layers of the first process are formed by sequentially depositing a pad oxide film, a silicon nitride film, and an HTO on a semiconductor substrate on which the field oxide film is formed. 8. The method of claim 7, wherein the depth of the semiconductor substrate to be etched in the third process is equal to or shallower than that of a field oxide film formed by being recessed into the semiconductor substrate. The method of claim 9, wherein a depth of the semiconductor substrate to be etched is about 3000 ns to about 5000 ns. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the antioxidant insulating film spacer of the fourth step is formed of a silicon nitride film. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the leakage current prevention film of the seventh step is formed at a thickness of 500 kV to 1000 kV. The method of claim 7, wherein a connection window for connecting the capacitor storage node and the source of the transistor to the active region is self-aligned only by a fourth process of forming an anti-oxidation insulating film spacer on the sidewall of the first etched second trench. A method of manufacturing a semiconductor memory device, characterized in that formed.