KR100243006B1 - Timing signal generator for charge coupled device camera - Google Patents

Abstract

The present invention relates to a timing signal generator of a CD camera that allows a screen to be edited using a timing signal generator. In the related art, there is no function that can be edited using a reset gate pulse. There is a problem that can not be viewed on the correct screen. Therefore, the present invention provides a signal generator 21 for generating a masking reset gate signal RG-1 for masking the reset gate signal RG in synchronization with the input main clock MCLK; Vertical control for vertically masking control of the reset gate signal RG by synchronizing the control data and the control vertical signal (ctl-ver2) (ctl-ver1) input from the microcomputer to the vertical synchronization signal input clock (HD CLK). A vertical reset gate controller 22 generating a signal Ver-Ctl; Horizontal reset gate controller 23 for generating a vertical control signal for horizontally masking control of the reset gate signal by synchronizing the control data and the control vertical signal ctl2-ver (ctl1-ver) input from the microcomputer to the pixel clock. )Wow; The masking reset gate signal RG-1 of the signal generator 21, the vertical control signal Ver-Ctl of the vertical reset gate controller 22, and the horizontal control signal of the horizontal reset gate controller 23 ( It consists of an oragate 24 that generates a reset gate signal RG for receiving a Hor-Ctl input and editing the screen, and the reset gate pulse is edited according to the control data according to the screen editing function in the microcomputer. When using such an editing function, it is possible to implement a relatively low price compared to the screen editing function using a conventional signal processing unit, and also, by using a reset gate pulse, it is possible to control the screen in units of pixels.

Description

Timing signal generator for CD cameras {TIMING SIGNAL GENERATOR FOR CHARGE COUPLED DEVICE CAMERA}

The present invention is to add a variety of screen editing functions to the video recording, in particular the timing of the CD camera to perform the screen editing function by changing the reset gate (RESET GATE: RG) output of the timing signal generator in units of fields It relates to a signal generator.

As shown in FIG. 1, a general CD camera system converts an optical signal input from the outside into an electrical signal according to the vertical synchronization signals H1 and H2 and the reset gate RG. CD 10 for outputting; A signal correction unit 30 which removes noise components of the signal converted through the CD 10, samples / holds the input analog signal, and converts the converted analog data into digital data whose gain is adjusted; A signal processor 40 for correcting or filtering digital data transmitted from the signal corrector 30 and finally outputting a video signal processed by the signal; The timing signal generator 20 generating the vertical synchronization signals H1 and H2, the reset gate signal RG, and the sample / holding signals SHD and SHP required by the CD 10 and the signal correction unit 30. )Wow; The timing signal generator 20 generates the necessary control data, and the signal processing section 40 constitutes a microcomputer 50 for performing the necessary control operations during signal processing.

Looking at the prior art configured as described above is as follows.

When the control data is generated by the microcomputer 50, the control data is inputted from the timing signal generator 20 and the vertical synchronization signals H1 and H2 and the reset gate signal RG (RESET GATE) required by the CD 10 are received. And generate and generate the sample / holding signals SHD and SHP required by the signal correction unit 30, respectively.

Then the CD 10 converts the optical signal input from the outside into an electrical signal

Output to the signal correction unit 30.

Accordingly, the signal correction unit 30 samples and holds the sample / holding signals SHD and SHP generated by the timing signal generator 20 to remove noise components, and is output from the CD 10. The gain value of the analog signal is adjusted and converted into digital data and output to the signal processor 40.

The signal processor 40 corrects the signal converted into digital data by the signal corrector 30 under the control of the microcomputer 50, and corrects the corrected video signal.

Finally output

However, there is a problem in that the conventional technology as described above does not have a function that can be edited using a reset gate (RG) pulse, so that the user can view a screen that meets the needs of the user.

Accordingly, an object of the present invention for solving the conventional problems as described above is to enable the screen control in units of pixels by using the reset gate (RG) pulse to cover-up (COVER UP), cover-down (COVER DOWN), Provides the timing signal generator of the CD camera to implement screen editing functions such as COVER LEFT, COVER RIGHT, BOX IN, and BOX OUT. Is in.

1 is a configuration of a conventional CD camera system.

Figure 2 is a detailed block diagram of the timing signal generator of the present invention the CD camera.

3 is a detailed block diagram of a vertical reset gate (RG) control in FIG.

4 is a detailed block diagram of the horizontal reset gate control unit in FIG.

FIG. 5 is an operational flowchart of V / 2 up-counter 1 in FIG.

FIG. 6 is an operational flowchart of V / 2 up-counter 2 in FIG.

FIG. 7 is a flowchart of operation of the H / 2 up-counter 1 in FIG. 4; FIG.

8 is a flowchart of operation of the H / 2 up-counter 2 in FIG.

FIG. 9 is a screen diagram illustrating vertical and horizontal control area allocation of a CD in FIG. 1.

10 is a table showing control data for each screen edit stored in the microcomputer.

*** Explanation of symbols for main parts of drawing ***

10: CD 20: Timing Signal Generator

30: signal correction unit 40: signal processing unit

50: microcomputer

The timing signal generator configuration of the CD camera of the present invention for achieving the above object is, as shown in Figure 2, the masking reset gate for masking the reset gate signal RG in synchronization with the input main clock (MCLK) A signal generator 21 for generating a signal RG_1; The vertical control signal Ver-Ctl for vertically masking control of the reset gate signal RG by synchronizing the control data and the control vertical signal Ctl_Ver2 and Ctl_Ver1 input from the microcomputer to the horizontal data clock HDCLK is performed. A vertical reset gate controller 22 generated; Vertical control signal Hor_Ct1 for horizontally masking control of the reset gate signal RG by synchronizing control data and control horizontal signals Ctl-Hor Ct2-Hor inputted from the microcomputer to the pixel clock PCLK. A horizontal reset gate controller 23 generating a); The masking reset gate signal RG_1 of the signal generator 21, the vertical control signal Ver_Ctl of the vertical reset gate control unit 22, and the horizontal control signal Hor_Ctl of the horizontal reset gate control unit 23, respectively. It is composed of an ora gate 24 for generating a reset gate signal (RG) to receive the input and edit the screen.

In the above, the vertical reset gate controller 22, as shown in Fig. 3, the first half of the vertical synchronization to output the value obtained by counting the 1/2 section of the horizontal synchronization signal of the normal screen when the control data input from the microcomputer ( 221; A second half of vertical sync for outputting a value obtained by counting the remaining half of the horizontal sync signal of the normal screen when inputting control data from the microcomputer; A first exclusive oragate 223 for receiving and exclusively ringing the count value of the first half of the vertical synchronization unit 221 and the first control vertical signal ct1-ver from the microcomputer; A second exclusive oragate 224 for receiving an exclusive control of the second control vertical signal ct2-ver and the count value of the second half of the vertical synchronization unit 222 from the microcomputer; The first or second gates 223 and 224 output the vertical control signals Ver-ct1 by outputting the output signals of the second exclusive orifices 223 and 224.

Also, as shown in FIG. 4, the horizontal reset gate control unit 23 outputs a value obtained by counting 1/2 section of the vertical synchronization signal of the normal screen when the control data input from the microcomputer is input. 231; A horizontal synchronous second half 232 for outputting a value obtained by counting the remaining half of the vertical synchronous signal of the normal screen when inputting control data from the microcomputer; A third exclusive oragate 233 which receives the count value of the first half of the horizontal synchronization unit 231 and the first control horizontal signal ct1-Hor from the microcomputer, and exclusively rings the first and second horizontal signals ct1-Hor; A fourth exclusive oragate 234 which receives exclusively the second control horizontal signal ct2-Hor from the microcomputer and the count value of the second half of the horizontal synchronization unit 232, respectively; The second or second gate 235 is configured to output the horizontal control signal Hor-ct1 by ringing the output signals of the third and fourth exclusive orifices 233 and 234.

Referring to the operation and effect of the present invention configured as described in detail as follows.

In the microcomputer of FIG. 1, when the control signal and the various control signals in the horizontal and vertical directions for adjusting the screen position are provided to the timing signal generator 20, the timing signal generator 20 shown in FIG. It is input by the vertical reset gate controller 22 and the horizontal reset gate controller 23.

That is, in the microcomputer 50, the vertical reset gate controller 22 controls the control data and the control vertical signal Ct2_Ver (Ct1_Ver) for position adjustment, and the horizontal reset gate controller 23 controls the control data and the control horizontal signal Ct2_Hor. Outputs (Ct1_Hor) respectively.

Accordingly, the vertical reset gate controller 22 generates and outputs a vertical control signal Ver_Ct1, and the horizontal reset gate controller 23 generates and outputs a horizontal control signal Hor_Ct1.

Here, a detailed operation of the vertical reset gate controller 22 and the horizontal reset gate controller 23 will be described.

First, as shown in FIG. 3, the input portion of the vertical data front control unit 221 of the vertical reset gate control unit 22 receives input during 1/2 section (C section) of the vertical synchronization signal VD of the normal screen shown in FIG. 9. It counts and outputs the counted Ver_Ct1_1 signal to the 1st exclusive orifice 223. FIG.

Then, the first exclusive ogate 223 receives the first control vertical signal Ct1_Ver transmitted from the microcomputer and outputs the exclusively ringed signal together with the Ver_Ct1_1 signal to the first ogate 225.

At the same time, the vertical data latter half control unit 222 also counts the inputs for the remaining 1/2 section (section D) of the vertical synchronization signal VD of the normal screen as shown in FIG. Output to 2 exclusive oragate 224.

Then, the second exclusive ogate 224 receives the second control vertical signal Ct2_Ver transmitted from the microcomputer and outputs the exclusively ringed path along with the Ver_Ct1_2 signal to the first ogate 225. .

Accordingly, the first oragate 225 generates the vertical control signal Ver_Ct1 by outputting the output signals of the first and second exclusive oragate 223 and 224.

Referring to FIG. 5, the operation of the vertical data front half control unit 221 starts to count the HD clock after loading the horizontal control data HD1 from the microcomputer.

The count value V / 2 obtained by performing the clock HD * integer, that is, as compared with the value of the half section (section C) of the vertical synchronization signal VD of the normal screen as shown in FIG.

As a result of comparison, if the count value (HD * integer) is less than or equal to the V / 2 value (section C), the low-state Ver_ct1_1 signal is output; if the count value (HD * integer) is greater than the V / 2 value, the HD clock The counting operation is terminated and the high Ver_Ct1_1 signal is output.

In addition, referring to FIG. 6, the operation of the vertical data second half control unit 222 is loaded with the horizontal control data HD2 from the microcomputer, and then placed in the center of the active period of the horizontal synchronization signal HD. Start counting.

The count value obtained by the same method as the clock HD * integer is compared with the value of V / 2, that is, the other half section (section D) of the vertical synchronization signal VD period of the normal screen as shown in FIG.

As a result of the comparison, if the count value is equal to or smaller than the V / 2 value (section D), the Ver_Ct1_2 signal in the high state is output. If the count value is small, the counting operation of the HD clock is terminated and the Ver_Ct1_2 signal in the low state is output.

Similarly, the horizontal data front half control section 231 of the horizontal reset gate control section 23 as shown in FIG. 4 is input during half section (section A) of the horizontal synchronization signal input HD of the normal screen as shown in FIG. And the Hor_Ct1_1 signal, which is the counted value, is output to the third exclusive orifice 233.

Then, the third exclusive ogate 233 receives the second control vertical signal Ct1_Hor transmitted from the microcomputer and outputs the exclusively ringed signal together with the Hor_ct1_1 signal to the second ogate 235.

At this time, the second half of the horizontal data control unit 232 similarly counts the input for the remaining 1/2 section (Section B) of the horizontal synchronization signal input HD on the normal screen, and the Hor_Ct1_2 signal of the counted value is Output to the fourth exclusive ogate 234.

Then, the fourth exclusive ogate 234 receives the fourth control horizontal signal Ct2-Hor transmitted from the microcomputer and exclusively rings the signal path that is exclusively ringed with the Hor_Ct1_2 signal to the second oargate 235. Output

Accordingly, the second oar gate 235 generates the horizontal control signal Hor_Ct1 by outputting the output signals of the third and fourth exclusive ogates 233 and 234.

The operation of the horizontal data front half control unit 231 will be described based on FIG. 7 after the vertical control data VD1 is loaded from the microcomputer. The pixel clock H1 or H2 starts to be counted.

The count value H / 2 obtained by performing pixel clock H2 * integer, that is, as compared with the value of 1/2 section (section A) of the horizontal synchronization signal HD of the normal picture as shown in FIG.

As a result of the comparison, when the count value (H2 * integer) is equal to or less than the H / 2 value (section A), the Hor_Ct1_1 signal in the low state is output.If the count value (H2 * integer) is greater than the H / 2 value, the pixel clock ( The counting operation of H1 or H2) ends and outputs a high Hor_Ct1_1 signal.

In addition, referring to FIG. 8, the operation of the horizontal data second half control unit 232 is performed by loading the vertical control data VD2 from the microcomputer, and then placing it in the center of the active period of the pixel clock H1 and then counting. To start.

The count value obtained in the same manner as the pixel clock (H2) * integer is compared with the value of H / 2, that is, the remaining 1/2 section (section B) of the horizontal synchronization signal HD period of the normal screen as shown in FIG. .

As a result of the comparison, when the count value is equal to or smaller than the H / 2 value (section B), the Hor_Ct1_2 signal in the high state is output, and when the count value is small, the counting operation of the pixel clock H1 or H2 is terminated and the Hor_Ct1_2 signal in the low state is terminated. Output

Then, in FIG. 2, the RG_1 signal of the signal generator 21, the Ver_Ct1 signal of the vertical reset gate controller 22, and the Hor_Ct1 signal of the horizontal reset gate controller 23 are ORed from the oragate 24 to reset the gate ( RG) outputs a pulse.

The microcomputer 50 transmits control data for each field to the vertical reset gate controller 22 and the horizontal reset gate controller 23 operating as described above.

The control data transmitted at this time is box in, box out, cover down, cover up, cover left, cover light, as shown in FIG. It is controlled differently according to screen editing function such as COVER RIGHT).

As a result, when the microcomputer 50 of FIG. 1 outputs control data according to the screen editing function as shown in FIG. 10 to the timing signal generator 20, the timing signal generator 20 is controlled by the CD 10. Outputs the reset gate (RG) signal to enable editing of the screen.

As described above, when the microcomputer outputs control data capable of performing a desired screen editing function, the timing signal generator receives an input so that the reset gate signal for editing can be output to the CD for editing. Using the same editing function has an effect that it can be implemented at a relatively low price compared to the screen editing function using a conventional signal processor.

In addition, the use of the reset gate pulse has the effect of enabling screen control in units of pixels.

Claims (3)

In a CD camera system in which a CD camera receives a reset gate (RG) signal and performs various screen editing functions for video recording, a reset gate signal (RG) to be finally outputted when a main clock (MCLK) is input. A signal generator for generating a masking reset gate signal RG_1 for masking the mask; A vertical reset gate controller configured to generate and generate a vertical control signal Ver_Ct1 for vertically masking control of the reset gate signal by using control data and a control vertical signal Ct2_Ver Ct1_Ver inputted from a microcomputer; A horizontal reset gate controller configured to generate and generate a vertical control signal Hor_Ct1 for horizontally masking control of the reset gate signal by using control data and a control horizontal signal Ct2_Hor Ct1_Hor input from a microcomputer; It is composed of an oragate which generates and generates a reset gate signal RG that can be edited by receiving the masking reset gate signal RG_1, the vertical control signal Ver_Ct1 and the horizontal control signal Hor_Ct1, respectively. Timing signal generator of the CD camera, characterized in that. The vertical reset gate control unit of claim 1, further comprising: a vertical data front control unit which outputs a value obtained by counting a half of a vertical synchronization signal of a normal screen when a control data input from a microcomputer is input; A vertical data second half control unit for outputting a value obtained by counting the remaining 1/2 section after counting by the vertical data first half control unit; A first exclusive oragate configured to receive and exclusively receive a count value of the vertical data front control unit and a first control vertical signal from a microcomputer; A second exclusive oragate that receives a second control vertical signal from the microcomputer and a count value of the second half of the vertical data controller and exclusively rings the second control vertical signal; And a first oragate configured to output a vertical control signal for controlling the vertical direction of the screen by ringing the output signals of the first and second exclusive oragates. The horizontal reset gate control unit of claim 1, further comprising: a horizontal data front control unit for outputting a value obtained by counting a half section of the horizontal synchronization signal of the normal screen when inputting control data input from a microcomputer; A horizontal data second half control unit for outputting a value obtained by counting the remaining 1/2 section after counting by the horizontal data first half control unit; A third exclusive oragate which receives the count value of the first half horizontal control unit and the first control horizontal signal from the microcomputer and exclusively rings the third data; A fourth exclusive oragate which receives the second control horizontal signal from the microcomputer and the count value of the second half of the horizontal data control unit and exclusively rings the second control horizontal signal; And a second orifice configured to output a horizontal control signal for controlling a horizontal direction of the screen by ringing the output signals of the third and fourth exclusive orifices.

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