KR100241741B1 - The sector address converting circuit of hard disk driving apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a technique for converting a logical sector address representing a specific position on a disk into a physical sector address in a hard disk drive.

2. Technical problem to be solved by the invention

Software-intensive sector address translation improves the time-consuming process.

3. Summary of Solution to Invention

One input of the logical sector address is sequentially operated in the first and second operation modes, and in the first operation mode, the logical sector address is divided by the number of sectors per cylinder to output a share as the cylinder number, followed by the second operation. In this mode, the remainder of the cylinder number calculation is divided by the number of sectors per track, and the quotient is output as the head number, and the remainder is output as the sector number.

4. Important uses of the invention

It is used to reduce the time required for sector address translation on the HDD.

Description

Sector Address Translation Circuit of Hard Disk Drive

1 is a sector address conversion circuit diagram according to the present invention.

2 is an operation timing diagram of FIG.

3 is a detailed configuration diagram of the divider 16 in FIG.

4 is a detailed configuration diagram of the subtractor 10 in FIG. 1 and the subtractor 40 in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard disk drive (hereinafter referred to as "HDD"), and more particularly to a circuit for converting a logical sector address representing a specific location on a disk into a physical sector address. It is about.

In general, the HDD has the advantage of accessing a large amount of data at high speed, and is widely used as a secondary memory device of a computer system. In a disk drive such as an HDD, data is stored sector by sector in tracks arranged concentrically on a magnetic disk. These tracks are accessed sector by sector by magnetic heads (or data transducers) for reading, writing and erasing data on the disc.

Typical HDDs use two or more double-sided disks stacked on a single spindle, with one-to-one correspondence to each disk surface, with heads moving simultaneously on the disk. In such an HDD, three coordinates are used when the disk controller refers to a specific position on the disk, that is, a head number, a cylinder number, and a sector number. The head number is a number assigned to the heads, which indicates a specific disk surface. The cylinder number is a number assigned to the cylinders, and one cylinder includes all tracks arranged at the same position on each disk surface. A sector number is a number assigned to sectors. A sector is a unit area for accessing data on a disk by dividing a track into a wedge shape. For example, if you have 4 heads, 3000 cylinders, and 100 sectors per track, you have 3000 × 4 × 100 = 1,200,000 of the total number of sectors. DOS (Disk Operating System), which is widely used at present, considers using 512-byte sectors, so that two sectors are 1K bytes, and thus a disk having 1,200,000 sectors has a storage capacity of 600M bytes. Therefore, it can be seen that the storage capacity of the HDD is determined according to the number of heads, the number of cylinders, and the number of sectors per track. These three coordinates are called physical sector addresses. The physical sector address as described above typically depends on the manufacturer or product model.

On the other hand, an interface on the host computer side has to have a uniform sector address system because it must be able to operate when connected to any HDD. In DOS, for example, sectors on a disk are arranged in a one-dimensional sector numbering scheme. DOS simply numbers all sectors on track 0, starting with sector 0 on disk 0 and track 0, followed by the previous number to the next, disk 1, sector on track 0. All sectors are numbered out. Such a sector address is called a logical sector address, and both the physical sector address and the logical sector address represent a specific position on the disk, that is, a specific sector, although there is a difference in representation.

There are mainly two types of interfaces between the HDD and the computer system. One is a small computer system interface (SCSI), which is mainly used for workstation-class computers or advanced PCs, and the other is an IDE (Integrated Devoce Electronics). In case of SCSI, only logical sector address is supported.In case of IDE, it supports both CHS (Cylinder, Head, Sector), that is, physical sector address and LBA (Logical Block Address), that is, logical sector address. The trend is to use.

Therefore, in order to refer to a specific position on the disk indicated by the logical sector address input from the host computer in the HDD, the logical sector address must be converted into a physical sector address indicating a physical position on the actual disk.

Conventionally, such sector address translation has been processed in software by an MPU (Micro Processor Unit) provided in the HDD. However, the sector address translation has a disadvantage in that it takes time because the calculation of the sum or decrease is repeated. In particular, when using a general CPU, the division takes a lot of time.

Accordingly, an object of the present invention is to provide a sector address conversion circuit that can reduce the time required for sector address translation.

Another object of the present invention is to provide a sector address translation circuit capable of processing sector address translation with simple hardware.

The sector address conversion circuit of the present invention for achieving the above objects operates sequentially in the first and second operating modes for one input of the logical sector address, and in the first operating mode, the logical sector address in sectors per cylinder. The quotient is output by the number of cylinders, and in the following second operation mode, the quotient of the cylinder number operation is divided by the number of sectors per track to output the quotient by the head number, and the remainder is output by the sector number.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Many specific details are set forth in order to provide a more thorough understanding of the present invention, such as in the following description and the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

1 shows a sector address conversion circuit diagram according to the present invention, which is applied to an HDD employing a recording method in the form of " constant-density " or " zone-bit ". Will be shown. The constant-density recording form allows all tracks, including inner tracks and outer tracks, to have substantially the same information density in order to improve the information capacity of the disc. In the constant-density recording form, the information recording area on the magnetic disk is divided into a plurality of zones in which the recording density is constant in the radial direction from the centrifugal on the magnetic disk. Accordingly, when the constant-density recording type is adopted, sector address translation must be performed in consideration of the zone.

In addition, in order to convert a logical sector address into a physical sector address, two separate divisions are generally required. However, in the present invention, as described later, one divider 16 is used for one logical sector address input using time division multiplexing. The circuit configuration was simplified by performing two divisions alone. To this end, the first and second operation modes are sequentially designated for one input of the logical sector address for the same time as the operation designation signal CYLB_HDSEC shown in FIG. 2 showing the operation timing of FIG. In FIG. 2, the cylinder number P_CYL is obtained in the first operation mode in which the operation designation signal CYLB_HDSEC corresponds to the logic “0” during the first time interval T1. In the second operation mode, the head number P_HD and the sector number P_SEC are obtained. The first and second time periods correspond to 33 pulses of the clock signal DIV_CLK, for example, as shown in FIG. The clock signal DIV_CLK is a clock signal for shifting data during division.

In FIG. 1, reference numeral L_AD denotes a logical sector address input from a host computer. ST_AD is preset to the start address of the zone corresponding to the logical sector address on the disk. SEC_P_CYL is preset as the number of sectors per cylinder. SEC_P_TRK is set in advance as the number of sectors per track.

First, the subtractor 10 subtracts the start address ST_AD of the corresponding zone on the disk from the input logical sector address L_AD and outputs the logical offset value L_OFS. In this state, the operation of the first operation mode is first performed during the first time interval T1 by the operation designation signal CYLB_HDSEC logic "0", followed by the second operation mode during the second time interval T2 by the operation designation signal CYLB_HDSEC logic "1". The operation is made.

First, the operation in the first operation mode will be described. At this time, the first multiplexer 12 which inputs the logical offset value L_OFS of the subtractor 10 and the remainder according to the division result of the divider 16 selects the logical offset value L_OFS by the operation designation signal CYLB_HDSEC of logic "0". To the input terminal DA of the divider 16. In addition, the second multiplexer 14 which inputs the sector number SEC_P_CYL per cylinder and the sector number SEC_P_TRK per track on the disk selects the sector number SEC_P_CYL per cylinder according to the operation designation signal CYLB_HDSEC of logic " 0 " Apply to terminal DB.

The divider 16 then loads the logical offset value L_OFS and the number of sectors per cylinder SEC_P_CYL selected by the first and second multiplexers 12 and 14, respectively, by the load signal LDB as shown in FIG. The L_OFS is divided by the number of sectors per cylinder SEC_P_CYL to output the quotient and remainder according to the result. At this time, 33 clock signals DIV_CLK as shown in FIG. 2 are used. The load signal LDB is generated twice for one input of a logical sector address. That is, the load signal LDB is generated at each start point of the first and second operation modes as shown in FIG.

The quotient is then applied to the adder 18 as a cylinder offset value CYL_OFS. The adder 18 then adds the cylinder offset value CYL_OFS to the base cylinder address CYL_BASE of the zone and outputs the cylinder number P_CYL of the physical sector address. At this time, the output of the adder 18 is latched and output to the first latch circuit 26. The first latch circuit 26 is a clock applied from the latch control circuit 32 and the AND gate 22 in the first operation mode. The output of the adder 18 is latched by the signal.

The operation in the second operation mode performed after the cylinder number P_CYL is obtained as described above will be described. At this time, the first multiplexer 12 selects the remainder according to the division result of the divider 16, that is, the remainder according to the cylinder number operation in the first operation mode by the operation designation signal CYLB_HDSEC of logic “1”. It is applied to the input terminal DA of the diffuser 16. The second multiplexer 14 selects the sector number SEC_P_TRK per track and applies it to the input terminal DB of the divider 16 by the operation designation signal CYLB_HDSEC of logic "0".

The divider 16 then loads the remainder selected by the first and second multiplexers 12 and 14 and the number of sectors per track SEC_P_TRK by the load signal LDB as shown in FIG. 2, and the remainder by the number of sectors per track SEC_P_TRK. Divide by to print the quotient and remainder according to the result. At this time, 33 clock signals DIV_CLK as shown in FIG. 2 are used.

The share is applied to the second latch circuit 28 as the head number P_HD of the physical sector address, and the rest is applied to the third latch circuit 30 as the sector number P_SEC of the physical sector address. Then, the second and third latch circuits 28 and 30 latch output the head number P_HD and the sector number P_SEC, respectively. In this case, the second and third latch circuits 28 and 30 latch the output of the divider 16 by a clock signal applied from the AND gate 24 of the latch control circuit 32 in the second operation mode.

Therefore, one logical sector address is converted into a physical sector address by the circuit of FIG.

Meanwhile, as described above, the latch control circuit 32 selectively selects the clock signal CLK as shown in FIG. 2 to the first latch circuit 26 and the second and third latch circuits 28 and 30 according to the operation designation signal CYLB_HDSEC. Is applied. The latch control circuit 32 includes an inverter 20 for inverting the operation designation signal CYLB_HDSEC, an AND gate 22 for multiplying the output of the inverter 20 with the clock signal CLK and applying it to the first latch circuit 26. And the AND gate 24 which logically multiplies the operation specifying signal CYLB_HDSEC and the clock signal CLK and applies it to the second and third latch circuits 28 and 30. Accordingly, only the first latch circuit 26 performs the latch operation at the end of the first operation mode, and only the second and third latch circuits 28 and 30 perform the latch operation at the end of the second operation mode. The clock signal CLK is generated once at the end of the first operation mode and the end of the second operation mode as shown in FIG.

Meanwhile, as shown in FIG. 3, the divider 16 includes the third multiplexer 34, the first and second shift registers 36 and 38, the subtractor 40, the NAND gate 42, and the inverter ( 44) and a serial / parallel converter 46. In FIG. 3, one of the number of pidgets input to the input terminal DA and the output of the subtractor 40 is selected by the third multiplexer 34 and loaded into the first shift register 36, and the clock signal as shown in FIG. Shift by DIV_CLK. The number of jets input to the input terminal DB is loaded into the second shift register 38 to be shifted and shifted by the clock signal DIV_CLK. The difference between the outputs of the first and second shift registers 36 and 38 is determined by the subtractor 40. At this time, if the difference between the number of jets and the number of jets determined by the subtraction of the subtractor 40 is greater than 0, the NAND gate 42 and the third multiplexer 34 transmit the new difference between the number of jets and the number of jets to the first shift register 36. The example shows a serial shift divider that loads, sets the quotient to "1", shifts the jet number by 1 bit, and repeats subtraction again. The most significant bit MSB of the output of the subtractor 40 is inverted by the inverter 44 and then applied to the serial / parallel converter 46 to be output as the quotient of parallel data, and the output of the first shift register 36 at that time is The rest.

The subtractor 40 is configured as the adder 48 and the inverter 50 as shown in FIG. That is, as the case where the input B is subtracted from the input A, the input B is inverted by the inverter 50 and then added by the adder 48 with the input A to subtract it. If this appears to be a logical formula, it is as following Formula (1).

As described above, the present invention has the advantage of improving the performance of the HDD by reducing the time required for sector address translation by converting the sector address as simple hardware.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, although the embodiment of the present invention shows an application example to the HDD employing the constant-density recording form, the same applies to the other cases. In this case, however, there is no need to distinguish the zones, so it is not necessary to use the subtractor 10 and the adder 18. The same applies to FDD as well as HDD. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalents of the claims and the claims.

Claims (8)

A sector address conversion circuit of a hard disk drive device that converts a logical sector address into a physical sector address consisting of a cylinder number, a head number, and a sector number, the first and second operation modes sequentially for one input of the logical sector address. The logical sector address is divided by the number of sectors per cylinder in the first operation mode, and the quotient is output as the cylinder number, and in the subsequent second operation mode, the remainder of the cylinder number operation is calculated. Division means for dividing by the number and outputting the quotient to the head number, and outputting the remainder to the sector number, and the rest according to the logical offset value and the cylinder number operation in order to correspond to the first and second operation modes. First selection means for selecting one by one and applying to the division means, and the number of sectors per cylinder on the disc; And second selection means for sequentially selecting one sector per track in correspondence to the first and second operation modes and applying it to the division means. 2. The track according to claim 1, wherein the division means comprises the logical sector address and the number of sectors per cylinder and the remainder from the calculation of the cylinder number and the track by a load signal generated twice for one input of the logical sector address. A sector address conversion circuit characterized by loading the number of sectors sequentially. 3. The method according to claim 2, wherein the first and second selection means sequentially designate the first and second operation modes sequentially for the same time with respect to one input of the logical sector address. And a sector address conversion circuit characterized in that the selection operation is performed. 3. The apparatus of claim 2, further comprising: latching the first latch means for latching the cylinder number output from the dividing means in the first operation mode, and latching the head number output from the dividing means in the second operation mode. A second latch means, a third latch means for latching out the sector number output from the division means in the second operation mode, at the end of the first operation mode and at the end of the second operation mode. And latch control means for sequentially providing a clock signal to the first latch means and the second and third latch means in accordance with the operation designation signal. In a sector address conversion circuit of a hard disk drive device that converts a logical sector address into a physical sector address consisting of a cylinder number, a head number, and a sector number, a logical offset value is obtained by subtracting the start address of the corresponding zone on the disk from the logical sector address. A subtracting means for outputting the sequential means, and sequentially operating in the first and second operation modes with respect to one input of the logical sector address, and in the first operation mode, dividing the logical offset value by the number of sectors per cylinder in the first operation mode. Division means for outputting an offset value, dividing the remainder according to the cylinder offset value calculation by the number of sectors per track in the subsequent second operation mode, outputting the quotient to the head number, and outputting the remainder to the sector number; In the first operation mode, the cylinder offset value of the base seal of the corresponding zone. An addition means for adding the address to the cylinder number and outputting the result to the cylinder number, and selecting the logical offset value and the rest according to the cylinder number operation one by one in order corresponding to the first and second operation modes and applying the result to the division means. And first selection means, and second selection means for sequentially selecting one sector per cylinder and one track per track on the disc in correspondence to the first and second operation modes and applying the same to the division means. Sector address conversion circuit. 6. The divider according to claim 5, wherein the dividing means further comprises the cylinder offset value and the number of sectors per cylinder and the remainder from the calculation of the cylinder number and the track by a load signal generated twice for one input of the logical sector address. A sector address conversion circuit characterized by loading the number of sectors sequentially. 7. The method according to claim 6, wherein the first and second selection means sequentially designate the first and second operation modes sequentially for the same time with respect to one input of the logical sector address. And a sector address conversion circuit characterized in that the selection operation is performed. 8. The method of claim 7, further comprising: latching the first latch means for latching the cylinder number output from the dividing means in the first operation mode, and latching the head number output from the dividing means in the second operation mode. A second latch means, a third latch means for latching out the sector number output from the division means in the second operation mode, at the end of the first operation mode and at the end of the second operation mode. And latch control means for sequentially providing a clock signal to the first latch means and the second and third latch means in accordance with the operation designation signal.