KR100240329B1 - Motion compensation appatratus for digital image - Google Patents

Abstract

The present invention relates to a motion compensation device of a digital image, and a motion compensation device of a digital image, which makes it easy to adjust the half-pixel calculation timing of a macro block using a 4-port RAM, which is relatively easy to control when using a first-in, first-out memory having a ping-pong structure. The object of the present invention is to provide a first selector for selectively outputting a pixel value of a macroblock whose half pixel value is calculated and a pixel value of the inverse discrete cosine transformed macro block; A four-port RAM configured to input and output the pixel value of the macroblock from which the half pixel value output from the first selector is calculated and the pixel value of the macroblock from the inverse discrete cosine conversion under the control of the controller; A second selector for selectively outputting a pixel value of the macroblock whose half pixel value output from the 4-port RAM and a pixel block of the inverse discrete cosine transformed pixel value; A half-pixel calculator that receives pixel values of the inverse discrete cosine transformed macroblock output from the second selector and calculates and outputs intermediate values between the pixels; And a control unit for generating input and output control signals to the respective units based on the pixel values of the inverse discrete cosine transformed macroblock.

Description

Motion Compensation Apparatus for Digital Image

The present invention relates to a motion correction apparatus for a digital image, and more particularly, to a motion correction apparatus for a digital image for simplifying control of a circuit for motion correction of a reconstructed digital image.

In general, in MPEG-II decoders, the process of restoring image information by inverse quantization of the compressed and transmitted digital image to be stretched to the original data length and then performing an inverse discrete cosine transform is essential. to be.

In addition, after performing the above process, motion correction is performed to restore original image information. In general, digital image processing is performed in units of macro blocks, and each macro block having a brightness value It consists of four 8x8 blocks.

Therefore, by calculating the half pixel value of each pixel in each 8 × 8 block unit, that is, the intermediate value between one pixel and the neighboring pixel, the image quality restored to the half pixel value thus calculated is slightly improved. do.

As shown in FIG. 1, the apparatus for correcting motion by calculating a half-pixel value includes a macroblock obtained by inverse discrete cosine transform (IDCT) and pixel values of a macroblock whose half-pixel value is calculated. A first selector 110 for selectively outputting a pixel value of? The pixel values of the macroblocks from which the half-pixel values output from the first selector 110 are calculated and the pixel values of the macroblocks subjected to inverse discrete cosine transform (IDCT) are input in a ping-pong structure in order of input. First and second first-in, first-out memory (120, 130) for outputting; A second selection for selectively outputting pixel values of the macroblock from which the half-pixel values output from the first and second first-in first-out memories 120 and 130 are calculated and pixel values of the inverse discrete cosine transformed (IDCT) macroblock; Unit 140; A half-pixel calculation unit 150 receiving pixel values of an inverse discrete cosine transform (IDCT) macro block output from the second selection unit 140 and calculating and outputting an intermediate value between each pixel; The control unit 100 generates an input / output control signal to each unit based on the pixel value of the inverse discrete cosine transform (IDCT) macroblock.

With reference to the accompanying drawings, a conventional motion compensation device for a digital image made in this way will be described in detail.

First, the controller 100 receives the pixel value of the n-th Inverse Discrete Cosine Transform (IDCT) macro block and controls the first selector 110 to store the first-in first-out memory 130 based on the pixel value. In addition, the first selector 110 is controlled so that the second first-in first-out memory 140 stores the n + 1 th Inverse Discrete Cosine transform (IDCT) pixel value in succession.

If the pixel values of the macroblocks subjected to the nth inverse discrete cosine transform (IDCT) are sequentially stored in the first-in first-out memory 130 by the selection of the first selection unit 110 by the capacity thereof, The controller 100 controls the first-in, first-out memory 130 to be sequentially output.

When the pixel value of the n-th macroblock is output from the first-in, first-out memory 120, the controller 100 controls the output of the second selector 140 so that the pixel value of the n-th macroblock is a half-pixel calculator. To be input to 150.

The half-pixel calculation unit 150 receives this and calculates a pixel value having an intermediate value between neighboring pixels as shown in FIG. 3. In general, the half-pixel calculation is performed in 8 × 8 block units. Therefore, in order to calculate half-pixels for one 8 × 8 block, half-pixels can be calculated only by reading pixels of neighboring blocks horizontally one by one, that is, by reading nine pixels horizontally.

The n-th macroblock whose half pixel value is calculated is applied to the first selection unit 110 again and stored in the second first-in first-out memory 130 under the control of the control unit 100.

When the n-th macroblock in which the half-pixel value is calculated is stored in the first-in, first-out memory 120, the controller 100 controls the first selector 110 to perform inverse discrete cosine transform (IDCT) n +. The pixel value of the first macro block may be stored in the second first-in first-out memory 130.

Subsequently, when the n-th block in which the half-pixel value stored in the first-in, first-out memory 120 is calculated is applied to the second selector 140, the controller 100 causes the second selector 140 to perform the above-mentioned operation. By controlling the output of the first-in, first-out memory 120 to be selected, the n-th block in which the half-pixel value is calculated, that is, the n-th block in which the motion is corrected, is displayed.

In addition, when the output of the first-in, first-out memory 120 is completed, the controller 100 controls the first selector 110 to store pixel values of the macroblocks subjected to n + 2th inverse discrete cosine transform (IDCT). The first first-in first-out memory 120 is controlled again.

In the above-described operation, the pixel value of the inverse discrete cosine transform (IDCT) n + 1th macroblock stored in the second first-in-first-out memory 130 is also processed by half-pixel processing.

On the other hand, a flip-flop may be used instead of a first-in, first-out memory. In this case, each flip-flop should be configured for each pixel of the macro block.

The motion compensation apparatus of the conventional digital image described above uses a first-in, first-out memory as a ping-pong structure to match the timing of half-pixel calculations, so that a control signal for each pixel value of a macro block is written and read. Control becomes difficult, and this causes a complicated configuration of the circuit.

Accordingly, in view of the above problems, the present invention provides a digital image motion compensation device that easily adjusts the half-pixel calculation timing of a macroblock using a 4-port RAM, which is relatively easy to control when using a ping-pong first-in-first-out memory. The purpose is.

1 is a block diagram showing a motion compensation apparatus of a conventional digital image.

2 is a block diagram showing a motion compensation apparatus for a digital image according to the present invention;

3 is a diagram for explaining a half-pixel for each pixel of an 8x8 block.

<Description of the code | symbol about the principal part of drawing>

200: control unit 210: first selection unit

220: 4-port RAM 230: second selector

240: half-pixel calculation unit

In order to achieve the above object, the apparatus for correcting motion of a digital image according to the present invention includes a pixel value of a macroblock in which a half-pixel value is calculated and a pixel value of a macroblock inverse discrete cosine transform (IDCT) as shown in FIG. A first selecting unit 210 for selectively outputting the control unit; Input and output the pixel value of the macroblock from which the half-pixel value output from the first selector 210 is calculated and the pixel value of the macroblock subjected to inverse discrete cosine transform (IDCT) under the control of the controller 200. 4-port RAM 220; A second selector 230 for selectively outputting pixel values of the macroblocks from which the half-pixel values output from the 4-port RAM 220 are calculated and pixel values of the macroblocks subjected to inverse discrete cosine transform (IDCT); A half-pixel calculator 240 that receives pixel values of an inverse discrete cosine transform (IDCT) macro block output from the second selector 230 and calculates and outputs an intermediate value between the pixels; The control unit 200 generates an input / output control signal to each unit based on the pixel value of the inverse discrete cosine transform (IDCT) macroblock.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, the controller 200 receives the pixel value of the nth inverse discrete cosine transform (IDCT) macroblock and controls the first selector 210 to store the 4-port RAM 220 based on the pixel value of the macroblock. In addition, the first selector 210 controls the 4-port RAM 220 to sequentially store the pixel values of the macroblocks subjected to the n + 1th Inverse Discrete Cosine Transform (IDCT).

At this time, the signal generated by the control unit 200 is an address signal and a read / write signal for controlling the input / output of the 4-port RAM instead of designating each first-in first-out memory and generating the input / output control signal thereto. .

Therefore, the 4-port RAM 220 outputs the pixel value of the n-th macroblock under the control of the controller 200, and the second selector 230 selects the half value by the control of the controller 200. Output to the pixel calculator 240.

The half-pixel calculator 240 receives this and calculates a pixel value having an intermediate value between neighboring pixels as shown in FIG. 3.

The n-th macroblock in which the half pixel value is calculated is applied to the first selector 210 again and stored in the 4-port RAM 220 under the control of the controller 200.

When the n-th macroblock in which the half-pixel value is calculated is stored in the 4-port RAM 220, the controller 200 controls the first selector 210 to perform n + 1 inverse discrete cosine transform (IDCT). The pixel value of the first macro block may be stored in the 4-port RAM 220.

Thereafter, when the n-th block in which the half-pixel value stored in the 4-port RAM is calculated is applied to the second selector 230, the controller 200 causes the second selector 230 to cause the 4-port RAM. By controlling the output of 220 to be selected, the n-th block in which the half-pixel value is calculated, that is, the n-th block in which the motion is corrected, is displayed.

In addition, when the output of the 4-port RAM 220 is completed, the controller 200 may control the first selector 210 to store the pixel value of the n + second inverse discrete cosine transform (IDCT) macro block. The four-port RAM 220 is controlled again.

In the above-described operation, the pixel value of the n + 1 macroblock subjected to inverse discrete cosine transform (IDCT) stored in the 4-port RAM 220 is also half-pixel-processed and output.

As described in detail above, the apparatus for compensating for motion of a digital image according to the present invention has an effect of easily matching the half-pixel calculation timing of a macro block using a 4-port RAM and simplifying a circuit structure.

Claims (1)

A first selector for selectively outputting pixel values of the macroblocks whose half pixel values are calculated and pixel values of the macroblocks inverse discrete cosine transformed; A four-port RAM configured to input and output the pixel value of the macroblock from which the half pixel value output from the first selector is calculated and the pixel value of the macroblock from the inverse discrete cosine conversion under the control of the controller; A second selector for selectively outputting a pixel value of the macroblock whose half pixel value output from the 4-port RAM and a pixel block of the inverse discrete cosine transformed pixel value; A half-pixel calculator that receives pixel values of the inverse discrete cosine transformed macroblock output from the second selector and calculates and outputs intermediate values between the pixels; And a control unit for generating an input / output control signal to each unit based on a pixel value of an inverse discrete cosine transformed macroblock.

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