KR100239903B1 - Method for forming metal wiring of semicondcutor device - Google Patents

Method for forming metal wiring of semicondcutor device Download PDF

Info

Publication number
KR100239903B1
KR100239903B1 KR1019970030025A KR19970030025A KR100239903B1 KR 100239903 B1 KR100239903 B1 KR 100239903B1 KR 1019970030025 A KR1019970030025 A KR 1019970030025A KR 19970030025 A KR19970030025 A KR 19970030025A KR 100239903 B1 KR100239903 B1 KR 100239903B1
Authority
KR
South Korea
Prior art keywords
plug
metal wiring
polishing
forming
metal
Prior art date
Application number
KR1019970030025A
Other languages
Korean (ko)
Other versions
KR19990005807A (en
Inventor
강준모
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR1019970030025A priority Critical patent/KR100239903B1/en
Publication of KR19990005807A publication Critical patent/KR19990005807A/en
Application granted granted Critical
Publication of KR100239903B1 publication Critical patent/KR100239903B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로서, 본 발명의 목적은 텅스텐 플러그에 의한 금속배선 형성시 전면식각이나 CMP로 표면을 평탄화할 때 플러그가 움푹패이거나 절연막이 침식되어 단락되는 결함을 방지하기 위해 플러그위에 텅스텐의 연마를 지역시키는 물질을 증착하여 균일한 연마로 표면을 평탄화시켜 다층간의 금속배선을 형성할 수 있도록 하는 반도체장치의 금속배선 형성방법을 제공함에 있다. 상기와 같은 목적을 실현하기 위한 본 발명은 플러그 형성에 의한 반도체장치의 금속배선 형성방법에 있어서, 표면의 평탄화를 위해 전면식각으로 확산방지막까지 저스트에치한 후, 확산방지막위에 금속의 연마지연을 위한 연마지연물질을 증착하고, 산성 슬러리에서 CMP하여 표면를 평탄화하여 금속배선을 형성하는 반도체장치의 금속배선 형성방법으로서 고신뢰성의 금속배선을 형성할 수 있다는 이점이 있다.The present invention relates to a method for forming a metal wiring in a semiconductor device, and an object of the present invention is to detect a defect in which a plug is pitted or an insulating film is eroded and shorted when the surface is planarized by etching or CMP when forming a metal wiring by a tungsten plug. The present invention provides a method for forming a metal wiring in a semiconductor device, by depositing a material localizing polishing of tungsten on a plug to planarize a surface by uniform polishing to form a metal wiring between layers. The present invention for achieving the above object in the method for forming a metal wiring of the semiconductor device by the plug formation, after just etching to the diffusion barrier in the entire surface etching for the planarization of the surface, for the polishing delay of the metal on the diffusion barrier As a method of forming metal wirings in a semiconductor device in which an abrasive delay material is deposited and CMP is made in an acidic slurry to planarize a surface, metal wirings can be formed with high reliability.

Description

반도체장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 텅스텐 플러그에 의한 금속배선 형성시 전면식각이나 CMP로 표면을 평탄화할 때 플러그가 움푹패이거나 절연막이 침식되어 단락되는 결함을 방지하기 위해 플러그위에 텅스텐의 연마를 지역시키는 물질을 증착하여 균일한 연마로 표면을 평탄화시켜 다층간의 금속배선을 형성할 수 있도록 하는 반도체장치의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to prevent a defect in which a plug is pitted or an insulating film is eroded when the surface is planarized by etching or CMP when forming a metal wiring by a tungsten plug. The present invention relates to a method for forming metal wiring in a semiconductor device in which a material for localizing tungsten polishing is deposited on a plug to planarize a surface by uniform polishing to form metal wiring between layers.

반도체장치가 고집적화 됨에 따라 배선의 넓이(Width) 뿐만 아니라 배선과 배선 사이의 간격(Space)도 현저하게 감소하는 추세에 있다. 더욱이 여러층의 도전층을 사용하는 반도체장치에서는 각 층에 형성된 소자와의 연결을 위해 콘택 및 비아홀을 형성하고 거기에 금속배선을 형성하게 된다.As semiconductor devices have been highly integrated, not only the width of the wiring but also the space between the wiring and the wiring have tended to decrease significantly. Furthermore, in a semiconductor device using multiple conductive layers, contacts and via holes are formed for connection with elements formed in each layer, and metal wirings are formed thereon.

도1은 종래의 방법에 의해 형성된 일반적인 비아(via) 콘택에 의한 금속배선을 나타낸 단면도이다.1 is a cross-sectional view showing a metal wiring by a general via contact formed by a conventional method.

도1에서 보는 바와 같이 금속라인을 패턴한후 금속(8) 라인간 절연체(Inter-Metal-Oxide ; IMO)를 증착한 후 금속(8)간 통로를 형성하는데 평탄화를 목적으로 유동성을 가지는 SOG(Spin On Glass), TEOS-03(Tetra-Ethyl Ortho Silicate- O3)등 여러가지 물질을 사용해 왔다.As shown in FIG. 1, after the metal lines are patterned, inter-metal insulators (IMOs) are deposited and SOGs having fluidity for the purpose of flattening are formed to form passages between the metals 8. Spin On Glass) and TEOS-03 (Tetra-Ethyl Ortho Silicate-O3) have been used.

그러나 SOG등에 함유되어 있는 수분으로 인해 콘택형성후 금속(8) 증착시 SOG의 수분이 가스화되어 금속(8)의 증착을 방해함으로서 콘택형성에 오류가 발생했을 뿐만아니라 평탄화 정도가 충분하지 못하여 스택티드 비아(Stacked Via)를 형성하는데 무리가 따랐다는 문제점이 있다.However, due to the moisture contained in the SOG, when the metal 8 is deposited after contact formation, the moisture of the SOG is gasified to prevent the metal 8 from being deposited, resulting in an error in contact formation and the degree of planarization is insufficient. There is a problem that it is difficult to form a stacked via.

이와 같은 문제점을 해결하기 위해 텅스텐 플러그(50) 형성방법을 통해 층간 연결이 이용되고 있다.In order to solve this problem, the interlayer connection is used through the tungsten plug 50 forming method.

이 텅스텐 플러그(50) 형성방법에 의한 표면 평탄화 방법에는 크게 텅스텐(40) 전면식각과 CMP(Chemical mechanical Polishing ; 화학 기계적 연마법)가 있는데 CMP의 방법을 이용하면 플러그 형상의 훼손이 적고 배선형성을 위한 식각후 잔유물(60)이 남지 않아 전면식각의 경우 보다 높은 수율을 얻는다. 또한 CMP는 이중상감처리(Dual Damascene Process)라는 금속 플러그 및 배선의 동시 형성을 가능하게 함으로 많은 각광을 받고 있으나 플러그가 리세션(recession)이나 침식(erosion) 현상은 아직 해결하지 못한 문제점이다.The surface planarization method by the tungsten plug 50 formation method includes tungsten (40) full surface etching and CMP (Chemical Mechanical Polishing), and the CMP method reduces plug shape and reduces wiring formation. After etching, the residue 60 is not left, so a higher yield is obtained in the case of full etching. In addition, CMP has received a lot of attention because it enables simultaneous formation of a metal plug and wiring called a dual damascene process, but the recession or erosion of the plug has not been solved yet.

도2는 텅스텐 플러그(50) 형성을 위해 절연막(10)에 콘택 비아홀(20)을 식각한 후 확산방지막(30)을 증착한 다음 텅스텐(40)을 증착한 상태를 나타낸 단면도이다.FIG. 2 is a cross-sectional view illustrating a state in which the contact via hole 20 is etched in the insulating film 10 to form the tungsten plug 50, the deposition barrier 30 is deposited, and the tungsten 40 is deposited.

도3은 도2와 같이 증착된 텅스텐(40)을 CMP를 하여 콘택 비아홀(20)안의 텅스텐(40)과 확산방지막(30)을 제외한 나머지 텅스텐(40)과 확산방지막(30)을 제거한 상태를 나타낸 단면도이다.FIG. 3 shows a state where the remaining tungsten 40 and the diffusion barrier 30 are removed except for the tungsten 40 and the diffusion barrier 30 in the contact via hole 20 by CMP of the deposited tungsten 40 as shown in FIG. It is sectional drawing shown.

도3을 보면 텅스텐(40)의 연마속도가 확산방지막(30)보다 빠르기 때문에 텅스텐 플러그(50)가 절연막(10)에 비해 낮게 위치한 것을 알 수 있다.3, the tungsten plug 50 is located lower than the insulating film 10 because the polishing speed of the tungsten 40 is faster than the diffusion barrier 30.

도4는 텅스텐 플러그(50)가 사이드어택트(Side Attack)에 의해 침식되는 상태를 나타낸 단면도로서 플러그 주위의 텅스텐(40)이 다 연마되고 확산방지막(30)이 연마되면서 텅스텐(40)과 확산방지막(30)의 연마속도 차이로 플러그의 리세션이 생겨나고 콘택 비아홀(20) 주위의 절연막(10)이 침식되게 된다.4 is a cross-sectional view illustrating a state in which the tungsten plug 50 is eroded by a side attack. As the tungsten 40 around the plug is polished and the diffusion barrier 30 is polished, the tungsten plug 50 is diffused with the tungsten 40. Due to the difference in the polishing rate of the barrier layer 30, the recess of the plug is generated and the insulating layer 10 around the contact via hole 20 is eroded.

도5는 텅스텐 플러그(50)의 절연막(10)이 심하게 침식된 상태를 나타낸 단면도로서 도4에서의 사이드어택트를 받아 침식될 때 SRAM과 같이 플러그의 밀도가 높은 경우에 플러그의 리세션 뿐만아니라 도4에 도시된 바와 같이 절연막(10)자체가 심하게 침식되어 단락되는 결함이 발생됨을 나타내고 있다.FIG. 5 is a cross-sectional view showing a state in which the insulating film 10 of the tungsten plug 50 is eroded badly. In addition, when the density of the plug is high, such as SRAM, when the side attack in FIG. As shown in FIG. 4, the insulation film 10 itself is severely eroded, and a short circuit defect is generated.

도6은 전면식각에 의한 텅스텐 플러그(50)의 형성상태를 나타낸 단면도로서 (a)는 저스트에치한 상태를 나타낸 단면도이고 (b)는 오버에치한 상태를 나타낸 단면도이다.6 is a cross-sectional view showing a state in which the tungsten plug 50 is formed by full etching, (a) is a cross-sectional view showing a just etched state, and (b) is a cross sectional view showing a overetched state.

도6의 (a)는 전면식각시 저스트에치(just etch)하여 텅스텐(40)을 제거한 상태로 금속잔유물(60)이 남아있다. 이 잔유뮬은 브리지를 유발시키게 된다.6 (a) shows that the metal residue 60 remains in a state in which the tungsten 40 is removed by just etching during the entire surface etching. This residual oil causes a bridge.

도6의 (b)는 저스트에치 후 발생된 금속잔유물(60)을 없애기 위해 오버에치(over etch)한 상태로 플러그가 심하게 파여 소자의 신뢰성이 저하된다는 문제점이 있다.6 (b) has a problem that the plug is severely dug in the over-etched state in order to remove the metal residue 60 generated after the just etch, thereby lowering the reliability of the device.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 다층간 금속배선을 위해 표면을 평탄화할 대 플러그 혹은 금속배선층이 확산방지막에 비해 빨리 연마되는 것을 방지하기 위해 전면식각후 CMP시 치밀한 산화막이 형성될 수 있는 연마지연물질을 증착하여 연마를 실시함으로서 균일한 연마로 평탄화하여 금속배선을 형성하는 반도체장치의 금속배선 형성방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to prevent the polishing of the plug or the metallization layer faster than the diffusion barrier layer in order to planarize the surface for the metallization between the layers. The present invention provides a method for forming a metal wiring in a semiconductor device in which a polishing delay material capable of forming a dense oxide film is deposited by CMP to perform polishing to planarize uniformly to form metal wiring.

도1은 종래 방법에 의한 일반적인 비아(via) 형성 단면도이다.1 is a cross-sectional view of a general via formation by a conventional method.

도2는 텅스텐 플러그 형성을 위해 텅스텐이 증착된 상태를 나타낸 단면도이다.2 is a cross-sectional view showing a state in which tungsten is deposited to form a tungsten plug.

도3은 텅스텐 플러그가 형성된 상태를 나타낸 단면도이다.3 is a cross-sectional view showing a state in which a tungsten plug is formed.

도4는 텅스텐 플러그가 사이드어택트에 의해 침식되는 상태를 나타낸 단면도이다.4 is a cross-sectional view showing a state in which a tungsten plug is eroded by a side attack.

도5는 텅스텐 플러그의 절연막이 침식된 상태를 나타낸 단면도이다.5 is a cross-sectional view illustrating a state in which an insulating film of a tungsten plug is eroded.

도6은 전면식각에 의한 텅스텐 플러그의 형성상태를 나타낸 단면도로서 (a)는 저스트에치한 상태를 나타낸 단면도이고 (b)는 오버에치한 상태를 나타낸 단면도이다.6 is a cross-sectional view showing a state in which a tungsten plug is formed by front etching, (a) is a cross-sectional view showing a just etched state, and (b) is a cross sectional view showing an over-etched state.

도7은 본 발명에 의한 방법에 의해 표면 평탄화를 행하는 공정을 단계적으로 나타낸 단면도이다.Fig. 7 is a cross-sectional view showing step by step of surface planarization by the method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 절연막 20 : 콘택 비아홀10 insulating film 20 contact via hole

30 : 확산방지막 40 : 텅스텐30: diffusion barrier 40: tungsten

60 : 잔유물 70 : 연마지연물질60: residue 70: abrasive delay material

상기와 같은 목적을 실현하기 위한 본 발명은 플러그 형성에 의한 반도체장치의 금속배선 형성방법에 있어서, 표면의 평탄화를 위해 전면식각으로 확산방지막까지 저스트에치한 후, 확산방지막위에 금속의 연마지연을 위한 연마지연물질을 증착하고, 산성 슬러리에서 CMP하여 표면를 평탄화하여 금속배선을 형성하는 반도체장치의 금속배선 형성방법을 제공한다.The present invention for achieving the above object in the method for forming a metal wiring of the semiconductor device by the plug formation, after just etching to the diffusion barrier in the entire surface etching for the planarization of the surface, for the polishing delay of the metal on the diffusion barrier Provided is a method for forming metal wirings in a semiconductor device in which polishing delay materials are deposited, and CMP in acidic slurry is used to planarize the surface to form metal wirings.

상기와 같은 방법에 의한 본 발명은 표면을 평탄화함에 있어 처리량이 우수한 전면식각으로 인해 발생되는 잔유물을 CMP를 이용하여 제거할 때 균일한 연마를 위해 금속부분의 연마를 지연시킬 수 있는 연마지연물질을 증착하여 균일한 연마로 리세션이나 침식이 발생되지 않고 표면을 평탄화시켜 다층구조의 금속배선을 형성할 수 있다.The present invention by the method as described above is a polishing delay material that can delay the polishing of the metal part for uniform polishing when removing the residues generated by the CMP with a good throughput in planarizing the surface using CMP It is possible to form a multi-layered metal wiring by flattening the surface without depositing or erosion by uniform polishing by deposition.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도7은 본 발명에 의한 실시예로서 표면 평탄화를 행하는 공정을 단계적으로 나타낸 단면도이다.Fig. 7 is a cross-sectional view showing the step of surface planarization step by step according to the embodiment of the present invention.

도7의 (a)는 텅스텐 플러그(50)를 형성하기 위해 절연막(10)에 콘택 비아홀(20)을 식각한 후 확산방지막(30)을 증착한 다음 CVD(Chemical Vapor Deposition ; 화학기상증착)법으로 텅스텐(40)을 증착한 상태를 나타낸 단면도이다.In FIG. 7A, the contact via hole 20 is etched into the insulating film 10 to form the tungsten plug 50, and then the diffusion barrier layer 30 is deposited, followed by CVD (Chemical Vapor Deposition) method. Is a cross-sectional view showing a state in which tungsten 40 is deposited.

본 실시예에서는 플러그(50)를 형성한 금속으로 텅스텐(40)을 사용하였으나 구리 등의 다른 금속을 사용할 수도 있다.In this embodiment, tungsten 40 is used as the metal on which the plug 50 is formed, but other metals such as copper may be used.

도7의 (b)는 도7의 (a) 결과물을 전면식각하여 플러그나 배선을 형성하는 텅스텐(40)이나 구리 등의 금속의 높이를 절연막(10) 높이 부근이 되도록 저스트에치(just etch)한 상태를 나타낸 단면도이다.FIG. 7B is just etched so that the height of the metal such as tungsten 40 or copper forming the plug or wire by etching the resultant of FIG. Is a cross-sectional view showing the state.

도7의 (b)에서 보는 바와 같이 확산방지막(30)위에는 많은 금속 잔유물(60)들이 남아있는 것을 볼 수 있다.As shown in FIG. 7B, many metal residues 60 remain on the diffusion barrier 30.

도7의 (c)는 도7의 (b)결과물에 CMP공정시 금속부분의 연마를 지연시켜 균일한 연마를 실시하기 위해 연마지연물질(70)을 증착한 상태를 나타낸 단면도이다.FIG. 7C is a cross-sectional view illustrating a state in which the abrasive retardation material 70 is deposited on the resultant product of FIG. 7B to uniformly polish the metal parts during the CMP process.

본 실시예에서는 연마지연물질(70)을 타이타늄(Ti)을 수 백Å의 두께로 증착하였다. 다른 연마지연물질(70)로 알루미늄(Al)등을 사용할 수도 있다.In this embodiment, the abrasive retardation material 70 was deposited with titanium (Ti) to a thickness of several hundred microns. As the other abrasive retardation material 70, aluminum (Al) or the like may be used.

도7의 (d)는 도7의 (c)결과물을 평탄화시키기 위해 Fe(NO3)3등과 같은 산성 슬러리(slurry)에서 CMP를 하여 평탄화한 상태를 나타낸 단면도이다.FIG. 7D is a cross-sectional view illustrating the planarized state by CMP in an acid slurry such as Fe (NO 3 ) 3 or the like to planarize the resultant product of FIG. 7C.

상기에서 사용하는 산성슬러리로 H2O2나 KlO3등을 사용할 수도 있다.As the acid slurry used above, H 2 O 2 or KlO 3 may be used.

이때 플러그 위에 증착된 연마지연물질(70)인 타이타늄(Ti)은 각각 플러그(50)를 구성하는 텅스텐(40)의 연마를 지연시킴으로서 패턴이 있는 지역과 없는 지역의 연마가 균일하게 이루어져 균일한 연마가 된 상태를 볼 수 있다.At this time, titanium (Ti), which is an abrasive retardation material 70 deposited on the plug, delays the polishing of the tungsten 40 constituting the plug 50, thereby uniformly polishing the patterned and non-patterned areas. You can see the status.

상기한 바와 같이 본 발명은 처리량이 우수한 전면식각 방법과 신뢰도가 높은 CMP 방법을 적절히 구성하여 전면식각후 연마를 지연시킬 수 있는 연마지연물질을 증착하여 처리량을 크게 저하시키지 않으면서 리세션이나 침식을 극소화시킴으로서 소자의 신뢰성을 향상시킨다는 이점이 있다.As described above, according to the present invention, the surface etching method having a high throughput and the CMP method having high reliability are properly configured to deposit a polishing delay material that can delay polishing after the surface etching, thereby minimizing recession or erosion without significantly reducing the throughput. This has the advantage of improving the reliability of the device.

또한 1 Giga 이상의 DRAM 및 0.35㎛ 이하의 회로 선폭을 갖는 ASIC 및 마이크로프로세서등에서 고신뢰성 콘택 및 비아 플러그를 형성하는 금속배선을 형성할 수 있다는 이점이 있다.In addition, an ASIC and a microprocessor having a DRAM of 1 Giga or more and a circuit line width of 0.35 µm or less have an advantage of forming a metal wiring forming high reliability contacts and via plugs.

Claims (4)

플러그 형성에 의한 반도체장치의 금속배선 형성방법에 있어서, 표면의 평탄화를 위해 전면식각으로 확산방지막까지 저스트에치한 후, 확산방지막위에 금속의 연마지연을 위한 연마지연물질을 증착하고, 산성 슬러리에서 CMP하여 표면를 평탄화하여 금속배선을 형성하는 것을 특징으로 한 반도체장치의 금속배선 형성방법.In the method of forming a metal wiring of a semiconductor device by the formation of a plug, in order to planarize the surface, the surface is etched to the diffusion barrier layer by the entire surface etching, and then a polishing delay material for the polishing delay of the metal is deposited on the diffusion barrier layer, and the CMP in the acid slurry. Forming a metal wiring by planarizing the surface to form a metal wiring. 제1항에 있어서, 상기 연마지연물질은 타이타늄인 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the polishing retardation material is titanium. 제1항에 있어서, 상기 연마지연물질은 알루미늄인 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the polishing retardation material is aluminum. 제1항에 있어서, 상기 산성 슬러리는 Fe(NO3)3,H2O2,KlO3로 구성된 군으로부터 선택된 어느 하나인 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 1, wherein the acidic slurry is any one selected from the group consisting of Fe (NO 3 ) 3, H 2 O 2, and KlO 3 .
KR1019970030025A 1997-06-30 1997-06-30 Method for forming metal wiring of semicondcutor device KR100239903B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970030025A KR100239903B1 (en) 1997-06-30 1997-06-30 Method for forming metal wiring of semicondcutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970030025A KR100239903B1 (en) 1997-06-30 1997-06-30 Method for forming metal wiring of semicondcutor device

Publications (2)

Publication Number Publication Date
KR19990005807A KR19990005807A (en) 1999-01-25
KR100239903B1 true KR100239903B1 (en) 2000-01-15

Family

ID=19512875

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970030025A KR100239903B1 (en) 1997-06-30 1997-06-30 Method for forming metal wiring of semicondcutor device

Country Status (1)

Country Link
KR (1) KR100239903B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546133B1 (en) * 2002-07-19 2006-01-24 주식회사 하이닉스반도체 Method of forming a semiconductor device

Also Published As

Publication number Publication date
KR19990005807A (en) 1999-01-25

Similar Documents

Publication Publication Date Title
US5935868A (en) Interconnect structure and method to achieve unlanded vias for low dielectric constant materials
JP4266502B2 (en) Method for treating the surface of a copper dual damascene structure on a surface of a semiconductor substrate
US7727888B2 (en) Interconnect structure and method for forming the same
US20070032062A1 (en) Methods of Forming Dual-Damascene Metal Wiring Patterns for Integrated Circuit Devices and Wiring Patterns Formed Thereby
US6503827B1 (en) Method of reducing planarization defects
US7074716B2 (en) Method of manufacturing a semiconductor device
US6297158B1 (en) Stress management of barrier metal for resolving CU line corrosion
US6403466B1 (en) Post-CMP-Cu deposition and CMP to eliminate surface voids
US6194307B1 (en) Elimination of copper line damages for damascene process
KR100239903B1 (en) Method for forming metal wiring of semicondcutor device
WO2002041391A2 (en) Amorphized barrier layer for integrated circuit interconnects
US6413869B1 (en) Dielectric protected chemical-mechanical polishing in integrated circuit interconnects
US20020127849A1 (en) Method of manufacturing dual damascene structure
KR100396878B1 (en) Method of forming metal interconnection using plating and semiconductor device manufactured by the method
US6500753B2 (en) Method to reduce the damages of copper lines
KR100538380B1 (en) Method of forming metal wiring in semiconductor device
US20030085443A1 (en) Semiconductor devices and methods for manufacturing the same
KR20010058209A (en) Method of forming metal line with dual damascene process
US8048799B2 (en) Method for forming copper wiring in semiconductor device
KR100289672B1 (en) Metallization of Self-arranged Unlanded Vias
KR100321156B1 (en) Method for forming metal interconnection line of semiconductor device
KR0171977B1 (en) Method of manufacturing semiconductor device
KR100788064B1 (en) Insitu diffusion barrier and copper metallization for improving reliability of semiconductor devices
KR100546296B1 (en) Method of manufacturing metal line preventing metal bridge for semiconductor device
GB2323704A (en) Multilevel interconnects for semiconductors

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050923

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee