KR100239702B1 - Linear fifo memory - Google Patents

Abstract

The present invention relates to a linear first-in first-out memory, and more particularly, to an apparatus and a method for replacing a conventional address generator and a state signal generator with a ring counter and replacing a decoder portion of a dual- And a linear first-in-first-out memory. When the corresponding word line signal of the word line signals WLO to WLn is activated, the present invention sequentially stores the input data in the area of the corresponding word line in synchronization with the clock (CLK), and when the read enable signal RE is activated A data storage unit 210 for sequentially outputting the storage data in accordance with a clock CLK and a data storage unit 210 for outputting the data stored in the data storage unit 210 according to a clock CLK when a read enable signal RE or a write enable signal WE is active. A data input / output control unit 220 which outputs status signals (FULL, Almost-FULL, Almost-EMPTY, and EMPYT) of the word line signals 210 and simultaneously outputs the word line signals WLO to WLn-1 to the data storage unit 210, .

Description

Linear first-in-first-out memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out memory, and more particularly to a linear first-in-first-out memory in which a circuit is configured to be simple and regular.

FIG. 1 is a block diagram of a first-in first-out memory using a general dual port memory. As shown in FIG. 1, when a write enable signal WE is active, data is stored in an area designated by a write address WADDR, A dual port memory 10 for outputting data of an area designated by the read address RADER when the write enable signal WE is active; An address generator 120 for generating an n-bit read address RADDR by counting the clock CLK when the read enable signal RE is active, And a status signal generator 130 for receiving the data WADDR (RADDR) and determining the data storage state of the dual port memory 110.

When the write enable signal WE or the read enable signal RE is active, the address generating unit 120 counts the clock and outputs the write coefficient enable signal WCE or the read coefficient enable signal RCE A write counter 123 for increasing a write pointer and outputting a write address WADDR when a write coefficient enable signal WCE of the coefficient enable generator 121 is active, And a read counter 122 for increasing the read pointer and outputting the read address RADDR when the read coefficient enable signal RCE of the coefficient enable generator 121 is activated.

The status signal generator 130 compares the output signals WADDR and RADDR of the address generator 120 to determine the state of the dual pod memory 110 (EMPTY, Almost-EMPTY, Almost-FULL, and FULL) .

The operation of the conventional art will be described as follows.

First, when the write mode of the first-in first-out memory is set to be inactive after the reset signal RST is inactive, the address generator 120 generates the count enable controller 121 when the write enable signal WE is active, The write counter enable signal WCE is activated in synchronization with the write enable signal WCE and the write counter 123 generates the address WADDR of n bits by inputting the write enable signal WCE.

Accordingly, the dual port memory 110 enabled by the write enable signal WE stores the input data in the area designated by the write address WADDR.

Thereafter, when the write enable signal WE is inactive and then active, the address generating unit 120 activates the write enable signal WCE again and sets the write enable signal (WCE) The write counter 123 receiving the write address WCE generates the write address WADDR by incrementing the write pointer by "1 ".

Accordingly, the dual port memory 110 stores the input data in the area designated by the write address WADDR generated by the address generator 120. [

If the read mode of the first-in first-out memory is set, the address generator 120 causes the count enable controller 121 to activate the read count enable signal RCE in synchronization with the clock CLK, The read counter 122 receiving the signal RCE generates the n-bit read address RADDR.

Accordingly, the dual port memory 110 enabled to the read enable signal RE outputs the data stored in the area designated by the read address RADDR.

Thereafter, when the read enable signal RE is inactive and then active, the address generating unit 120 activates the count enable signal 121 again to activate the read count enable signal RCE, The read counter 122 receiving the RCE generates the read address RADDR by incrementing the read pointer by "1 ".

Accordingly, the dual port memory 110 outputs the data stored in the area designated by the read address RADDR generated by the address generator 120.

The read / write operation as described above may occur simultaneously.

When performing the read / write operation as described above, the status signal generator 130 compares the read / write address EADDR (WADDR) generated by the address generator 120 with the size of the read / write address EADDR The state of the display unit 110 is determined.

That is, if the comparison result is "0", EMPTY, "1", Almost-EMPTY, and if the size of the first-in first-out memory is "n", the comparison result is FULL, And outputs a signal FULL.

In the above case, when a read / write operation occurs at the same time, a value obtained by subtracting the read address RADDR from the write address WADDR is a comparison result.

However, the operating characteristics of first-in-first-out (FIFO) memories are different from dual-port memories.

Therefore, the prior art has a disadvantage in that the circuit configuration is complicated and the regularity in the circuit configuration is lowered by constructing the first-in first-out memory by adding the address generator and the state signal generator as the case of using the dual port memory.

This prior art is not suitable for a lay-out generation tool such as a data-path compiler (data-compiler).

If the operation structure of the dual port memory is a ring-buffer, if the first-in first-out memory is changed to a linear-buffer structure, the control portion of the first-in first-out memory becomes simple and regularly changed, It can be easily applied to a data-path compiler, which is a generation technique.

Therefore, in order to solve the disadvantages of the related art, the present invention replaces the existing address generator and the state signal generator with the ring counter, and substitutes a single ring counter for the decoder portion of the dual port memory, And a linear first-in-first-out memory.

1 is a block diagram of a first-in first-out memory using a conventional dual-port memory.

2 is a block diagram of a linear first-in-first-out memory of the present invention.

3 is a timing chart in the present invention.

4 is a detailed circuit diagram of the present invention.

5 is a detailed circuit diagram of a memory cell in FIG.

6 and 7 are detailed circuit diagrams of the ring counter in Fig.

8 is an exemplary diagram showing the operation of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

210: Data storage unit 220: Data input / output control unit

221: control signal generator 222: status signal generator

223: Word line selector Co ~ Cn: Ring counter

Bo, o ~ B _{n-1, n-1} : memory cell

As shown in the block diagram of FIG. 2 and FIG. 4, when the corresponding word line signal of the word line signals WLO to WLn is activated, the embodiment of the present invention synchronizes with the clock CLK to input A data storage unit 210 for sequentially storing data and sequentially outputting the stored data in response to a clock CLK when the read enable signal RE is activated, a read enable signal RE or a write enable signal RE, (FULL, Almost-FULL, Almost-EMPTY, and EMPYT) of the data storage unit 210 according to the clock CLK and simultaneously outputs the word line signals WLO to WLn-1 And a data input / output control unit 220 for outputting the data to the data storage unit 210.

The data storage unit 210 includes memory cells (BO, 0 to Bn-1, 0 to BO, n-1 to Bn-1, n-1) in which a clock CLK and a read- 0 to BOn, 0 to Bn-1, n-1 to BO, n-1) are connected to the input terminals DN of the memory cells Bn- 1 to Bn-1, 0 to Bn-1, and n-1) are sequentially connected in series to the input terminal DS of the next stage, and the output terminals Q of the memory cells And the word line signals WLO to WLn-1 of the data input / output control unit 220 are commonly connected to the input terminals DS of the memory cells Bn-1, 0 to Bn-1, 0 ', and data is outputted from the output terminals of the memory cells B0, 0 to B0, and n-1.

As shown in FIG. 5, the memory cells B0,0 to Bn-1, n-1 include a NAND gate 212 for transferring a write enable signal WE and an input signal DN, A NAND gate 213 for inverting an inverted signal of the enable signal WE and an input signal DS and a read enable signal RE and a NAND gate 213 for inputting a read enable signal RE and an inverted output signal QN A NAND gate 214 for outputting the output signals of the O gate 211 and the first and second NAND gates 212 and 213 and a NAND gate 214 for outputting a clock signal CLK And a D flip-flop 215 for latching the output signal of the NAND gate 214 in synchronization with each other and outputting a non-inverted output signal Q and an inverted output signal QN.

The data input / output control unit 220 generates a control signal for generating a read coefficient enable signal RCE or a write coefficient enable signal WCE by logically combining a read enable signal RE and a write enable signal WE, Almost-FULL, Almost-EMPTY, and EMPYT) of the data storage unit 210 by performing an arithmetic operation according to the output signal RCE (WCE) of the control signal 221, And outputs the word line signals WLO to WLn-1 to the data storage unit 210. The state-signal generator 222 outputs the n-bit output signals of the state signal generator 222 and the write enable signal WE, And a word line selector 223 for outputting the word line selector 223.

The control signal generator 221 includes an AND gate 221-1 for outputting a lead coefficient enable signal RCE by logically multiplying the inverted signal of the write enable signal WE and the read enable signal RE, And an AND gate 221-2 for logically multiplying the inverted signal of the enable signal RE and the write enable signal WE and outputting the write coefficient enable signal WCE.

The state signal generator 222 applies the output signal RCE (WCE) and the clock signal CLK of the control signal generator 221 to (n + 1) ring counters CO to Cn in common, A signal '0' is applied to the input terminal INC of the ring counter Cn and a signal '0' is applied to the input terminal DEC of the ring counter Cn, and the output terminals Qn To Q1 of the ring counters CO to Cn-1 are connected to the input terminals DEC of the ring counters Cn-1 to Cn-1, respectively, and the output terminals Q0 to Qn- Qn-1, and Qn of the ring counters CO, C1, Cn-1, and Cn are connected to the input terminals INC of the switches C1 to Cn, -EMPTY, Almost-FULL and FULL) and outputs the output signals (Q0 to Qn-1) of the ring counters CO to Cn-1 to the word line selector 223.

6, the ring counter Co includes a NAND gate 242 for nailing a write coefficient enable signal WCE and an input signal INC, a NAND gate 242 for inputting a read coefficient enable signal RCE, An OR gate 241 for performing a logical AND operation on the NAND gate 243 for outputting the read enable signal RCE (WD), the write enable signal RCE (WCE) and the inverted output signal (QN) A NAND gate 244 for NANDing the output signals of the NAND gates 242 and 243 and a reset signal RST applied to the set terminal SET for output of the NAND gate 244 And a D flip-flop 245 for latching the signal and outputting the non-inverted output signal Q and the inverted output signal QN.

7, the ring counter C ₁ to Cn includes a NAND gate 252 for nailing a write coefficient enable signal WCE and an input signal INC, a read count enable signal RCE, An OR gate 251 for performing a logical AND operation on the NAND gate 253 for nANDing the input signal DEC and the read and write coefficient enable signal RCE (WCE) and the inverted output signal QN, A reset signal RST is applied to the clear terminal CLEAR and a reset signal RST is applied to the NAND gate 254 and the NAND gate 254 according to the clock CLK, And a D flip-flop 255 for latching the output signal of the non-inverted output signal Q and outputting the inverted output signal QN.

The word line selector 223 performs logical multiplication of the write enable signal WE and the output signals Q0 to Qn-1 of the status signal generator 222 to output the word line signals WLO to WLn-1, respectively n AND gates (AN ₀ to ANn- ₁ ).

The operation and effect of the present invention will be described as follows.

When the reset signal RST is initialized by the reset signal RST, the data input / output control unit 220 sets the output value of the ring counter CO to '1' in the state signal generator 222 and the output value of the remaining ring counters C1 to Cn to ' 0 '.

In the above, the output values of the ring counters C0 to Cn designate a storage position of data when a write occurs.

Here, since the output value Qo of the ring counter Co is '1', it indicates that the state of the data storage unit 210 is 'EMPTY'.

When the data (Do ~ D _n-1 ) is input and only the write enable signal WE is active, the AND gate AN ₁ of the word line selector 223 in the data input / output control unit 220 is activated by the state signal generator 222 And outputs the word line signal WLo as '1', as shown in FIG. 5B. The output enable signal WE is '1'.

At this time, the data storage unit 210 selects the memory cells Bo, o ~ Bo, n-1.

Accordingly, the data of the input terminals Do ~ Dn- ₁ are input to the input terminals DN of the memory cells Bo, o ~ Bo, n- ₁ at the rising edge of the clock CLK.

Since the write enable signal WE is in the active state of '1', the data input / output control unit 220 sets the output signal WCE of the AND gate 221-2 to '1' in the control signal generator 221 And is input to the status signal generator 222.

Accordingly, the state signal generator 222 latches only the output signal Q ₁ of the ring counter C ₁ to '1' because the ring counter Co to Cn latches the signal of the input terminal INC to the output terminal Q, .

Here, since the output value Q ₀ of the ring counter C ₁ is '1', it indicates that the state of the data storage unit 210 is 'Almost-EMPTY'.

Thereafter, the write enable signal WE and the read enable signal RE are activated so that the next data is stored in the input terminals Do ~ Dn-1, and the write enable signal WE and the read enable signal RE) is inactive.

At this time, if the write enable signal WE and the read enable signal RE are simultaneously activated, there is no change in the ring counters CO to Cn of the state signal generator 222.

Thereafter, when only the write enable signal WE is active, the data input / output unit 220 outputs the output signal Q ₀ (1) of the state signal generator 222 to the AND gate (AN ₂ ) of the word line selector 223, ) And the write enable signal WE of '1' to output the word line signal WLo as '1'

At this time, the data storage unit 210 selects the memory cells B ₁ , 0 to B _{1, n-1} .

Accordingly, the data of the input terminals D ₀ to D _n-1 are input to the input terminals DN of the memory cells B ₁ , 0 to B _{1, n-1} at the rising edge of the clock CLK _, do.

Performing a storage operation of the data, only the write enable signal (WE) is a "1" in the above, and the write enable signal (WE) and read enable signal (RE) all of which are '1' input terminals (D ₀ ~ D _n-1), a new data input to, and then, only the write enable signal (WE) and read enable signal (rE) is after all is inactive "0" again in the write enable signal (WE), 1 'And performs a process of storing data repeatedly.

Accordingly, when the output signal Q _n-1 of the status signal generator 222 becomes '1' by repeating the above process, the data storage unit 210 shows 'Almost-FULL' state.

Thereafter, the write enable signal WE and the read enable signal RE are activated so that the next data is stored in the input terminals D ₀ to D _n-1 , and the write enable signal WE and the read enable The signal RE is inactive.

Thereafter, when only the write enable signal WE is active, the word line generator 223 outputs the output signal WL _n-1 of the AND gate AN _n-1 to '1' The memory cells B _{n-1, 0} to B _{n-1, n-1} are selected. In this way, the memory cell at the rising edge of the clock _{(CLK) (Bn- 1, o} ~ Bn- 1, n- 1) is the input data of the input terminal (DN) to the input terminals _{(D 0 ~ D n-1} ) of And stored.

Since the write enable signal WE is in the active state of '1', the data input / output control unit 220 sets the output signal WCE of the AND gate 221-2 to '1' in the control signal generator 221 And is input to the status signal generator 222.

Accordingly, the state signal generator 222 latches the output signal Qn of the ring counter Cn to '1' because the ring counter C ₀ to C _n latches the signal of the input terminal INC to the output terminal Q, .

Here, since the output value Qn of the ring counter Cn is '1', it indicates that the state of the data storage unit 210 is 'FULL'.

The memory cells B _0,0 to B _n-1,0 to B _{0, n-1} to B _{n-1, n-1} are configured as shown in FIG.

Accordingly, only the write enable signal WE is activated to '1' during the write operation, so that the output signals of the OR gate 211 and the NAND gate 213 become '1' and the output value of the NAND gate 212 becomes the input signal DN), and the output value of the NAND gate 214 is determined by the output value of the NAND gate 212.

For example, if the input data is '1', the output signal of the NAND gate 212 becomes '0' and the output signal of the NAND gate 214 becomes '1'.

Therefore, the D flip-flop 215 latches the output signal of the NAND gate 214 at the rising edge of the clock CLK to store the input data DN.

The ring counter Co is configured as shown in FIG. 6, and the ring counters C ₁ to C _n are configured as shown in FIG.

Accordingly, when the reset signal RST is activated to '0', the ring counter Co outputs a signal of '1' to the D flip-flop 245, and the ring counters C ₁ to C _n , Flop 255 is reset to output a signal of " 0 ".

Then, when the write enable signal WE is activated to '1' for a write operation, only the write coefficient enable signal WCE is activated to '1', so that the ring counter Co receives the OR gate 241 and the NAND gate The output signal of the NAND gate 242 becomes '1', and the output value of the NAND gate 242 is determined by the input signal INC.

At this time, since the input signal INC is '0', the output value of the NAND gate 242 becomes '1' and the output values of the OR gate 241 and the NAND gates 242 and 243 are '1' And the output value of the adder 244 becomes '0'.

Accordingly, the D flip-flop 245 latches the output signal of '0' of the NAND gate 244 at the rising edge of the clock signal CLK so that a signal of '0' is outputted to the non-inverted output terminal Q, And outputs a signal of '1' to the terminal QN.

Therefore, the ring counter Co initially outputs a signal of '1' and then continuously outputs a signal of '0' during a write operation.

Since only the write coefficient enable signal WCE is' 1 ', the output signals of the OR gate 251 and the NAND gate 253 become' 1 ', and each of the ring counters C ₁ to C _n becomes' The output value is determined by the input signal INC.

Since the output value of the NAND gate 252 is determined by the input signal INC and the output values of the OR gate 251 and the NAND gate 253 are both '1', the output value of the NAND gate 254 is' (252).

Thus, the D flip-flop 255 latches the output signal of the NAND gate 254 at the rising edge of the clock (CLK).

Therefore, every time the write coefficient enable signal WCE becomes '1', the ring counter C ₁ to C _n receives the output signal of the lower ring counter. Therefore, the output of the initial ring counter Co '1' The signal is shifted to the left to indicate the state of the data storage unit 210.

Conversely, the read operation will be described as follows.

Here, the read operation will be described on the assumption that the data storage unit 210 is in the 'FULL' state.

First, only the read enable signal RE is active, and the data storage unit 210 stores the data of the memory cells B _n-1 to B _0,0 to B _{n-1, n-1} to B _{0, n -1} ) perform a shift operation to the right, and the stored data of the memory cells B _0,0- to B _{0, n-1} are output.

In the memory cells B _n-1 to B _0,0 to B _{n-1, n-1} to B _{0, n-1} , the storage data of the previous stage memory cells are shifted and stored.

For example, data stored in the memory cells (B _1,0 -B _{1, n-1} ) are shifted and stored in the memory cells (B _0,0 to B _{0, n-1} ).

At this time, '0' is inputted and stored in the input terminal DS of the memory cells B _n-1,0 to B _{n-1, n-1} .

Since the read enable signal RE is active at '1', the output signal of the AND gate 221-1 of the control signal generator 221 in the data input / output control unit 220 becomes '1'.

Accordingly, the state signal generator 222 is a ring counter _(n C ~ C ₀₎ performs the shift operation, because the ring counter (C _n) of "1" output signal (Qn) of the counter ring (C _{n- 1} ) latches and the state of the data storage unit 210 is 'Almost-FULL'.

The ring counter C _n latches the '0' signal applied to the input terminal DEC.

Thereafter, both the read enable signal RE and the write enable signal WE are activated to "0".

When only the read enable signal RE is active, the data storage unit 210 stores the data in the memory cells B _n-1 to B _0,0 to B _{n-1, n-1} to B _{0, n- 1} ) perform the shift operation to the right, and the stored data of the memory cells B _0,0 to B _{0, n-1} are output.

The memory cells B _n-1,0 to B _0,0 to B _{n-1, n-1} to B _{0, n-1} store the storage data of the previous _stage memory cells by the shift operation do.

At this time, the memory cell _{(Bn- 1, o ~ Bn- 1} , n-1) input terminals (DS) is stored is 'O' is input, the memory cells _{(Bn- 2, o ~ Bn- 2} , the n -1), 'O' signals stored in the memory cells Bn- ₁ , o to Bn- ₁ , n- ₁ are shifted and stored.

Since the read enable signal RE is active at '1', the output signal of the AND gate 221-1 of the control signal generator 221 in the data input / output control unit 220 becomes '1'.

Accordingly, the state signal generator 222 shifts the output signal Q _n-1 of '1' of the ring counter C _n-1 because the ring counter C _n to C ₀ performs the shift operation The output signal Q _{n-2 of} the ring counter C _n-2 becomes '1'.

At this time, a '0' signal shifted by the ring counter Cn is latched in the ring counter (C _n-1 ).

That is, each time the read enable signal RE is activated, the memory cells B _n-1,0 to B _0,0 to B _{n-1, n-1} to B _{0, n-1)} are each performing a shift operation to save the output data and at the same time, the data input-output control unit 220 is a state signal generator 222 is a ring counter (C _n ~ C ₀₎ have to perform a shift operation of the data storage unit in the The state of the display unit 210 is displayed.

Accordingly, when the output signal Q ₁ of the ring counter C ₁ becomes '1' in the state signal generator 222 due to the repetition of the read enable signal RE as described above, the state of the data storage unit 210 Is 'Almost-EMPTY', and the data storage unit 210 stores data only in the memory cells B _0,0 to B _{0 and n-1} .

Thereafter, when the read enable signal RE is inactive and active, data is output from the memory cells B _0,0 to B _{0, n-1 of} the data storage unit 210.

Accordingly, '0' is stored in all of the memory cells (B _n-1,0 to B _0,0 ) to (B _{n-1, n-1} to B _{0, n-1} ).

At this time, the data status signal generator 222 of the input-output control unit 220 is '1' of the ring counter (C1) signal is shifted to the ring counter (C _o) exhibits that the data storage unit 210 is "EMPTY" status do.

In the memory cells (Bo, o to Bn- ₁ , o) to (Bo, n- _{1 to} Bn- ₁ , n- ₁ ) configured as shown in FIG. 5, only the read enable signal RE, 1 ', the output signal of the NAND gate 213 is determined by the input signal DS, and the output signal of the NAND gate 214 is set to' 1 ', so that the output signal of the OR gate 211 and the NAND gate 212 is always' The output value of the NAND gate 212 is determined by the output value of the NAND gate 212.

For example, if the input data is '1', the output signal of the NAND gate 213 becomes '0' and the output signal of the NAND gate 214 becomes '1'.

Thus, the D flip-flop 215 latches the output signal of the NAND gate 214 at the rising edge of the clock CLK to store the input data DN.

Therefore, in the read operation, the memory cells B _n-1 to B _0,0 to B _{n-1, n-1} to B _{0, n-1} perform the right shift operation, The output data of the previous stage memory cell is latched and transferred to the right whenever RE is activated.

The ring counter C _o is configured as shown in FIG. 6, and the ring counters C ₁ to C _n are configured as shown in FIG.

The output signal of the OR gate 241 and the output signal of the NAND gate 242 become '1' and the output value of the NAND gate 242 is determined by the input signal DEC.

Since the input signal DEC is the output signal Q ₁ of the ring counter C ₁ , the output value of the NAND gate 242 is '0' until the data storage unit 210 becomes 'Almost-EMPTY' And the output value of the NAND gate 244 is '1' because the output values of the OR gate 241 and the NAND gates 242 and 243 are all '1'.

Accordingly, the D flip-flop 245 latches the output signal '1' of the NAND gate 244 at the rising edge of the clock CLK, 1 'to the non-inverting output terminal Q and outputs a signal of' 0 'to the inverting terminal QN until the -EMPTY state is reached.

Since only the read count enable signal RCE is' 1 ', the output signals of the OR gate 251 and the NAND gate 252 become' 1 ', and each of the ring counters C ₁ to C _n becomes' The output value of the adder 253 is determined by the input signal DEC.

Since the output value of the NAND gate 253 is determined by the input signal DEC and the output value of the OR gate 251 and the NAND gate 252 is always' 1 ', the output value of the NAND gate 254 is' (253).

Thus, the D flip-flop 255 latches the output signal of the NAND gate 254 at the rising edge of the clock (CLK).

That is, the ring counters C ₁ to C _n perform a right shift operation.

The ring counter C _n shifts the '0' value of the input terminal DEC to the right every time the read coefficient enable signal RCE is activated.

Therefore, when the ring counter (C ₁ to C _n ) of the state signal generator 222 outputs a signal of '1' as the data storage unit 210 is 'FULL' state, for example, The output signals of the ring counters C ₁ to C _n sequentially become '0' each time the read count enable signal RCE is activated.

Thereafter, when the output signal Q1 of the ring counter C ₁ becomes '0', the state of the data storage unit 210 is 'Almost-EMPTY'.

The above-described write and read operations are performed in the same manner as the timing of FIG.

For example, as shown in the example of FIG. 8, when the write enable signal WE is 4 * 4, the data is stored and the data storage state is indicated every time the write enable signal WE is activated. Whenever data is stored, it shows the state of the remaining data.

As described in detail above, the present invention not only replaces the existing address generator and state signal generator with a ring counter, but also replaces two decoder portions of the dual port memory with one ring counter, So that it is easy to expand.

Claims (7)

When the corresponding word line signal of the (corrected) word line signals WLO to WLn is activated, the input data is sequentially stored in the area of the corresponding word line in synchronization with the clock CLK, and when the read enable signal RE is active, (RCE) or a write coefficient enable signal (RCE) by logically combining a read enable signal (RE) or a write enable signal (WE) in a data storage unit for sequentially outputting the storage data in accordance with a clock signal (CLK) (FULL, Almost-FULL, Almost-EMPTY, and EMPYT) of the data storage unit by performing a calculation operation according to an output signal (RCE) (WCE) of the control signal generator, (WLO to WLn-1) to the data storage unit by logically multiplying the n-bit output signals (Q0 to Qn-1) of the status signal generator and the write enable signal (WE) ) Linear first-in-first-out memory, characterized in that it consists of a de-line selector. The data storage unit of claim 1, wherein the data storage unit includes memory cells (BO, 0 to Bn-1, 0 to BO, n-1 to Bn-1, n- 0 to BOn, 0 to Bn-1, n-1 to BO, n-1) are connected to the input terminals DN of the memory cells Bn- 1 to Bn-1, 0 to Bn-1, and n-1) are sequentially connected in series to the input terminal DS of the next stage, and the output terminals Q of the memory cells 0) to the input terminals DS of the memory cells Bn-1, 0 to Bn-1, n-1, respectively, to the word line signals WLO to WLn-1 of the data input / And the data is outputted from an output terminal of the memory cell (B0,0 to B0, n-1). The memory cell according to claim 2, wherein the memory cells (B0,0 to Bn-1, n-1) include a first NAND gate for nailing the write enable signal (WE) and the input signal (DN) A second NAND gate for inverting the output signal of the inverter, the input signal DS and the read enable signal RE, and a read / write enable signal RE (WE) and an inverted output A third NAND gate for outputting an output signal of the OR gate and an output signal of the first and second NAND gates and a third NAND gate for outputting an output signal of the third NAND gate in synchronization with a clock (CLK) And a D flip-flop for latching an output signal of the D flip-flop and outputting a non-inverted output signal (Q) and an inverted output signal (QN), respectively. The control signal generator according to claim 1, wherein the control signal generator comprises: a first inverter for inverting a write enable signal (WE); and a second inverter for inverting the read enable signal (RECE) by logically multiplying the output signal of the first inverter and the read enable signal And a second AND gate for outputting a write enable signal WE by logically multiplying the read enable signal RE by a first AND gate for outputting a write enable signal WE. The system according to claim 1, wherein the state signal generator applies the output signal RCE (WCE) and the clock (CLK) of the control signal generator to (n + 1) ring counters (CO to Cn) A signal '0' is applied to the input terminal INC of the ring counter Cn and a signal '0' is applied to the input terminal DEC of the ring counter Cn, Q1 of the ring counters CO to Cn-1 are connected to the input terminals DEC of the ring counters Cn-1 to C0n and the output terminals QO to Qn-1 of the ring counters CO to Cn- Cn are respectively connected to the input terminals INC of the ring counters CO, C1, Cn-1 and Cn and the status signals EMPTY, Almost- EMPTY, Almost-FULL and FULL) and outputs the output signals (Q0 to Qn-1) of the ring counters (CO to Cn-1) to the word line selector (223) First in first out memory. The ring counter (CO) according to claim 5, wherein the ring counter (CO) comprises a first NAND gate for nailing a write coefficient enable signal (WCE) and an input signal (INC) A first OR gate for performing a logical AND between a first NAND gate and a second NAND gate for performing a nANDing operation, a read / write coefficient enable signal (RCE) (WCE) and an inverted output signal (QN) A third NAND gate for latching the output signal of the second NAND gate and a reset signal RST applied to the set terminal SET to latch the output signal of the third NAND gate according to the clock CLK, And a first D flip flop for outputting a signal Q and an inverted output signal QN and the ring counters C1 to Cn are constituted by a fourth coefficient generator for generating a write coefficient enable signal WCE and an input signal INC, A fifth NAND gate for nANDing the NAND gate, the read count enable signal RCE and the input signal DEC, A second OR gate for performing an OR operation on a write enable signal RCE (WCE) and an inverted output signal (QN), and an output signal of the second O gate and an output signal of the fourth and fifth NAND gates A sixth NAND gate for latching the output signal of the sixth NAND gate and a reset signal RST applied to the clear terminal CLEAR to latch the output signal of the sixth NAND gate according to the clock CLK, And a second D flip-flop for outputting the first D flip-flop (QN). The method of claim 1, wherein the word line selector logic-multiplies the write enable signal (WE) and the output signal (Q0 to Qn-1) of the status signal generator to generate word line signals (WL0 to WLn- And the n first AND gates (AN0 to ANn-1) outputting the first AND gate.