KR100239288B1 - Interleaver and deinterleaver of atm cell - Google Patents

Abstract

The present invention provides an ATM cell transmitter for transmitting an Asynchronous Cell (ATM) cell using a radio channel, and inserts bits of an ATM cell header into a payload at regular intervals, and restores the original ATM cell. The interleaver and deinterleaver of an ATM cell are provided. The interleaver of an ATM cell separates five incoming ATM cells into headers and payloads by a demux, and blocks the five ATM cell headers by byte. The interleaving is performed on a cell-by-cell basis, and the interleaving process transmits an ATM cell in which five ATM cell headers are inserted by one bit in 10-bit intervals into five ATM cell payloads to the receiving end. Deinterleaver receives the interleaved and transmitted ATM cells, stores them in a 5-cell buffer, and reads the headers of each cell alternately every 10 bits at 50-bit intervals from the 5-cell buffer. And the HEC calculation block of the HEC calculation block connected in parallel to the 5-cell header buffer to identify the boundary of the ATM cell and restore the original ATM cell. Even if a continuous burst error of 50 bits or less occurs at a minimum of 50 bit intervals during transmission, the cell header can be recovered and the cell discard rate can be greatly reduced.

Description

Interleaver and Deinterleaver for Asynchronous Transfer Mode (ATM) Cells

The present invention relates to an ATM cell transmission apparatus for transmitting an Asynchronous Transfer Mode (hereinafter, referred to as ATM) cell using a wireless channel, wherein a bit of an ATM cell header is payloaded. The interleaver and the deinterleaver of an ATM cell can be inserted and transmitted at regular intervals, and restored to the original ATM cell.

In general, the transmission of conventional ATM cells is mainly performed in an optical fiber or a wired environment with almost no errors, and the standard is also adapted to the optical fiber or a wired environment.

In particular, in the transmission of such an ATM cell, an error mainly occurring in the header of the ATM cell is a continuous burst error. When a 1-bit error occurs in the ATM cell header, a header error control algorithm using HEC (Header Error Control) is used. While correcting the error through the error, the cell is discarded when an error of 2 bits or more occurs.

On the other hand, ATM cell transmission using a wireless channel has recently emerged, and a burst error occurs in the ATM cell header.

However, in the transmission of an ATM cell using the radio channel, when using the same header error control algorithm and transmission method as in the transmission of an ATM cell in an optical fiber or a wired environment, a random burst error (BER) Of course, successive burst errors occur at the same time, which leads to an increase in cell discard rate. Accordingly, there is a problem that transmission of ATM cells using a radio channel is very inefficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to insert and transmit an ATM cell header 1 bit into 5 ATM cell payloads at 50 bit intervals based on 5 ATM cells. The present invention provides an interleaver and a deinterleaver of a 5-unit ATM cell capable of significantly reducing the cell discard rate by the cell header error control algorithm by restoring the original ATM cell.

In order to achieve the above object, the interleaver of the ATM cell of the present invention divides five ATM cells into headers and payloads by demux, and performs block interleaving on the separated five ATM cell headers by byte. Interleaving is performed on a cell-by-cell basis. By interleaving, five ATM cell headers are inserted at intervals of 10 bits into an ATM cell payload in which five ATM cell headers are inserted one bit at 10 bit intervals into five ATM cell payloads. It is characterized by transmitting the ATM cell inserted by 1 bit to the receiving end.

The deinterleaver of the ATM cell of the present invention receives the interleaved and transmitted ATM cells, sequentially stores them in a 5-cell buffer, and reads the header of each cell from the 5-cell buffer every 10 bits at 50-bit intervals. It is stored in the 5-cell header buffer, and the boundary of the ATM cell is identified and restored to the original ATM cell through the HEC calculation process of the HEC calculation block connected in parallel to the 5-cell header buffer.

1 is a block diagram of an interleaver of an ATM cell according to the present invention.

2 is a block diagram of a deinterleaver of an ATM cell according to the present invention.

3 is a diagram illustrating an input sequence of a plurality of ATM cells and ATM cell headers according to the present invention.

4 is a block diagram of a block interleaving process of bytes of an ATM cell header according to the present invention.

(A) of FIG. 5 is a diagram showing the configuration of a single unit ATM cell block interleaved by the present invention, and (b) is a diagram showing the configuration of a single unit ATM cell interleaved cell by cell according to the present invention.

<Explanation of symbols for main parts of drawing>

100: demux 110: payload buffer

120, 210: 5-cell header buffer unit 130, 240: mux

140, 250: control unit 200: 5-cell buffer

220: HEC calculation unit 230: speed matching buffer

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the interleaver and deinterleaver of the ATM cell of the present invention.

1 is a block diagram of an interleaver of an ATM cell according to the present invention, which includes a demux (DEMUX) 100 that separates an input ATM cell a into a header and a payload, and the demux 100. A 40-bit payload buffer 110 for temporarily storing payloads of the separated ATM cells a and five 5-byte headers of the ATM cells a separated by the demux 100 are stored. 5 cell header buffer unit 120 comprising 5 buffers 121 to 125 and the payload buffer 110 to output 9-bit ATM cell (a) payload data, and then the 5 cell A mux 130 for outputting one bit ATM cell (a) header data by connecting the header buffer unit 120, the demux 100, the 5-cell header buffer unit 120, and the mux 130. Control unit 140 for controlling each operation of the).

The payload buffer 110 is to remove delay caused by inserting headers between payloads and temporarily stores ATM cell payload data separated by the demux 100.

The interleaver of the present invention configured as described above does not need a separate buffer to store a cell because the cell header can be interleaved and transmitted immediately after the header of the cell is stored in the 5-cell header buffer unit 120. Only the header is inserted into the payload. Only the payload buffer 110 is needed to eliminate the delay that occurs.

Accordingly, the interleaver of the present invention can implement a 5-unit ATM cell interleaver with only 5 x 5 bytes of memory for storing previously received headers.

FIG. 2 is a block diagram of a deinterleaver of an ATM cell according to the present invention, and includes a 5-cell buffer 200 and a 5-cell buffer 200 for sequentially storing an ATM cell b interleaved and transmitted by an interleaver. A five-cell header buffer unit 210 composed of five buffers 211 to 215 having a 40-bit capacity for reading and storing each header data of the ATM cell b stored in the cross-section every 10 bits at 50-bit intervals, Five HEC calculation blocks connected in parallel with each of the buffers 211 to 215 of the 5-cell header buffer unit 210 to perform CRC-8 calculation using bit values of the headers stored in the buffers 211 to 215 ( HEC calculation unit 220 composed of 221 to 225, 40-bit capacity matching buffer 230 for speed matching of ATM cell (b) payload stored in the 5-cell buffer 200, and 5 Connect the cell header buffer 210 to output 40-bit ATM cell header data, and then connect the 5-cell buffer 200 to 40-bit header. A control unit for controlling the mux 240 for determining and deinterleaving the cell boundary identification using the mux 240 for outputting the remaining ATM cell payload, and the HEC calculation result of the HEC calculation unit 220 ( 250).

The operation of the interleaver and deinterleaver of the ATM cell according to the present invention configured as described above will be described with reference to the accompanying drawings.

3 is a cross-sectional view showing the input order of a plurality of ATM cells and ATM cell headers according to the present invention. For the flow and description of the cells, the number of cells and each cell header are specified by byte from 1 to 5, for example. In case of 1.1, it indicates the first header byte of cell 1.

4 is a diagram illustrating a block interleaving process for each byte of an ATM cell header according to the present invention, and FIG. 5 (a) is a diagram showing the configuration of a single unit ATM cell block interleaved according to the present invention, and (b) According to the present invention, a diagram illustrating a configuration of a single unit ATM cell interleaved on a cell basis.

First, the operation of the ATM cell interleaver will be described.

In order to interleave five ATM cells (a), the demux 100 of the interleaver separates the input ATM cells (a) into headers and payloads according to a control signal of the controller 140.

Subsequently, the header of the ATM cell a separated by the demux 100, that is, each of the five byte headers of the five ATM cells according to the control signal of the control unit 140, is stored in the five cell header buffer unit 120. The payloads of the remaining ATM cells (a) separated by the demux 100 are stored in the buffers 121 to 125, and are stored in the payload buffer 110 having a 40-bit capacity.

In this case, the process of storing the header of the ATM cell (a) in the 5-cell header buffer unit 120 is a process of performing block interleaving for each byte of the header.

That is, as shown in FIG. 4, in the block interleaving method, the header of cell 1 is stored in the header buffer unit 120 from the right column 1 of the first row by byte, and the second cell is stored in three rows. From the right 2nd column, cell 3 is stored from the right 3rd column of 5 rows, the 4th cell is stored from the right 4th column of 2nd row, and the 5th cell is stored from the right 5th column of 4 rows.

Subsequently, incoming cells are also stored in the 5-cell header buffer unit 120 in the same manner and order.

In other words, as shown in the 5-cell header buffer unit 120 of FIG. 1, the method for selecting each of the buffers 121 to 125 of the 5-cell header buffer unit 120 includes the first buffer 121 at a 5-cell cycle. The third buffer 123, the fifth buffer 125, the second buffer 122, and the fourth buffer 124 are used in order. For example, if a header of a previously entered cell is stored in the first buffer 121, it is inputted later. The header of the cell is stored in the third buffer 123 and the header of the next incoming cell is stored in the fifth buffer 125, respectively.

When the block interleaving of the five ATM cell headers is completed as described above, interleaving in units of cells is performed as shown in FIGS. 5A and 5B.

Here, the case of interleaving the fifth cell of the hatched portion of FIG. 4 will be described as an example. The fifth byte (1.5) of the first cell header, the second byte (4.2) of the fourth cell header, and the second cell header 10 bits each one bit into the 5th cell payload, hatched a total of 40 bits of the 4th byte (2.4), the 1st byte (5.1) of cell header 5, and the 3rd byte (3.3) of cell header 3 It inserts and transmits at intervals, and inserts all 40 bits of different cell headers by one byte up to the 400th bit, and transmits only the payload as it is from the remaining 401th bit to 424 bits, which is the end of the cell.

That is, when the header of the input cell is stored in an arbitrary buffer of the 5-cell header buffer unit 120, the demux 100 under the control of the controller 140 connects the payload buffer 110 to the ATM cell pay. The load passes through the payload buffer 110 and outputs 9-bit ATM cell payload data through the mux 130.

When all of the 9-bit payload data is output, the mux 130 under the control of the controller 140 connects the first buffer 121 and shifts from the buffer 121 to the left one bit to the right one bit once. Output cell header data.

At this time, since payload data is continuously input through the demux 100, one bit is input and stored in the payload buffer 110 while the cell header data is output.

Then, the mux 130 connects the payload buffer 110 and outputs 9-bit payload data again, and connects the second buffer 122 to output a shift of one bit of the header of cell 4 from left to right. .

At this time, since payload data is continuously input through the demux 100, two bits are stored in the payload buffer 110.

In this manner, the MUX 130 has 9 bits of payload, 1 bit of the third buffer 123, 9 bits of payload, 1 bit of the fourth buffer 124, 9 bits of the payload, and 5th buffer 125. One bit, then nine bits of payload and one bit from the first buffer 121 are sequentially output.

When 40 times are performed in this manner, 40 bits of header data are output for each byte stored in five 5-cell header buffer units 120, and 24 bits, which have not yet been transmitted to the 40-bit payload buffer 110, namely, Of the 384 bits of 48 bytes, 9x40 bits of data have been output, leaving the remaining 24 bits of data.

Therefore, finally, the MUX 130 connects the 40-bit payload buffer 110 to output the remaining 24 bits of payload data in the ebuffer 110, and the cells continuously input in the same order as above. 1-3-5-2-4) after storing the header in the 5-cell header buffer unit 120 (at this time, since the data has been shifted from left to right, the 5-cell header buffer unit 120 has a total of 5 bytes). It is possible because it is empty). The above process is repeated to interleave and transmit ATM cell data.

As a result of the final interleaved result, it can be seen that the bit distance between the same cells is at least 50 bits, and the bit distance between adjacent cells is at least 20 bits.

Next, the operation of the deinterleaver of the ATM cell according to the present invention will be described.

The 5-cell buffer 200 inputs a 5-unit ATM cell b interleaved and transmitted by the interleaver while shifting from left to right in units of bits.

Subsequently, five buffers 211 to 215 having a 40-bit capacity of the five-cell header buffer unit 210 read cell header data stored in the five-cell buffer 200 alternately every 10 bits at every 50-bit interval. And save.

At this time, the data position of the five-cell buffer 200 is the start bit of the first cell of the five cells is located at the right end of the five-cell buffer 200 and the last bit of the fifth cell is located at the left end of the five-cell buffer 200 If present, data is taken from each header bit position.

As described above, when 40-bit header data, which is 5 bytes of the same cell, is respectively stored in each of the buffers 211 to 215 of the 5-cell header buffer unit 210, HEC calculations are performed in parallel to each buffer 211 to 215 for each bit. In the HEC calculation blocks 221 ˜ 225 of the unit 220, a cyclic redundancy check (CRC) -8 calculation for cell boundary identification is performed, and the result is output to the controller 250.

At this time, the control unit 250 is interleaved, when the inputted cells are in the correct position, the CRC-8 value calculated by one of the five HEC calculation blocks 221 to 225 of the HEC calculation unit 220 is ˝0˝ Through this, the boundary of the cell can be determined.

Subsequently, when the controller 250 identifies the warning of the cell through the HEC calculator 220, the control unit 250 outputs a control signal according to the control of the MUX 240.

Accordingly, the mux 240 outputs the 40-bit header data from the first buffer 211 of the five buffers 211 to 215 storing the 40-bit header data for each cell, and then the 5-cell buffer ( Among the 424 bits (53 bytes) corresponding to one cell stored in 200, payload data other than 40 bits of the interleaved cell header is output.

The mux 240 continues with the header data of the second buffer 212, the payload data, the header data of the third buffer 213, the payload data, the header data of the fourth buffer 214, the payload data and the fifth buffer ( Header data and payload data of 215 are sequentially output.

In this case, the speed matching buffer 230 is positioned between the 5-cell buffer 200 and the 5-cell header buffer 210 to output the cell header and the payload following the 5-cell buffer 200 and the 5-cell header buffer. Speed matching between the units 210 is performed.

By repeating the above process, the deinterleaver of the present invention can restore all five-unit ATM cells (a) based on the original five cells.

As described above, the present invention can be easily implemented in an ASIC or an FPGA, and used for transmission of a wireless environment by adding interleaving / deinterleaving technology without modifying hardware or algorithm of a conventional wire-based ATM cell transmission system. This has the effect of reducing the additional cost for wireless transmission.

In addition, even if a continuous burst error of 50 bits or less occurs during transmission at least 50-bit intervals, the cell header can be recovered and the cell discard rate can be greatly reduced, and the interleaver is provided through a payload buffer. In this case, the transmission delay caused by the system can be minimized, and since the deinterleaver can identify the cell boundary, no hardware for boundary identification is needed, and a burst error of 20 bits or less is required as the distance between adjacent cells is at least 20 bits apart. By reducing the probability of the header error control algorithm in the detection mode, cells discarded in the detection mode can be reduced.

Claims (5)

A demux 100 for separating the input ATM cell into a header and a payload, a payload buffer 110 for temporarily storing the payload of the ATM cell separated by the demux 100, and the demux 5 cell header buffer unit 120 composed of 5 buffers 121 to 125 for storing 5 5 byte headers of ATM cells separated by 100, and the payload buffer 110 are connected to each other. A mux 130 for outputting one-bit ATM cell payload data and then connecting the five-cell header buffer unit 120 to output one-bit ATM cell header data, and the demux 100 and the five-cell header buffer An interleaver of an asynchronous transmission mode (ATM) cell, characterized in that it comprises a control unit 140 for controlling each operation of the unit 120 and the mux 130. The ATM cell separated by the demux 100 includes a first buffer 121, a third buffer 123, a fifth buffer 125, and a second buffer of the 5-cell header buffer unit 120. 122), the interleaver of the asynchronous transmission mode (ATM) cell, characterized in that it is stored in the order of the fourth buffer (124). According to claim 1, The mux 130 is connected to the payload buffer 110 outputs payload data of a predetermined bit, each buffer 121 to 125 of the five-cell header buffer unit 120 at a predetermined bit interval To connect one by one to output the header data of one bit to output the header data of each byte stored in the five 5-cell header buffer unit 120 and output the remaining payload data (ATM) ) Interleaver of the cell. A 5-cell buffer 200 for storing ATM cells interleaved and transmitted by an interleaver, and the header data of ATM cells stored in the 5-cell buffer 200 are read and stored alternately at predetermined bit intervals at predetermined bit intervals. The 5-cell header buffer unit 210 including five buffers 211 to 215 having a 40-bit capacity and the buffers 211 to 215 are connected in parallel with each of the buffers 211 to 215 of the 5-cell header buffer unit 210. HEC calculation unit 220 comprising five HEC calculation blocks 221 to 225 for performing CRC-8 calculation using the bit values of the headers stored in the header), and the ATM cell pay stored in the five cell buffer 200. A 40-bit capacity matching buffer 230 for speed matching of the load and the 5-cell header buffer 210 are connected to output an ATM cell header, and then the 5-cell buffer 200 is connected to exclude the header. The mux 240 outputting the remaining ATM cell payload and the HEC calculation result of the HEC calculation unit 220 are used. The deinterleaver of the asynchronous transmission mode (ATM) cell, characterized in that for determining the cell boundary identification and control unit 250 for controlling the operation of the mux 240. 5. The MUX 240 outputs an ATM cell header by sequentially connecting the buffers 211 to 215 of the 5-cell header buffer unit 210, and outputs an ATM cell header. A deinterleaver of an asynchronous transfer mode (ATM) cell, characterized in that to connect the buffer 200 to output the remaining ATM cell payload for the same cell.

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