KR100235618B1 - High voltage semiconductor device and method of manufacturing the same - Google Patents
High voltage semiconductor device and method of manufacturing the same Download PDFInfo
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- KR100235618B1 KR100235618B1 KR1019960047569A KR19960047569A KR100235618B1 KR 100235618 B1 KR100235618 B1 KR 100235618B1 KR 1019960047569 A KR1019960047569 A KR 1019960047569A KR 19960047569 A KR19960047569 A KR 19960047569A KR 100235618 B1 KR100235618 B1 KR 100235618B1
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
본 발명은 소오스/드레인 영역을 콘택홀을 형성한 후에 형성함으로써, 고전압 구동에 따라 두꺼워지는 게이트 산화막의 과도 식각으로 인하여 소자가 열화되는 것을 방지할 수 있는 고전압 반도체 소자 및 그의 제조방법에 관한 것으로, 20V 이상의 동작전압을 갖는 상보형 모스 구조의 고전압 트랜지스터를 제조하는 방법으로서, 소오스/드레인 예정 영역에 제 2 전도형 저농도 불순물 영역이 형성되고, 상부의 전면에는 게이트 산화막이 형성되고, 게이트 산화막의 소정 부분에는 게이트 전극이 형성된 제 1 전도형 반도체 기판을 제공하는 단계; 반도체 기판 상에 절연막을 형성하는 단계; 절연막의 소정 부분에 소오스/드레인 예정 영역과의 전기적인 연결을 위한 콘택홀을 형성하고, 콘택홀을 통하여 제 2 전도형 고농도 불순물의 이온주입 및 열적 어닐링 공정을 통하여 제 2 전도형 고농도 소오스/드레인영역을 형성하는 단계; 및, 소오스/드레인 영역과 콘택되는 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a high-voltage semiconductor device capable of preventing a device from being deteriorated due to excessive etching of a gate oxide film which is thickened by high-voltage driving by forming a source / drain region after forming a contact hole, A method of manufacturing a high-voltage transistor of a complementary MOS structure having an operating voltage of 20 V or higher, comprising the steps of: forming a second conductive low-concentration impurity region in a predetermined region of a source / drain region; forming a gate oxide film on a front surface of the upper portion; Providing a first conductive semiconductor substrate on which a gate electrode is formed; Forming an insulating film on the semiconductor substrate; A contact hole for electrically connecting to a predetermined region of the source / drain region is formed in a predetermined portion of the insulating film, and a second conductivity type high concentration source / drain region is formed through ion implantation of the second conductivity type high concentration impurity and thermal annealing through the contact hole. Forming a region; And forming a wiring to be in contact with the source / drain region.
Description
본 발명은 반도체 소자 및 그의 제조방법에 관한 것으로, 특히 게이트 산화막의 과도식각에 의해 소자가 열화되는 것을 방지할 수 있는 고전압 트랜지스터 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage transistor that can prevent a device from being deteriorated by excessive etching of a gate oxide film and a method of manufacturing the same.
일반적으로 고전압을 사용하는 외부 시스템이 집적 회로에 의해 제어되는 경우, 집적 회로는 내부에 고전압 제어를 위한 소자가 필요하게 되고, 이러한 소자는 높은 브레이크 다운 전압(Breakdown Voltage)을 갖는 구조를 필요로 한다.In general, when an external system using a high voltage is controlled by an integrated circuit, an integrated circuit requires a device for high voltage control therein, and such a device requires a structure having a high breakdown voltage .
즉, 고전압이 직접 인가되는 트랜지스터의 드레인에 있어서는 외부 시스템을 원할하게 동작할 수 있도록 하기 위하여, 드레인과 기판 사이의 펀치 쓰루(punch through) 전압과 상기 드레인과 웰(well) 사이의 브레이크 다운 전압이 상기 고전압보다 커야 한다. 따라서, 상기한 바와 같은 높은 브레이크 다운 전압을 얻기 위하여, 드레인 하부에 드레인과 동일 전도 타입의 저농도층을 갖는 구조의 트랜지스터를 사용하였다.That is, in a drain of a transistor to which a high voltage is directly applied, a punch through voltage between the drain and the substrate and a breakdown voltage between the drain and the well are set so that the drain- Must be higher than the high voltage. Therefore, in order to obtain the high breakdown voltage as described above, a transistor having a low concentration layer of the same conduction type as the drain is used under the drain.
또한, 동작 전압과 밀접한 관계가 있는 게이트 산화막의 두께는, 예컨대 40V 이상의 동작 전압을 사용할 경우 800Å 이상의 두께를 가져야 한다. 그리고, 게이트 산화막의 형성 후 소오스/드레인 영역을 구현하기 위하여, 예컨대 As, BF2등과 같은 무거운 불순물 이온을 반도체 기판으로 주입하게 되는데, 이러한 불순물이 충분한 양으로 주입되기 위해서는 반도체 기판 상에 약 150 내지 200Å 이하의 산화막이 있어야만 한다.Further, the thickness of the gate oxide film closely related to the operating voltage should be 800 ANGSTROM or more when using an operating voltage of 40 V or more, for example. In order to realize a source / drain region after the formation of the gate oxide film, heavy impurity ions such as As, BF 2 and the like are implanted into the semiconductor substrate. In order to implant such impurities in a sufficient amount, An oxide film of 200 Å or less should be present.
따라서, 상기한 고전압 구동을 위한 트랜지스터에 있어서는 반도체 기판 표면에 상기 150 내지 200Å의 산화막을 얻기 위하여, 게이트 산화막을 과도하게 식각하게 된다.Therefore, in the above transistor for high-voltage driving, the gate oxide film is excessively etched to obtain the 150-200 Å oxide film on the surface of the semiconductor substrate.
그러나, 상기한 바와 같은 고전압 트랜지스터 제조 공정은 게이트 산화막의 과도 식각으로 인하여 게이트 전극 물질인 폴리실리콘막에 소정의 언더컷이 발생하여 소오스/드레인 영역의 비오버랩(non-overlap) 문제를 일으키게 된다. 이러한 소오스/드레인 영역과 폴리실리콘막의 사이에서 발생되는 소정의 스페이싱은 심한 경우 브레이크 다운 전압을 20V 까지도 변화시키게 된다.However, in the above-described high-voltage transistor manufacturing process, due to excessive etching of the gate oxide film, a predetermined undercut occurs in the polysilicon film which is a gate electrode material, causing a non-overlap problem of the source / drain regions. The predetermined spacing generated between these source / drain regions and the polysilicon film can also change the breakdown voltage to 20V in severe cases.
또한, 과도한 식각으로 인하여 게이트 산화막이 열화됨과 더불어 소오스/드레인 영역의 기판 손상으로 소정의 접합 누설 전류를 발생시켜 소자의 특성을 열화시키는 문제가 발생하게 되는데, 이러한 문제는 동작 전압이 증가할수록 더욱더 심하게 일어나게 된다.In addition, the gate oxide film is deteriorated due to excessive etching, and a problem of deteriorating the characteristics of the device due to damage of the substrate in the source / drain region due to a predetermined junction leakage current is generated. It happens.
이에, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 소오스/드레인 영역을 콘택홀을 형성한 후에 형성함으로써, 고전압 구동에 따라 두꺼워지는 게이트 산화막의 과도 식각으로 인하여 소자가 열화되는 것을 방지할 수 있는 고전압 반도체 소자 및 그의 제조방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can prevent deterioration of the device due to excessive etching of the gate oxide film, And a method of manufacturing the same.
도 1A 내지 도 1J는 본 발명의 실시예에 따른 고전압 반도체 소자의 제조방법을 설명하기 위하여 순차적으로 나타낸 공정 단면도.1A to 1J are process sectional views sequentially illustrating a method of manufacturing a high-voltage semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Description of the Related Art [0002]
1 : 반도체 기판2 : n웰1: semiconductor substrate 2: n well
3 : n-오프셋층4 : p-오프셋층3: n - offset layer 4: p - offset layer
5 : 필드 산화막6 : 게이트 산화막5: field oxide film 6: gate oxide film
7 : 게이트 전극8 : TEOS 산화막7: gate electrode 8: TEOS oxide film
9 : BPSG막13 : n+소오스/드레인 영역9: BPSG film 13: n + source / drain region
14 : p+소오스/드레인 영역15a, 16a : 소오스 전극14: p + source / drain region 15a, 16a: source electrode
15b, 16b : 드레인 전극15b, 16b: drain electrode
상기 목적을 달성하기 위한 본 발명에 따른 고전압 반도체 소자는 소자 분리막 사이의 액티브 영역을 포함하는 제 1 전도형 반도체 기판 상에 형성된 게이트 산화막과, 상기 게이트 산화막 상부의 소정 영역에 형성된 게이트 전극과, 상기 액티브 영역에 형성된 제 2 전도형 고농도 소오스 및 드레인 영역과, 상기 고농도 소오스 및 드레인 영역 하부에 형성되어 고전압을 흡수하여 전기장의 세기를 약화시키기 위한 제 2 전도형 저농도 반도체 영역과, 상기 소오스 및 드레인 영역과 콘택하는 소오스 및 드레인 전극과, 상기 소오스 및 드레인 전극과 상기 게이트 전극 사이의 상기 반도체 기판 상에 형성된 절연막을 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a high-voltage semiconductor device including: a gate oxide film formed on a first conductive semiconductor substrate including an active region between device isolation films; a gate electrode formed on a predetermined region of the gate oxide film; A second conduction type low concentration semiconductor region formed in the lower portion of the heavily doped source and drain regions and absorbing a high voltage to weaken the strength of the electric field; And an insulating film formed on the semiconductor substrate between the source and drain electrodes and the gate electrode.
여기서, 상기 게이트 산화막은 상기 소오스 및 드레인 영역과 접촉하는 각각의 소오스 전극 및 드레인 전극 사이의 반도체 기판 상에 소정의 두께로 형성된 것을 특징으로 한다.Here, the gate oxide film is formed on the semiconductor substrate between the source electrode and the drain electrode in contact with the source and drain regions to have a predetermined thickness.
또한, 상기한 구성으로 된 본 발명에 따른 고전압 반도체 소자의 제조방법은 20V 이상의 동작전압을 갖는 상보형 모스 구조의 고전압 트랜지스터를 제조하는 방법으로서, 소오스/드레인 예정 영역에 제 2 전도형 저농도 불순물 영역이 형성되고, 상부의 전면에는 게이트 산화막이 형성되고, 상기 게이트 산화막의 소정 부분에는 게이트 전극이 형성된 제 1 전도형 반도체 기판을 제공하는 단계; 상기 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막의 소정 부분에 상기 소오스/드레인 예정 영역과의 전기적인 연결을 위한 콘택홀을 형성하고, 상기 콘택홀을 통하여 제 2 전도형 고농도 불순물의 이온주입 및 열적 어닐링 공정을 통하여 제 2 전도형 고농도 소오스/드레인영역을 형성하는 단계; 및, 상기 소오스/드레인 영역과 콘택되는 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a high-voltage semiconductor device according to the present invention having the above-described structure is a method of manufacturing a high-voltage transistor having a complementary MOS structure having an operating voltage of 20 V or more, Providing a first conductive type semiconductor substrate on which a gate oxide film is formed on a front surface of the upper portion and a gate electrode is formed on a predetermined portion of the gate oxide film; Forming an insulating film on the semiconductor substrate; Forming a contact hole for electrically connecting with a predetermined region of the source / drain region in a predetermined portion of the insulating film; and performing ion implantation and thermal annealing of the second conductivity type high concentration impurity through the contact hole, Forming a source / drain region; And forming a wiring to be in contact with the source / drain region.
상기 구성으로 된 본 발명에 의하면, 콘택홀의 형성 후 소오스 및 드레인 영역을 형성함으로써 과도한 게이트 산화막의 식각을 방지할 수 있게 되어 게이트 산화막의 열화 및 기판의 손상으로 인하여 소자가 열화되는 것을 방지할 수 있게 된다.According to the present invention having the above structure, it is possible to prevent the gate oxide film from being etched excessively by forming the source and drain regions after the formation of the contact holes, thereby preventing degradation of the gate oxide film and deterioration of the device due to damage to the substrate do.
[실시예][Example]
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 1J는 본 발명의 실시예에 따른 고전압 트랜지스터를 나타낸 공정 단면도로서, p웰이 형성된 반도체 기판(1)에 형성된 n웰(2)과, 각각의 웰이 형성된 반도체 기판(1) 상에 형성된 필드 산화막(5)과, 필드 산화막(5) 사이의 n웰(2) 및 p웰 상부에 각각 형성된 게이트 산화막(6)과, 게이트 산화막(6)의 소정 부분에 형성된 게이트 전극(7)과, 필드 산화막(6) 사이의 액티브 영역에 각각 형성된 n+소오스/드레인 영역(13) 및 p+소오스/드레인 영역(14)과, 각각의 소오스/드레인 영역 (13, 14)하부에 각각 형성된 n-오프셋층(3a, 3b) 및 p-오프셋층(4a, 4b)과, 각각의 소오스/드레인 영역(13, 14)과 콘택홀을 통하여 접촉하는 소오스 전극(15a, 16a) 및 드레인 전극(15b, 16b)과, 각각의 전극 사이의 절연을 위하여 기판 상부의 전극들 사이에 형성된 TEOS 산화막(8) 및 BPSG막(9)의 절연막을 포함하여 구성되어 있다.1J is a cross-sectional view of a high-voltage transistor according to an embodiment of the present invention, showing an n-well 2 formed in a semiconductor substrate 1 on which a p-well is formed and a n-well 2 formed on a semiconductor substrate 1 A gate oxide film 6 formed on the n well 2 and the p well between the oxide film 5 and the field oxide film 5 and a gate electrode 7 formed on a predetermined portion of the gate oxide film 6, each of which is formed on the active region between the oxide film (6), n + source / drain region 13 and p + source / drain region 14 and each source / drain regions (13, 14) n respectively formed on the lower-offset layer (3a, 3b) and p - offset layer (4a, 4b) and each of the source / drain regions (13, 14) and the source electrode in contact through a contact hole (15a, 16a) and a drain electrode (15b, 16b And an insulating film of the TEOS oxide film 8 and the BPSG film 9 formed between the electrodes on the substrate for insulation between the electrodes .
여기서, 게이트 산화막(6)은 콘택홀을 통하여 각각의 소오스/드레인 전극(13, 14)과 접촉하는 각각의 소오스 전극(15a, 16a) 및 드레인 전극(15b, 16b) 사이의 반도체 기판(1) 상에 소정의 두께로 형성된 구조를 갖는다.The gate oxide film 6 is formed on the semiconductor substrate 1 between the source electrodes 15a and 16a and the drain electrodes 15b and 16b which are in contact with the respective source / drain electrodes 13 and 14 through the contact holes. As shown in Fig.
이어서, 상기한 구성으로 된 고전압 트랜지스터의 제조방법을 살펴본다Next, a method of manufacturing a high-voltage transistor having the above-described structure will be described
도 1A 내지 도 1J는 본 발명의 실시예에 따른 고전압 트랜지스터의 제조방법을 순차적으로 나타낸 공정 단면도이다.1A to 1J are process sectional views sequentially illustrating a method of manufacturing a high-voltage transistor according to an embodiment of the present invention.
먼저, 도 1A에 도시된 바와 같이, p웰이 형성된 반도체 기판(1) 상에 n형 불순물을 이온 주입하고, 어닐링을 진행하여 소정의 농도 및 깊이를 갖는 n웰(2)을 형성한다.First, as shown in Fig. 1A, an n-type impurity is ion-implanted on a semiconductor substrate 1 on which a p-well is formed, and annealing is performed to form an n-well 2 having a predetermined concentration and depth.
도 1B에 도시된 바와 같이, 이온 주입 공정 및 드라이브 인(drive-in) 공정을 통하여, 이후에 가해지게 될 고전압을 흡수하여 전기장의 세기를 약화시키기 위한 n-오프셋 층(3a, 3b) 및 p-오프셋 층(4a, 4b)을 반도체 기판(1) 및 n웰(2) 영역의 소오스/드레인 예정 영역에 각각 형성한다.As shown in FIG. 1B, n - offset layers 3a and 3b and p (n) are formed through an ion implantation process and a drive-in process to absorb a high voltage to be applied subsequently to weaken the strength of an electric field, The offset layers 4a and 4b are formed in the regions of the source and drain regions of the semiconductor substrate 1 and the n-well 2 region, respectively.
도 1C에 도시된 바와 같이, 반도체 기판(1) 상에 공지된 LOCOS(LOCal Oxidation of Silicon)방법으로 소자간 분리를 위한 필드 산화막(5)을 형성한다. 이때, 필드 문턱전압을 높이기 위한 채널 필드 스톱이온 주입 공정을 진행하여 필드 산화막(5) 하부에 접하는 채널 스톱 영역(도시되지 않음)을 형성한다.As shown in FIG. 1C, a field oxide film 5 for element isolation is formed on a semiconductor substrate 1 by a known LOCOS (LOCal Oxidation of Silicon) method. At this time, a channel field stop ion implantation process for increasing a field threshold voltage is performed to form a channel stop region (not shown) contacting the bottom of the field oxide film 5. [
도 1D에 도시된 바와 같이, 반도체 기판(1) 상부에 800 내지 900Å의 두께로 게이트 산화막(6)을 형성하고, 그 상부에 게이트 전극(7) 형성을 위하여 폴리실리콘막을 형성한다.As shown in FIG. 1D, a gate oxide film 6 is formed on the semiconductor substrate 1 to a thickness of 800 to 900 ANGSTROM, and a polysilicon film is formed on the gate oxide film 6 to form a gate electrode 7 thereon.
도 1E에 도시된 바와 같이, 상기 폴리실리콘막 상부에 포토리소그라피를 통하여 포토레지스트막(도시되지 않음) 패턴을 형성하고, 상기 포토레지스트막을 이용하여 하부의 상기 폴리실리콘막 및 게이트 산화막(6)을 식각함으로써 게이트 전극(7)을 형성한다. 이때, 게이트 산화막(6)의 식각 후 두께는 상기 폴리실리콘막이 게이트 산화막(6) 상에 잔재하는 것을 방지할 수 있도록 약 90 내지 110Å 정도만 식각하여 예컨대 게이트 산화막(6)의 두께가 800Å인 경우 700Å이 남도록 한다. 그리고 나서, 상기 폴리실리콘막의 식각 손상을 제거하기 위하여 소정의 어닐링을 진행한다.1E, a photoresist film (not shown) is formed on the polysilicon film by photolithography, and the polysilicon film and the gate oxide film 6 of the lower part are formed using the photoresist film And the gate electrode 7 is formed by etching. At this time, the etched thickness of the gate oxide film 6 is only about 90 to 110 ANGSTROM so as to prevent the polysilicon film from remaining on the gate oxide film 6. For example, when the thickness of the gate oxide film 6 is 800 ANGSTROM, Let us remain. Then, predetermined annealing is performed to remove etch damage of the polysilicon film.
도 1F에 도시된 바와 같이, 전체 구조물 상부에 이후에 형성될 금속층과의 절연을 위한 유전막으로서 TEOS 산화막(8) 및 BPSG막(9)을 순차적으로 적층하고, BPSG막(9)의 플로우를 실시하여 결과물 상부의 평탄화를 이루도록 한다.As shown in FIG. 1F, a TEOS oxide film 8 and a BPSG film 9 are sequentially stacked as a dielectric film for insulation with a metal layer to be formed later on the entire structure, and the flow of the BPSG film 9 is performed Thereby achieving planarization of the upper part of the resultant product.
이어서, BPSG막(9) 상부에 포토리소그라피를 통하여 포토레지스트막(도시되지 않음) 패턴을 형성한다. 상기 포토레지스트막을 식각 마스크로하여 n-오프셋층(3a, 3b) 및 p-오프셋층(4a, 4b)이 소정 부분 노출되도록 하부의 BPSG막(9) 및 TEOS산화막(8)과 상기 식각되지 않은 나머지의 게이트 산화막(5)을 식각하여 콘택홀(10)을 형성한다.Then, a photoresist film (not shown) is formed on the BPSG film 9 by photolithography. The lower BPSG film 9 and the TEOS oxide film 8 are etched using the photoresist film as an etching mask so that the n - offset layers 3a and 3b and the p - offset layers 4a and 4b are partially exposed, And the remaining gate oxide film 5 is etched to form the contact hole 10.
도 1G에 도시된 바와 같이, 콘택홀(10)이 형성된 반도체 기판(1) 상에 포토리소그라피를 통하여 n웰 영역을 마스킹하는 제 1 포토레지스트막(11) 패턴을 형성한다. 그리고 나서, 콘텍홀(10)을 통하여 노출된 p-오프셋층(4a, 4b)으로 p형 불순물, 바람직하게는 BF2를 주입한다.As shown in FIG. 1G, a first photoresist film 11 pattern is formed on the semiconductor substrate 1 on which the contact hole 10 is formed through photolithography to mask the n-well region. Then, a p - type impurity, preferably BF 2 , is implanted into the p - offset layers 4a and 4b exposed through the con- tact hole 10.
도 1H에 도시된 바왁 같이, 공지된 방법으로 제 1 포토레지스트막(10)을 제거하고, 콘택홀(10)이 형성된 반도체 기판(1) 상에 다시 포토리소그라피를 통하여 p웰 영역을 마스킹하는 제 2 포토레지스트막(12) 패턴을 형성한다. 그리고 나서, 콘텍홀(10)을 통하여 노출된 n-오프셋층(3a, 3b)으로 n형 불순물, 바람직하게는 As 이나 P를 주입한다.The first photoresist film 10 is removed by a known method such as the method shown in Fig. 1H, and a mask is formed on the semiconductor substrate 1 on which the contact hole 10 is formed by masking the p-well region through photolithography again 2 photoresist film 12 are formed. Then, an n - type impurity, preferably As or P, is implanted into the n - offset layers 3a and 3b exposed through the con- tact hole 10.
도 1I에 도시된 바와 같이, 공지된 방법으로 제 2 포토레지스트막(11)을 제거하고, 상기 이온 주입된 불수물의 활성화를 위하여 어닐링을 진행함으로써 p웰 및 n웰(2) 영역에 n+소오스/드레인 영역(13)과 p+소오스/드레인 영역(14)을 형성한다. 또한, 상기 어닐링 공정의 진행시 콘택 리플로우도 동시에 진행되도록 한다.As shown in Fig. 11, the second photoresist film 11 is removed by a known method, and annealing is performed for activation of the ion-implanted water, thereby forming n + source / Drain region 13 and the p + source / drain region 14 are formed. Also, the contact reflow process is performed simultaneously with the annealing process.
도 1J에 도시된 바와 같이, 콘택홀(10)을 통하여 각각의 소오스/드레인 영역(13, 14)과 전기적으로 접촉하도록 금속층을 증착하고, 포토리소그라피 및 식각 공정으로 상기 금속층을 패터닝하여 각각의 소오스 전극(15a, 16a) 및 드레인 전극(15b, 16b)을 형성함으로써 고전압 트랜지스터를 완성하게 된다.As shown in FIG. 1J, a metal layer is deposited so as to be in electrical contact with the respective source / drain regions 13 and 14 through the contact hole 10, and the metal layer is patterned by photolithography and etching processes, By forming the electrodes 15a and 16a and the drain electrodes 15b and 16b, a high-voltage transistor is completed.
상기 실시예에 의하면, 콘택홀의 형성 후 소오스 및 드레인 영역을 형성함으로써 과도한 게이트 산화막의 식각을 방지할 수 있게 되어 게이트 산화막 및 기판의 손상으로 인하여 소자가 열화되는 것을 방지할 수 있게 된다.According to this embodiment, since the source and drain regions are formed after the formation of the contact holes, it is possible to prevent the gate oxide film from being etched excessively, thereby preventing the device from being deteriorated due to the damage of the gate oxide film and the substrate.
또한, 콘택 형성시의 마스크 패턴만으로 자기 정렬된 소오스 및 드레인 영역을 형성할 수 있게 됨으로서 공정이 용이해질 뿐만 아니라, 소오스 및 드레인의 정렬 불량을 고려할 필요가 없으므로 칩 면적을 축소시킬 수 있게 된다.In addition, since the source and drain regions can be formed by self-aligned only by the mask pattern at the time of contact formation, the process can be facilitated and the chip area can be reduced since there is no need to consider the defective alignment of the source and the drain.
한편, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.The present invention is not limited to the above-described embodiment, and various modifications may be made without departing from the technical gist of the present invention.
이상 설명한 바와 같이 본 발명에 의하면, 게이트 산화막의 과도식각에 의해 소자가 열화되는 것을 방지할 수 있는 고전압 트랜지스터 및 그의 제조방법을 실현할 수 있게 된다.As described above, according to the present invention, it is possible to realize a high voltage transistor and a manufacturing method thereof that can prevent the elements from being deteriorated by excessive etching of the gate oxide film.
Claims (8)
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