KR100235603B1 - Atm cell delay circuit - Google Patents

Abstract

The present invention relates to an ATM cell delay circuit that can maintain a constant transfer delay time of an ATM cell and simplify the circuit configuration. The present invention relates to a method for storing ATM cells having different delay times input from outside for a predetermined time. A buffer unit for outputting the ATM cells to have the same delay time; A dummy cell generating unit for outputting a dummy ATM cell having the same size as the ATM cells output from the buffer unit; A cell multiplexing unit for multiplexing the ATM cells and the dummy ATM cells output from the buffer unit and the dummy cell generating unit, respectively, and outputting a predetermined signal; And a cell filter unit configured to receive a predetermined signal multiplexed by the ATM cell and the dummy ATM cell from the cell multiplexing unit, remove the dummy ATM cell from the predetermined signal, and output the ATM cell. By such an apparatus, it is possible to keep the propagation delay time of ATM cells input from the outside constant and to simplify the configuration of the ATM cell delay circuit.

Description

An ATM cell delay circuit

The present invention relates to an ATM (Asynchronous Transfer Mode) cell delay circuit. More specifically, the present invention relates to an ATM cell that maintains a constant transfer delay time of an ATM cell and simplifies the circuit configuration. It relates to a delay circuit.

1 and 2 schematically show a configuration of a conventional ATM cell delay circuit.

First, referring to FIG. 1, one example of a conventional ATM cell delay circuit receives an ATM cell having a different delay time from the outside, increases a short delay time among each ATM cell, and short a long delay time. And a delay adding unit 10 for outputting ATM cells by adjusting the delay time of each ATM cell so as to have the same delay time.

However, an ATM cell delay circuit having such a configuration requires a large shift resistor to increase or decrease the delay time of ATM cells, and also provides a propagation delay time of ATM cells in an ATM network. There is a lot of difficulty in accurately controlling the change in.

Another example of a conventional ATM cell delay circuit proposed to solve this problem is schematically illustrated in FIG. 2.

Referring to FIG. 2, another example of the conventional ATM cell delay circuit includes a dummy cell generating unit 20 for outputting a dummy ATM cell having the same size as the ATM cells, and the dummy cell generating unit ( A cell multiplexing unit 30 which receives dummy ATM cells from the cell 20, multiplexes two signals by receiving ATM cells from the outside, and ATM cells and dummy ATM cells from the cell multiplexing unit 30; And after removing the dummy ATM cells by receiving the multiplexed signals of the cell, the cell filter 40 outputting only ATM cells and the ATM cells input from the cell filter 40 have the same delay time. It has a configuration including a delay adder 10 for increasing and decreasing the delay time of the ATM cells.

However, according to such an ATM cell delay circuit, a plurality of ATM cells input from the outside can have the same delay time to some extent, whereas the configuration of the ATM cell delay circuit becomes very complicated.

SUMMARY OF THE INVENTION The present invention proposed to solve the above-described problem is to provide an ATM cell delay circuit that can maintain a constant delivery delay time of an ATM cell and simplify the circuit configuration.

1 schematically illustrates an example of a conventional ATM cell delay circuit;

2 is a schematic illustration of another example of a conventional ATM cell delay circuit;

3 is a schematic view of a configuration of an ATM cell delay circuit according to an embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

10: delay add unit 20: dummy cell generating unit

30 cell multiplexer 40 cell filter unit

50: buffer part

[Configuration]

According to the present invention for achieving the above object, the ATM cell delay circuit, for storing the ATM cells having a different delay time input from the outside for a predetermined time to output each of the ATM cells having the same delay time with each other; A buffer unit; A dummy cell generating unit for outputting a dummy ATM cell having the same size as the ATM cells output from the buffer unit; A cell multiplexing unit multiplexing the ATM cells and the dummy ATM cells output from the buffer unit and the dummy cell generating unit, respectively, and outputting a predetermined signal; a predetermined signal multiplexed from the cell multiplexing unit by the ATM cell and the dummy ATM cell; And a cell filter unit for outputting an ATM cell after removing the dummy ATM cell in the predetermined signal.

[Action]

By such an apparatus, it is possible to keep the propagation delay time of ATM cells input from the outside constant and to simplify the configuration of the ATM cell delay circuit.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on attached drawing FIG.

3, the ATM cell delay circuit according to the preferred embodiment of the present invention, the ATM cell delay circuit, the ATM cells having a different delay time input from the outside for a predetermined time to store the respective ATM cells It has a configuration including a buffer unit for outputting to have the same delay time with each other. By this apparatus, it is possible to keep the propagation delay time of ATM cells input from the outside constant, and to simplify the configuration of the ATM cell delay circuit.

In Fig. 3, components that perform the same functions as those of the conventional ATM cell delay circuits shown in Figs. 1 and 2 are given the same reference numerals.

3 schematically shows the configuration of an ATM cell delay circuit according to an embodiment of the present invention.

Referring to FIG. 3, an ATM cell delay circuit according to an embodiment of the present invention stores ATM cells having different delay times input from the outside for a predetermined time and outputs the ATM cells to have the same delay time. A buffer unit 50 to output the dummy ATM cell having the same size as the ATM cells output from the buffer unit 50, a dummy cell generating unit 20, and a buffer cell and the dummy cell zener A cell multiplexer 30 for multiplexing the ATM cells and dummy ATM cells output from the rating unit 20 and outputting a predetermined signal, and a predetermined multiplexed ATM cell and dummy ATM cell from the cell multiplexer 30. And a cell filter unit 40 for outputting an ATM cell after removing the dummy ATM cell within the predetermined signal.

The operation of the ATM cell delay circuit having the configuration as described above is as follows.

First, the buffer unit 50 stores ATM cells input from the outside for a predetermined time, and then outputs them by adjusting each ATM cell to have the same delay time.

In addition, the dummy cell generating unit 20 including a cell pattern generator and a gating circuit for forming a continuous cell pattern of the same size may include dummy ATM cells having the same size as the ATM cells. This is a dummy ATM cell for inserting a missing ATM cell in an ATM cell pattern that is composed of a combination of a plurality of ATM cells and outputted from the buffer unit 50.

Next, when multiplexing and outputting the ATM cells and the dummy ATM cells adjusted to have the same delay time from the cell multiplexing unit 30, the cell filter unit 40 receives the multiplexed signals of the ATM cells and the dummy ATM cells. After removing the dummy ATM cells within, only the ATM cells are output.

By the ATM cell delay circuit as described above, it is possible to maintain the propagation delay time of ATM cells input from the outside, and to simplify the configuration of the ATM cell delay circuit.

Claims (1)

A buffer unit 50 storing ATM cells having different delay times input from the outside for a predetermined time and outputting the ATM cells to have the same delay time, and ATM cells output from the buffer unit 50 Multiplexes the dummy cell generating unit 20 for outputting a dummy ATM cell having a size equal to and a plurality of ATM cells and dummy ATM cells output from the buffer unit 50 and the dummy cell generating unit 20, respectively; After receiving a predetermined signal multiplexed by the cell multiplexing unit 30 and the cell multiplexing unit 30 multiplexed the ATM cell and the dummy ATM cell, and removes the dummy ATM cell within the predetermined signal, An ATM cell delay circuit comprising a cell filter unit 40 for outputting an ATM cell.

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