KR100234724B1 - Structure of selected segment in flash eeprom - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a segment selection structure of a flash Y pyrom, and conventionally, when there is an erased cell on the left side of a cell to be read when one cell is read, the reading operation of the cell is slowed due to leakage current through the cell. Had a problem. Therefore, the present invention applies a dummy voltage across one cell when reading cells 0 and 3, applies a dummy voltage across two cells when reading cell 2, and piles four cells when reading cell 1 By applying a voltage, the bit lines crossed between the two cells are configured to be connected with the bit lines of the drain terminals of the leading cells, thereby minimizing leakage current and enabling high speed sensing.

Description

Segment Selection Structure of Flash Epirom

The present invention relates to a segment selection structure of flash ypyrom to minimize leakage current from the sense line to the other bit lines through the surrounding erase cells. In particular, the present invention relates to a segment selection structure of two flash cells. The present invention relates to a segment selection structure of a flash Y pyrom which minimizes leakage current by applying voltage and enables high-speed sensing.

As shown in FIG. 1, the segment selection structure of the conventional flash memory has a word line (row0, row1, ....., row62, row63) connected to a control terminal, and a source terminal and a drain terminal, respectively. A cell array 10 including dummy cells D0, D1, D2, and D3 or cells 0 to 15, ... connected to the dummy bit line DBL or bit line BL; A ground voltage supply unit 20 for supplying a ground voltage of the global bit line MLF for supplying a ground voltage VSS to the cell according to a segment selection decoding signal XYO XYOB; A dummy voltage supply unit 30 for supplying a dummy voltage of a dummy line DUMMY for supplying a dummy voltage to the dummy cell to the dummy cell according to a segment selection decoding signal XYE (XYEB); Supplying the sensing bias voltage of the global bit line (GBL) for supplying the sensing bias voltage for reading the cells to the cell according to the segment selection decoding signals (XYO, XYOB), (XYE, XYEB) It consists of the 1st, 2nd sensing bias voltage supply parts 41 and 42. FIG.

The ground voltage supply unit 20 connects a source terminal to a global bit line MLF for supplying a ground voltage VSS, a drain terminal to a dummy bit line DBL, and a control terminal, respectively. NMOS transistors N21 and N22 configured to receive the segment selection decoding signal XYO (XYOB).

The dummy voltage supply unit 30 connects each of the small source terminals to the dummy line DUMMY for supplying the dummy voltage, connects the drain terminals to the dummy bit line DBL, and decodes the segment selection to the control terminal. NMOS transistors N31 and N32 configured to receive signals XYE and XYEB.

In addition, the first sensing bias voltage supply unit 41 connects the source terminals to the global bit line GBL for supplying the sensing bias voltage, connects the drain terminals to the bit lines BL, respectively, and selects segments as control terminals. It consists of two NMOS transistors configured to receive decoding signals XYO and XYOB, and consists of N transistors. The second sensing bias voltage supply unit 42 is formed in the same manner as the first sensing bias voltage supply unit 41, and the input signal is a segment selection decoding signal XYE (XYEB).

Referring to the operation and effect of the prior art configured as described in detail as follows.

The word line voltage is applied to the word line row0 to read the cell " 0 " of the cell array 10, and to the dummy bit line DBL (3) connected to the source terminal of the cell " 0 ". In order to supply the ground voltage VSS, the ground voltage VSS is applied to the global bit line MLF.

Thereafter, in order to supply the ground voltage to the cell "0", the segment selection decoding signals XYO and XYOB become XYO = 0 and XYOB = 1 and are applied to the ground voltage supply unit 20.

Then, the NMOS transistor N21 of the ground voltage supply unit 20 is turned off, and the NMOS transistor N22 is turned on.

Therefore, the ground voltage VSS applied to the global bit line MLF is applied to the dummy bit line DBL 3 through the global bit line MLF and the NMOS transistor N22.

The ground voltage VSS applied to the dummy bit line DBL 3 is again applied to the source terminal of the cell " 0 ".

At this time, the sensing bias voltage is applied to the global bit line GBL (0), and the segment selection decoding signals XYE and XYEB of XYE = 1 and XYEB = 0 are applied to the first sensing bias voltage supply 41.

As a result, the NMOS transistor N40 of the first sensing bias voltage supply unit 41 is turned on, and the NMOS transistor N41 is turned off.

Then, the sensing bias voltage supplied to the global bit line GBL (0) is applied to the bit line BL (0) via the NMOS transistor N40.

As a result, the sensing bias voltage is applied to the drain terminal of the cell " 0 " of the cell array 10 via the bit line BL (0).

At this time, if the left cells of the leading cell "0" are erased cells, a leakage current is generated through the relaxed cells.

In order to prevent the leakage current, a dummy voltage equal to a sensing bias voltage applied to the global bit line GBL (0) is applied to the global bit line GBL (1) of the second sensing bias voltage supply unit 42. .

Then, the NMOS transistor N50 is turned off by the segment selection decoding signals XYO = 0 and XYOB = 1, and the NMOS transistor N51 is brought into a conductive state.

Therefore, the dummy voltage supplied to the global bit line GBL (1) is applied to the bit line BL (3) via the NMOS transistor N51.

This prevents further leakage.

Eventually, in order to read the cell "0", XYO = 0, XYOB = 1, XYE = 1, XYEB = 0, MLF = 0, GBL (0) = 1, GBL (1) = D, as shown in FIG. Is authorized.

As a result, a reading operation of the cell " 0 " is performed.

In addition, a word line voltage is applied to the word line row0 to read the cell " 1 " of the cell array 10, and the bit line BL (0) connected to the source terminal of the cell " 1 " The ground voltage (0) is applied to the global bit line (GBL (0)) to supply the ground voltage (VSS) to.

Subsequently, segment selection decoding signals XYE and XYEB are applied to the first sensing bias voltage supply part 41 by applying XYE = 1 and XYEB = 0 to supply voltage to the cell “1”.

Then, the NMOS transistor N40 of the first sensing bias voltage supply unit 41 is in a conductive state, and the NMOS transistor N41 is in a blocking state.

Therefore, the ground voltage 0 applied to the global bit line GBL (0) is applied to the bit line BL (0) via the global bit line GBL (0) and the NMOS transistor N40. .

The ground voltage applied to the bit line BL (0) is applied to the source terminal of the cell "1" again.

At this time, the sensing bias voltage is applied to the global bit line GBL (1) of the second sensing bias voltage supply unit 42, and the segments of XY0 = 1 and XY0B = 0 are applied to the control terminals of the NMOS transistors N50 and N51. The selection decoding signals XY0 and XY0B are applied.

As a result, the NMOS transistor N50 is turned on, and the NMOS transistor N51 is turned off.

Then, the sensing bias voltage supplied to the global bit line GBL (1) is applied to the bit line BL (1) via the NMOS transistor N50.

As a result, the sensing bias voltage is applied to the drain terminal of the cell " 1 " of the cell array 10 via the bit line BL (1).

At this time, if the left cells of the leading cell "1" are erased cells, a leakage current is generated through the relaxed cells.

In order to prevent the leakage current, a dummy voltage equal to a sensing bias voltage applied to the global bit line GBL (1) is applied to the global bit line GBL (2) of the first sensing bias voltage supply unit 41. .

In other words, a dummy voltage is applied across two cells.

Then, the NMOS transistor N42 is brought into a conductive state by the segment selection decoding signals XYE = 1 and XYEB = 0, and the NMOS transistor N43 is turned off.

Therefore, the dummy voltage supplied to the global bit line GBL (2) is applied to the bit line BL (4) via the NMOS transistor N42.

This prevents further leakage.

Eventually, in order to read the cell "1", XYO = 1, XYOB = 0, XYE = 1, XYEB = 0, GBL (0) = 0, GBL (1) = 1, ... Is approved.

This leads to reading of the cell " 1 ".

As described above, data values of the decoding signal and the global bit line for reading each cell are as shown in FIG. 2.

However, in the prior art as described above, when the cell "0" is read, the cell 1 and the cell 2 are erased cells, and the cell 3 is a programmed cell, the bit line BL (1) and the bit line BL ( 2)) is charged up through the cells 1 and 2 from the bit line BL (0), which is a sensing node, wherein cells 1 and 2 are turned on as the word line row0 rises. Therefore, even when sensing the cell "0", there is a problem that the leakage current continues to slow the sensing of the programmed cell.

Accordingly, an object of the present invention for solving the conventional problems as described above is flash Y pyrom which enables high-speed sensing by reducing the number of bit lines to be occupied by the erased cells around the reading, and reducing the leakage current It is to provide a segment selection structure of.

In the case of reading the cells " 0 " and the cells " 3 "

Another object of the present invention is to provide a segment select structure of flash Y pyrom to apply a dummy voltage across two cells when reading cell "2".

Another object of the present invention is to apply a dummy voltage across four cells when reading a cell " 1 ", and to connect the bit lines across two cells together with the bit lines of the leading cell to enable high-speed sensing. The segment selection structure of flash Y pyrom is provided.

1 is a block diagram of a segment selection structure of a conventional flash Y pyrom.

FIG. 2 is a diagram showing signal values for selecting each cell CELL in FIG.

Figure 3 is a segment selection structure of the present invention flash ypyrom.

FIG. 4 is a diagram showing signal values for selecting each cell in FIG. 3; FIG.

Explanation of symbols on the main parts of the drawings

100: cell array 200: first voltage supply unit

300: second voltage supply unit

In order to achieve the above object, the present invention applies a dummy voltage across one cell when reading cells "0" and a cell "3", and applies a dummy voltage across two cells when reading cell "2". When the cell “1” is read, a dummy voltage is applied across four cells, and a bit line crossing two cells is connected together with the bit line of the leading cell to enable high-speed sensing.

Hereinafter, with reference to the accompanying drawings in detail as follows.

3 is an embodiment showing a segment selection structure of the flash Y pyrom according to the present invention. As shown in FIG. 3, each word line row0, row1, ..., row62, row63 is connected to a control terminal. A cell array consisting of dummy cells D0, D1, D2, and D3 or cells 0 to 15, ..., connected to the source and drain terminals, respectively, with a dummy bit line DBL or a bit line BL. 100; Connect the source terminals to the global bit line GBL for supplying a predetermined voltage, connect the drain terminal to the bit line BL, and receive the segment selection decoding signal XYOB XYO as the control terminal, respectively. A first voltage supply unit 200 constituting a plurality of NMOS transistors connected in series; The global bit line GBL for supplying a predetermined dummy voltage is connected to the source terminal, the drain terminal is connected to the bit line BL, respectively, and the segment select decoding signal XYEB XYE is respectively connected to the control terminal. The second voltage supply unit 300 constitutes a plurality of NMOS transistors so as to be input.

Referring to the operation and effect of the present invention configured as described in detail as follows.

The word line voltage is applied to the word line row0 to read the cell " 0 ", and to supply the ground voltage VSS to the dummy bit line DBL 3 connected to the source terminal of the cell " 0 ". The ground voltage VSS is applied to the global bit line MLF.

Thereafter, in order to supply the ground voltage to the cell "0", the segment selection decoding signals XYO and XYOB become XYO = 1 and XYOB = 0 and are applied to the first voltage supply unit 200.

Then, the NMOS transistor N1 of the first voltage supply unit 200 is turned off, and the NMOS transistor N2 is turned on.

Therefore, the ground voltage VSS applied to the global bit line MLF is applied to the dummy bit line DBL 3 through the global bit line MLF and the NMOS transistor N2.

The ground voltage VSS applied to the dummy bit line DBL 3 is again applied to the source terminal of the cell " 0 ".

At this time, the sensing bias voltage is applied to the global bit line GBL (0), and the segment selection decoding signals XYE and XYEB of XYE = 1 and XYEB = 0 are applied to the second voltage supply unit 300.

As a result, the NMOS transistor N63 of the second voltage supply unit 300 is turned on, and the NMOS transistor N64 is turned off.

Then, the sensing bias voltage supplied to the global bit line GBL (0) is applied to the bit line BL (0) via the NMOS transistor N63.

As a result, the sensing bias voltage is applied to the drain terminal of the cell " 0 " of the cell array 10 via the bit line BL (0).

At this time, a dummy voltage is applied to the global bit line GBL (1).

The dummy voltage is then applied to the bit line BL (1) via the global bit line GBL (1) and the NMOS transistor N3.

Accordingly, even if the cells on the left of the leading cell "0" are erased, current does not leak.

The ground voltage is supplied to the global bit line GBL (0) to supply the ground voltage VSS to the bit line BL (0) connected to the source terminal of the cell “1”. (VSS) is applied.

Subsequently, in order to supply the ground voltage to the cell “1”, the segment selection decoding signals XYE and XYEB become XYE = 1 and XYEB = 0 and are applied to the second voltage supply unit 300.

Then, the NMOS transistor N64 of the second voltage supply unit 300 is in a blocking state, and the NMOS transistor N63 is in a conductive state.

Therefore, the ground voltage VSS applied to the global bit line GBL (0) is applied to the bit line BL (0) via the global bit line GBL (0) and the NMOS transistor N63.

The ground voltage VSS applied to the bit line BL (0) is applied to the source terminal of the cell “1” again.

In this case, the sensing bias voltage is applied to the global bit line GBL (1), and the segment selection decoding signals XYO and XYOB of XYO = 1 and XY0B = 1 are applied to the first voltage supply unit 200.

As a result, all of the NMOS transistors N3 and N4 of the first voltage supply unit 200 are in a conductive state.

Then, the sensing bias voltage supplied to the global bit line GBL (1) is applied to the bit line BL (1) via the NMOS transistor N3.

As a result, the sensing bias voltage is applied to the drain terminal of the cell " 1 " of the cell array 100 via the bit line BL (1).

As the NMOS transistors N3 and N4 are both in a conducting state, the bit line BL (3) and the global bit line GBL (1) are connected to each other so that the bit line BL (1) and the bit line are connected. (BL (3)) is charged up to the same voltage.

The dummy voltage is applied to the bit line BL (5) and the bit line BL (7) by applying the dummy voltage to the global bit line GBL (3).

In order to read the cell "2", the ground is applied to the global bit line GBL (1) to supply the ground voltage VSS to the bit line BL (1) connected to the source terminal of the cell "2". The voltage VSS is applied.

Thereafter, the segment selection decoding signals XY0 and XY0B become XY0 = 1 and XY0B = 0, and are applied to the first voltage supply unit 200.

Then, the NMOS transistor N4 of the first voltage supply unit 200 is turned off, and the NMOS transistor N3 is turned on.

Therefore, the ground voltage VSS applied to the global bit line GBL (1) is applied to the bit line BL (1) via the global bit line GBL (1) and the NMOS transistor N3.

The ground voltage VSS applied to the bit line BL (1) is again applied to the source terminal of the cell " 2 ".

In this case, the sensing bias voltage is applied to the global bit line GBL (0), and the segment selection decoding signals XYE and XYEB of XYE = 0 and XYEB = 1 are applied to the second voltage supply unit 300.

Accordingly, the NMOS transistor N64 of the second voltage supply unit 300 is in a conductive state, and the NMOS transistor N63 is in a blocking state.

Then, the sensing bias voltage supplied to the global bit line GBL (0) is applied to the bit line BL (2) via the NMOS transistor N64.

As a result, the sensing bias voltage is applied to the drain terminal of the cell " 2 " of the cell array 100 via the bit line BL (2).

At this time, a dummy voltage is applied to the bit line BL (4) by applying a dummy voltage to the global bit line GBL (2).

Finally, in order to read cell "3", ground to global bit line GBL (0) to supply ground voltage VSS to bit line BL (2) connected to the source terminal of cell "3". The voltage VSS is applied.

Thereafter, in order to supply the ground voltage to the cell "3", the segment selection decoding signals XYE and XYEB become XYE = 0 and XYEB = 1 and are applied to the second voltage supply unit 300.

Then, the NMOS transistor N63 of the second voltage supply unit 300 is in a blocking state, and the NMOS transistor N64 is in a conductive state.

Therefore, the ground voltage VSS applied to the global bit line GBL (0) is applied to the bit line BL (2) via the global bit line GBL (0) and the NMOS transistor N64.

The ground voltage VSS applied to the bit line BL (2) is applied to the source terminal of the cell “3” again.

In this case, the sensing bias voltage is applied to the global bit line GBL (1), and the segment selection decoding signals XYO and XYOB of XYO = 1 and XY0B = 1 are applied to the first voltage supply unit 200.

As a result, the NMOS transistor N3 of the first voltage supply unit 200 is turned off, and the NMOS transistor N4 is turned on.

Then, the sensing bias voltage supplied to the global bit line GBL (1) is applied to the bit line BL (3) via the NMOS transistor N4.

As a result, the sensing bias voltage is applied to the drain terminal of the cell "3" of the cell array 100 via the bit line BL (3).

At this time, a dummy voltage is applied to the bit line BL (4) by applying a dummy voltage to the global bit line GBL (2).

That is, when reading cells "0" and cells "3", a dummy voltage is applied across one cell, and when a cell "2" is read, a dummy voltage is applied across two cells, and a cell "1" is read. In this case, dummy voltage is applied across four cells.

Then, since the bit lines crossing the two cells are connected together with the bit lines of the drain terminal of the leading cell, the bit lines are charged up together, which is equivalent to applying a dummy voltage across the two cells.

Here, the data applied to each of the signals and the global bit line is as shown in the table of FIG. 4.

As described above, the application of the dummy voltage is repeated, so that the reading of each cell is performed.

As described above, the present invention applies a dummy voltage across one cell when reading cells “0” and a cell “3”, and applies a dummy voltage across two cells when reading cells “2”. When a cell " 1 " reading is applied, a dummy voltage is applied across four cells, and eventually a dummy voltage is applied across two cells, thereby minimizing leakage current to another bit line through the erased cell. Sensing becomes possible.

Claims (1)

Dummy voltage is applied across one cell when reading cells 0 and 3, Dummy voltage is applied across two cells when reading cell 2, and dummy voltage is applied across four cells when reading cell 1 And a bit line crossing two cells is connected together with a bit line of a drain terminal of a leading cell.

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