KR100234698B1 - Semiconductor device having spiral electrode pattern and its making method - Google Patents
Semiconductor device having spiral electrode pattern and its making method Download PDFInfo
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- KR100234698B1 KR100234698B1 KR1019960056007A KR19960056007A KR100234698B1 KR 100234698 B1 KR100234698 B1 KR 100234698B1 KR 1019960056007 A KR1019960056007 A KR 1019960056007A KR 19960056007 A KR19960056007 A KR 19960056007A KR 100234698 B1 KR100234698 B1 KR 100234698B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000005381 potential energy Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/108—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the Schottky type
- H01L31/1085—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the Schottky type the devices being of the Metal-Semiconductor-Metal [MSM] Schottky barrier type
Abstract
본 발명은 금속-반도체-금속(Metal-Semiconductor-Metal ; MSM)구조된 포토디텍터에서 전극패턴을 나선형으로 설계하고, 전극의 핑거팁(finger tip)수를 감소시킴으로서 고전계에 의한 내부게인(internal gain) 및 어얼리 브레이크다운(early breakdown) 현상을 줄일수 있을 뿐만 아니라 다크(dark)/포토(photo) 전류-전압특성을 향상시키고, 하이스피드(high speed)의 응답특성을 가질 수 있도록 된 나선형 전극패턴을 가진 반도체소자 및 그 제조방법에 관한 것으로, 반도체기판과, 상기 반도체기판상에 형성된 적어도 하나이상의 프로우빙패드와, 상기 프로우빙패드에서 나선형으로 연장되어 형성된 전극핑거로 이루어진 것이다. 그 제조방법은 반도체 기판상에 절연층을 나선형구조로 패터닝하는 단계와, 상기 반도체기판과 절연층의 측면을 제외한 절연층위에 금속을 증착하는 단계와, 상기 절연층을 습식식각법에 의해 식각하는 단계를 포함하여 이루어진다.The present invention relates to a metal-semiconductor-metal (MSM) structured photodetector in which an electrode pattern is spirally designed and the number of finger tips of the electrode is reduced, which can reduce the gain and early breakdown, improve the dark / photo current-voltage characteristics, and have high-speed response characteristics. The present invention relates to a semiconductor device having an electrode pattern and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, at least one probing pad formed on the semiconductor substrate, and an electrode finger extending spirally from the probing pad. The method includes the steps of: patterning an insulating layer on a semiconductor substrate in a spiral structure; depositing a metal on the insulating layer excluding the side surfaces of the semiconductor substrate and the insulating layer; etching the insulating layer by a wet etching method / RTI >
Description
제1도는 종래의 일실시예에 따른 전극패턴의 평면도,FIG. 1 is a plan view of an electrode pattern according to a conventional example,
제2도는 종래의 또다른 실시예에 따른 전극패턴의 개략적인 평면도,FIG. 2 is a schematic plan view of an electrode pattern according to another conventional example,
제3도는 종래의 전극패턴을 가진 반도체소자내부에서의 전계의 영향을 나타낸 종단면도,FIG. 3 is a longitudinal sectional view showing the influence of an electric field inside a semiconductor element having a conventional electrode pattern,
제4도는 종래의 전극패턴을 가진 반도체소자의 에너지밴드를 나타낸 그래프,FIG. 4 is a graph showing energy bands of a semiconductor device having a conventional electrode pattern,
제5도는 본 발명에 따른 나선형 전극패턴의 평면도,FIG. 5 is a plan view of a spiral electrode pattern according to the present invention,
제6도(a) 내지 (d)는 본 발명에 따른 나선형 전극패턴을 가진 반도체소자의 단계적인 제조공정도,6 (a) to 6 (d) are a step-wise manufacturing process of a semiconductor device having a spiral electrode pattern according to the present invention,
제7도는 전압과 다크전류(dark current)와의 관계를 나타낸 그래프,7 is a graph showing a relationship between a voltage and a dark current,
제8도는 시뮬레이션(simulation) 결과에 따른 임펄스 응답(impulse resp onse)을 나타낸 그래프이다.FIG. 8 is a graph showing an impulse response according to a simulation result. FIG.
〈도면의 주요부분에 대한 부호의 설명〉Description of the Related Art
21, 22 : 프로우브 패드(probe pad) 23, 24 : 전극핑거21, 22: Probe pad 23, 24: Electrode finger
23a, 24a : 핑거팁 30 : 반도체기판23a, 24a: finger tip 30: semiconductor substrate
32 : 포토레지스트 34a, 34b : 금속층,32: photoresist 34a, 34b: metal layer,
d : 액티브 영역의 지름d: Diameter of active area
본 발명은 나선형(spiral) 전극패턴을 가진 반도체소자 및 그 제조방법에 관한 것으로, 특히 금속-반도체-금속(Metal-Semiconductor-Metal : MSM)구조된 된 포토디텍터에서 전극패턴을 나선형으로 설계하고, 전극의 핑거팁(finger tip)수를 감소시킴으로서 고전계에 의한 내부게인(internal gain) 및 어얼리 브레이크다운(early breakdown) 현상을 줄일 수 있을 뿐만 아니라 다크(dark)/포토(photo) 전류-전압특성을 향상시키고, 하이스피드(high speed)의 응답특성을 가질 수 있도록 된 나선형 전극패턴을 가진 반도체소자 및 제조방법에 관한 것이다.The present invention relates to a semiconductor device having a spiral electrode pattern and a method of manufacturing the same. More particularly, the present invention relates to a spiral electrode pattern in a metal-semiconductor-metal (MSM) By reducing the number of finger tips of the electrode, it is possible not only to reduce the internal gain and early breakdown due to the high electric field, but also to reduce the dark / photo current-voltage To a semiconductor device having a spiral electrode pattern and a method of manufacturing the same, which are capable of improving characteristics and having high-speed response characteristics.
도1는 종래의 전극패턴의 일실시예에 따른 평면도로서, 이에 도시한 바와 같이, 프로우빙패드(probing pad)(1,2)는 빗살모양으로 패터닝된 다수개의 전극핑거(electrode finger)(1a, 2a)를 가지며, 상기 패드(1,2)의 각각의 전극핑거(1a, 2a)들은 서로 닿지 않고 깍지낀형태(interdigitated)이다.FIG. 1 is a plan view of an electrode pattern according to an embodiment of the present invention. As shown in FIG. 1, a probing pad 1, 2 includes a plurality of electrode fingers 1a 2a, each of the electrode fingers 1a, 2a of the pads 1, 2 being interdigitated without touching each other.
상기 전극패턴을 가진 반도체소자는, 언도프드(undoped) Ⅲ-Ⅴ족 반도체기판상에 포지티브 포토레지스트(positive photoresist)를 코팅한 후 포토리소그래피공정에 의해 패터닝하는 단계와, 상기 패터닝된 포토레지스트를 마스크로 하여 증착기(evaporator)에 의해 쇼트키금속(Schottky)층, 즉, Ti/Au, 혹은 A1 혹은 Ti/Pt/Au 등을 증착시키는 단계와, 리프트오프(Lift-off)방법에 의해 원하는 부분에만 상기 금속층을 남기고 나머지 부분은 제거함으로써 전극핑거(electrode finger)와 프로우빙패드(probing pad)를 형성한다.The semiconductor device having the electrode pattern may include a step of coating a positive photoresist on an undoped III-V semiconductor substrate and patterning the photoresist by a photolithography process, Depositing a Schottky layer, that is, Ti / Au, or Al or Ti / Pt / Au or the like by an evaporator by a lift-off method, The electrode finger and the probing pad are formed by removing the remaining portion of the metal layer.
도1에 도시한 바와 같이, 활성영역(active region)은 다수개의 전극핑거(1a, 2a)가 위치한 부분이고, 참조부호 W,S,D, 및 1은 각각 전극핑거폭, 전극핑거스페이스, 전극핑거주변길이 및 프로우빙패드길이를 나타낸다.1, an active region is a portion where a plurality of electrode fingers 1a and 2a are located, and reference numerals W, S, D, and 1 denote an electrode finger width, an electrode finger space, Finger circumference length and probing pad length.
그러나, 상기 종래 전극패턴을 가진 반도체소자는, 전극핑거팁부분이 날카롭기 때문에 전극핑거팁의 첨점(peak point)에서는 전계집중(electric field cloud)현상이 발생하여 누설전류(leakage current)가 증가되고, 전류게인(current gain)이 증가한다. 또한 신호응답속도(signal response speed)가 감소하는 문제점이 있었다.However, in the semiconductor device having the conventional electrode pattern, since the electrode finger tip portion is sharp, an electric field cloud phenomenon occurs at the peak point of the electrode finger tip to increase the leakage current , The current gain increases. Also, there is a problem that the signal response speed is decreased.
도2는 종래 다른 실시예의 전극패턴을 가진 반도체소자이다(IEEE PHOTONICS THCHNOLOGY LETTERS, VOL.2, NO.1, JANUARY 1990, p56).도시한 바와 같이, 전극핑거팁(finger tip)(6)을 둥글게하여 전계집중현상을 날카로운 전극핑거팁을 사용한 경우보다 줄일 수 있도록 하였다. 그러나, 실제로 빛의 소스(light source)는 원형이므로 전극의 중심부분을 제외한 전극핑거팁(finger tip)영역은 빛에 노출되지 않아 이용하지 않으므로 전극핑거팁을 둥글게 한 경우에도 전계집중현상을 크게 줄이는 효과를 기대할 수 없고, 이 실시예에서도 전극핑거팁이 다수개이므로 이로 인한 다크전류(dark current)가 증가하는 문제점이 있었다. 또한, 둥근 핑거팁을 사용하는 경우에는 액티브영역을 불필요하게 넓히는 결과를 초래하여 캐패시턴스증가 원인이 되는 문제점이 있었다.FIG. 2 is a semiconductor device having an electrode pattern according to another embodiment of the present invention (IEEE PHOTONICS THERMOLOGY LETTERS, Vol. 2, No. 1, Jan 1990, p56) So that the electric field concentration phenomenon can be reduced as compared with the case of using a sharp electrode finger tip. However, since the light source is circular in shape, the electrode finger tip region except for the central portion of the electrode is not used because it is not exposed to light. Therefore, even when the electrode finger tip is rounded, The effect can not be expected. In this embodiment as well, there are a plurality of electrode finger tips, which causes a problem that the dark current is increased. In addition, when a round finger tip is used, there is a problem that the active region is widened unnecessarily, which causes an increase in capacitance.
도3에 도시한 바와 같이, 종래의 전극패턴을 가진 반도체 소자에 있어서, 각각의 전극에 전압을 가하면 전극 밑에 있는 반도체 내부로 공핍영역이 생겨 이부분에 비균일(non-uniform)한 전계(electric field)(8)가 형성된다. 이후 동작영역에 hν에 해당하는 에너지의 빛을 조사(illumination)하면 그에 비례하는 전자-정공쌍(Electron Hole Pair : EHP)이 형성되고, 전자는 (+)극 쪽으로, 정공은(-)극 쪽으로 각각 힘을 받아 이동한다. 전자와 정공이 반대쪽 전극에 도달되면 외부에서 전류를 측정할 수 있다. 전계의 전기력선은 물질표면으로부터 멀어질수록 밀도가 낮아지므로 빛에 의해 형성된 캐리어들은 더욱 적은 힘을 받아 이동속도가 떨어지고, 캐리어의 라이프-타임(life-time)도 영향을 받아 전류(current)가 줄어들고 신호 응답속도(signal response speed)도 느려진다.As shown in Fig. 3, in a semiconductor device having a conventional electrode pattern, when a voltage is applied to each electrode, a depletion region is formed inside the semiconductor under the electrode, and a non-uniform electric field field 8 is formed. Then, when the energy of the energy corresponding to hv is illuminated in the operation region, an electron hole pair (EHP) proportional to the electron is formed. The electrons are directed to the (+) pole and the holes are directed to the Each receives power and moves. When electrons and holes reach the opposite electrode, the current can be measured from the outside. Since the electric force lines of the electric field become lower as the distance from the surface of the material becomes lower, the carriers formed by the light will receive less force to lower the moving speed, and the life-time of the carrier will be affected and the current will be reduced The signal response speed is also slowed down.
도4에 도시한 바와 같이, 종래의 전극패턴을 가진 반도체 소자의 에너지밴드 다이아그램에서, 양극(anode)(+)에서는 정공(hole)이, 음극(cathode)(-)에서는 전자(electron)가 전위장벽(potential barrier)을 뛰어넘어 외부전류에 영향을 주는데 이를 다크전류(dark current)라 한다, 다크전류(dark current)는 인가전압 및 증착 금속의 종류와 소자동작온도등에 비례하여 영향을 받는다. 따라서 높은 전압일수록 금속-반도체간의 장벽높이인에 의해 주어지는 이미지력 저하(image force lowering)와 함께 전자 및 정공의 반도체쪽으로의 주입(injection)이 커져 많은 다크전류(dark current)가 흐르는데, 특히 이러한 현상은 핑거팁(finger tip)에서 많이 발생하며 아울러 결함(defect)과 함께 내부게인(internal gain)에도 큰 영향을 미친다. 도4에서, qv는 포텐셜에너지(potential energy), Ev는 밸런스밴드(balance band)에너지, Ec는 콘덕션밴드(conduction band)에너지, Jh는 정공누설전류밀도(hole leakage current density), Je는 전자누설전류밀도(electron leakage current density)를 각각 나타낸다.As shown in Fig. 4, in the energy band diagram of a semiconductor device having a conventional electrode pattern, holes are generated in the anode (+) and electrons are generated in the cathode (-) The dark current is influenced by the applied voltage, the type of the deposited metal, and the operating temperature of the device. The dark current is affected by the external current, which is beyond the potential barrier. Therefore, the higher the voltage, the higher the barrier height between metal and semiconductor A large amount of dark current flows due to an increase in the injection of electrons and holes toward the semiconductor along with the image force lowering caused by the electron beam and the hole. In addition, it has a large effect on the internal gain as well as the defect. In FIG. 4, qv is a potential energy, Ev is a balance band energy, Ec is a conduction band energy, Jh is a hole leakage current density, Je is an electron And the electron leakage current density, respectively.
본 발명은 상기한 바와 같은 종래 전극패턴을 가진 반도체소자에서의 문제점을 개선하기 위해 안출한 것으로, 전극핑거팁에서의 전계집중현상을 줄이고, 또한 전극핑거수를 줄임으로써 누설전류를 줄일 수 있는 나선형전극패턴을 가진 반도체소자를 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems in the semiconductor device having the conventional electrode pattern as described above, and it is an object of the present invention to provide a spiral type electrode which can reduce the electric field concentration phenomenon in the electrode finger tip, And an object of the present invention is to provide a semiconductor device having an electrode pattern.
상기한 바와 같이 목적을 달성하기 위하여 본 발명의 바람직한 일실시예에 따르면, 도핑안된(undopep) 반도체기판과, 상기 반도체기판상에 형성된 제 1 및 제 2 프로우빙패드와, 상기 제 1 및 제 2 프로우빙패드에서 각각 나선형(spiral)으로 연장형성되고, 각각이 깍지낀(interdigitated)형태로 형성된 전극핑거로 이루어진 것을 특징으로 하는 나선형 전극패턴을 가진 반도체소자가 제공된다.In order to achieve the above object, according to a preferred embodiment of the present invention, there is provided a semiconductor device comprising: an undoped semiconductor substrate; first and second probing pads formed on the semiconductor substrate; A plurality of electrode fingers extending in a spiral direction from the proud electrode pad and formed of interdigitated electrode fingers, respectively.
상기한 바와 같은 본 발명에 따른 나선형 전극패턴을 가진 반도체소자 제조방법은 도핑안된(undoped) 반도체 기판상에 포토레지스트를 코팅하는 단계와, 상기 포토레지스트를 패터닝하는 단계와, 상기 패터닝된 포토레지스트를 포함한 상기 반도체기판상에 금속층을 형성하는 단계와, 상기 패터닝된 포토레지스트를 에칭하여 상기 포토레지스트패턴상의 금속층을 동시에 제거하는 단계를 포함하고 있다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device having a spiral electrode pattern, comprising: coating a photoresist on an undoped semiconductor substrate; patterning the photoresist; Forming a metal layer on the semiconductor substrate including the photoresist pattern; and etching the patterned photoresist to remove the metal layer on the photoresist pattern at the same time.
상기 본 발명에 따른 나선형전극패턴을 가진 반도체소자는 다크전류 혹은 누설전류에 의한 영향이 줄어듬에 따라 하이스피드 응답특성을 가진다.The semiconductor device having the spiral electrode pattern according to the present invention has a high-speed response characteristic as the influence of the dark current or the leakage current is reduced.
이하 본 발명에 따른 나선형전극패턴을 가진 반도체소자를 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device having a spiral electrode pattern according to the present invention will be described in detail with reference to the accompanying drawings.
도5에 도시한 바와 같이, 본 발명에 따른 나선형 전극패턴은 프로우빙패드(21,22)에서 각각 연장형성된 2개의 나선형(spiral) 전극핑거(23,24)가 깍지낀( interdigitated)형태로 형성되어 있다. 각각의 전극핑거(23,24)의 전극핑거팁(23a, 24a)은 둥글게 형성하여 날카로운 핑거팁으로 인해 전계집중현상을 억제한다.5, the spiral electrode pattern according to the present invention is formed by forming two spiral electrode fingers 23 and 24 extended from the probing pads 21 and 22 in an interdigitated form, . The electrode fingers 23a and 24a of the electrode fingers 23 and 24 are formed in a round shape to suppress electric field concentration due to sharp finger tips.
참고부호 d는 액티브영역(active region)의 지름을 나타내며, 액티브영역은 일반적인 입력라이트빔(input light beam)의 모양과 일치하도록 원형으로 설계되었다.Reference symbol d denotes the diameter of the active region, and the active region is designed in a circular shape to match the shape of a typical input light beam.
상기 본 발명에 따른 나선형 전극패턴을 가진 반도체소자의 제조공정을 도6의 (a) 내지 (d)를 참조하여 설명한다.The manufacturing process of the semiconductor device having the spiral electrode pattern according to the present invention will be described with reference to Figs. 6A to 6D.
도6의 (a)에서, 도핑안된(undoped) Ⅲ-Ⅴ족 반도체 기판(30)상에 절연층인 포토레지스트(32)를 코팅한다. 상기 절연층은 산화막 또는 질화막중의 하나로 형성할 수 도 있다.6A, a photoresist 32, which is an insulating layer, is coated on an undoped III-V semiconductor substrate 30. The insulating layer may be formed of one of an oxide film and a nitride film.
도6의 (b)에서, 상기 포토레지스트(32)를 패터닝하여 상기 기판(30)의 일정영역을 노출시킨다.In FIG. 6 (b), the photoresist 32 is patterned to expose a certain region of the substrate 30.
도6의 (c)에서, 상기 패터닝된 포토레지스트(32)를 포함한 상기 반도체기판(30)상에 EB증기법(Electron Beam evaporation method) 또는 스퍼터링(sputtering)에 의해 금속층(34)을 형성한다. 상기 금속층은 Ta 또는 Ti(34a)를 각각 약 350A 증착한 후 Au(34b) 약 1500!+을 증착한다. 이때, 증착되는 금속층은 포토레지스트의 상층과 노출된 기판에만 증착되고 포토레지스트의 측면에는 증착되지 않는다.6 (c), a metal layer 34 is formed on the semiconductor substrate 30 including the patterned photoresist 32 by EB (Electron Beam Evaporation) or sputtering. The metal layer is formed by depositing Ta or Ti (34a) at about 350A and Au (34b) at about 1500s +. At this time, the deposited metal layer is deposited only on the upper layer of the photoresist and on the exposed substrate, and is not deposited on the side of the photoresist.
도6의 (d)에서, 리프트-오프(Lift-Off)방법으로 상기 패터닝된 포토레지스트(32)를 제거한다. 이로인해 상기 포토레지스트패턴(32)상의 금속층(34)도 함께 제거되고, 상기 반도체기판(30)상에는 패터닝된 금속층(34)이 남게된다.6 (d), the patterned photoresist 32 is removed by a lift-off method. As a result, the metal layer 34 on the photoresist pattern 32 is also removed, leaving a patterned metal layer 34 on the semiconductor substrate 30.
도7는 본 발명 및 종래기술에 따른 전압과 다크전류(dark current)와의 관계를 나타낸 그래프로서, 이에 도시한 바와 같이, 본 발명에 따른 반도체소자의 전류-전압특성(9)은 날카로운 팁의 수를 감소시킴으로써 이로 인해 발생하였던 전계집중현상의 영향력을 줄일 수 있으므로 종래 반도체소자의 전류-전압특성(10)보다 다크전류가 줄어들었다. 특히 높은 전압을 가했을 때 이 사실은 더욱 명백하다. 이로부터 알 수 있는 사실은 낮은 전압구간(도7의 점선부분)에서는 쇼트키(schottky)금속에 의한 이미지력저하(image force lowering)에 의해 캐리어 주입(injection)과 열에너지(thermal energy)에 의한 주입(injection)이 누설전류와 내부게인의 주 원인이지만, 높은 전압구간에서는 전극핑거팁(finger tip)에서 국부적으로 일어나는 충격이온화(impact ionization)가 주된 원인으로 실험상 밝혀진다.FIG. 7 is a graph showing the relation between the voltage and the dark current according to the present invention and the related art. As shown in FIG. 7, the current-voltage characteristic 9 of the semiconductor device according to the present invention is expressed by the number of sharp tips The influence of the field concentration phenomenon which has been caused thereby can be reduced, so that the dark current is smaller than the current-voltage characteristic 10 of the conventional semiconductor device. This fact is more evident especially when high voltage is applied. It can be seen from the fact that in the low voltage section (the dotted line portion in FIG. 7), injection by carrier injection and thermal energy by image force lowering by schottky metal, injection is the main cause of leakage current and internal gain. However, experimentally, it is revealed that the impact ionization occurs locally in the electrode finger tip at high voltage.
한편, 본 발명에 따른 나선형전극패턴을 가진 반도체소자는 전극 길이가 긴 관계로 임피던스(impedance)증가로 인한 임펄스응답(impulse response)에 영향을 주지만 이러한 문제점은 액티브영역을 줄임으로써 극복할 수 있다.Meanwhile, the semiconductor device having the spiral electrode pattern according to the present invention affects the impulse response due to an increase in impedance due to a long electrode length, but such a problem can be overcome by reducing the active area.
도8는 본 발명 및 종래 기술에 관한 시뮬레이션(simulation)결과에 따른 임펄스응답(impulse response)을 나타낸 그래프, 이에 도시한 바와 같이, 나선형 전극패턴에 의한 곡선(11)이 종래 전극패턴에 의한 곡선(12)에 비해 실재로 잘 알려진 인턴턴스 피킹(inductance peaking)에 의해 임펄스 응답(impulse response)의 트레일링 에지 프로파일(trailing edge profile)이 개선되었음을 알 수 있다. 특히, 본 발명에 따른 반도체소자의 나선형 전극패턴은 장거리 통신에서 사용되는 광파이버(optical fiber)의 모양과 일치(match)됨으로 커플링 효과(coupling efficiency)를 증가시키는 효과도 있다.8 is a graph showing an impulse response according to the simulation results of the present invention and the related art. As shown in FIG. 8, a curved line 11 formed by a spiral electrode pattern is a curved line 12, it can be seen that the trailing edge profile of the impulse response is improved by the well-known inductance peaking. Particularly, the spiral electrode pattern of the semiconductor device according to the present invention has an effect of increasing the coupling efficiency because it matches with the shape of the optical fiber used in long-distance communication.
또한, 본 발명에 따른 나선형 전극패턴을 가진 반도체소자의 전압-광전류의 관계에 있어서, 높은 전압에서 내부 직류 게인이 종래의 전극패턴을 가진 반도체소자에 비해 훨신 적어지는 효과가 있다.In addition, in the relationship between the voltage and the photocurrent of the semiconductor device having the spiral electrode pattern according to the present invention, there is an effect that the internal DC gain at the high voltage is much smaller than that of the semiconductor device having the conventional electrode pattern.
Claims (18)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960056007A KR100234698B1 (en) | 1995-12-30 | 1996-11-21 | Semiconductor device having spiral electrode pattern and its making method |
| JP8348996A JPH09293887A (en) | 1995-12-30 | 1996-12-26 | Semiconductor element and manufacture thereof |
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| KR95-68667 | 1995-12-30 | ||
| KR1019950068667 | 1995-12-30 | ||
| KR19950068667 | 1995-12-30 | ||
| KR1019960056007A KR100234698B1 (en) | 1995-12-30 | 1996-11-21 | Semiconductor device having spiral electrode pattern and its making method |
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| KR100234698B1 true KR100234698B1 (en) | 1999-12-15 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100885668B1 (en) * | 2006-12-06 | 2009-02-26 | 한국전자통신연구원 | Inter digitate electrode for electronic device and Electronic device using inter digitate electrode |
| US7520173B2 (en) | 2006-12-06 | 2009-04-21 | Electronics And Telecommunications Research Institute | Interdigitated electrode for electronic device and electronic device using the same |
| KR100931578B1 (en) * | 2007-12-18 | 2009-12-14 | 한국전자통신연구원 | Piezoelectric element microphone, speaker, microphone-speaker integrated device and manufacturing method thereof |
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1996
- 1996-11-21 KR KR1019960056007A patent/KR100234698B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100885668B1 (en) * | 2006-12-06 | 2009-02-26 | 한국전자통신연구원 | Inter digitate electrode for electronic device and Electronic device using inter digitate electrode |
| US7520173B2 (en) | 2006-12-06 | 2009-04-21 | Electronics And Telecommunications Research Institute | Interdigitated electrode for electronic device and electronic device using the same |
| KR100931578B1 (en) * | 2007-12-18 | 2009-12-14 | 한국전자통신연구원 | Piezoelectric element microphone, speaker, microphone-speaker integrated device and manufacturing method thereof |
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