KR100232889B1 - Apparatus and method for preventing data loss - Google Patents

Abstract

The present invention makes the voltage swing width made by the write data larger than the voltage swing width on the IO line (or / IO line) by the read data, so that when two conflicting data collide on the IO line, the IO The present invention relates to a data loss prevention method and apparatus for recovering write data by sensing a voltage difference generated between a and / IO lines in a write driver.

Description

Data loss prevention method and device therefor in case of data collision

In general, data by a read command is sent to a data output block through a data input / output line (hereinafter, referred to as an 'IO line') and a data input block (by a write command). Data entering the Din Block is loaded on the bit line via the IO line.

FIG. 1 illustrates operations of read and write when the cas signal CAS has a length of 2 and a burst length of 4. Data1, which is the first data by the read command, has a CAS length of 2, so it is loaded on the IO line after the positive edge of clock 2 to send data to the data output block before the positive edge of clock 3. Export this data from the data output block to the DQ. The Write command enters the clock (7), and since the CAS length for the write is zero, Data1 enters the clock (7). This is loaded onto the IO line after the positive edge of clock 7 as shown in FIG. 1 via the Din block. A block diagram of a circuit that performs this operation is shown in FIG. At this time, the operation of IO line and / IO line is as follows. In the initial state, both IO and / IO are at high voltage. The data to be read or written is the "high" voltage. If the data to be read or written is 'high', the voltage on the IO line is dropped by ΔV, and if the data is 'low', the voltage drop is dropped by ΔV on the / IO line. Occurs. The timing diagram in Figure 1 shows the behavior of the IO when the read data is "high" and the write data is "low."

The timing diagram shown in FIG. 3 is an operation timing diagram for another read and write command. The write command is coming in from the clock 5. In this case, among the data loaded into the Dout block by the read command, Data3 collides with Data1 coming into the DQ by the write command. In order to prevent this, the DQM command is required as shown in FIG. This can prevent collision with write data by suppressing sending Data3 and Data4 to DQ in the Dout block. However, as shown in FIG. 3, the read data on the IO line cannot be removed, so the clock (5) can prevent the collision of Data4, the last data of the read, and the Write data. There is a problem that can not be avoided and lose the write data.

Therefore, in the present invention, the voltage swing width made by the write data is made larger than the voltage swing width at the IO line (or / IO line) by the read data, so that when data having two opposite values collide on the IO line It is an object of the present invention to provide a data loss prevention method and apparatus for recovering write data by sensing a voltage difference generated between the IO and / IO lines in a write driver.

In order to achieve the above object, the data loss prevention method according to the present invention comprises the first step of transmitting the data amplified by the bit line sense amplifier by the read command to the data bus line pair, and the data input by the write command; A second process of buffering and transmitting the data data to the data bus line pair; sensing the potential swing width of the write data on the complementary data bus line and the read data transmitted from the bit line; And a fourth process of amplifying the data carried on the data bus line and outputting the amplified data to the output buffer.

In order to achieve the above object, another method of preventing data loss of the present invention includes a first process of inputting two different commands, and a method for giving priority to any one of the two different commands over another one. When the data generated by the command collide with each other on the same data bus line, the potential swing width of the data generated by the command having priority is the potential of the data generated by the command that is not. The third process was made larger than the swing width.

In order to achieve the above object, the data loss prevention apparatus of the present invention includes column switching means for transmitting read data amplified by a bit line sense amplifier to a data bus line pair by a column decoder output signal, and inputted by a write command. A data input buffer means for buffering data and transmitting the data to the data bus line pair, and sensing the potential swing width of the write data on the complementary data bus line and the read data transmitted from the bit line, and then sensing the write data. A write driver means for outputting the data bus line, and a data bus line sense amplifier for amplifying the data carried on the data bus line and outputting the data to the output buffer.

1 is a first operation timing diagram for a conventional lead and light.

2 is a configuration diagram of a semiconductor memory device for conventional read and write operations.

3 is a second timing diagram of a conventional lead and light.

4 is a block diagram of a data loss prevention apparatus according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: bit line sense amplifier 20: P-MOS clamp circuit

30: write driver 40: databus line sense amplifier

50: input buffer block 60: output buffer block

70: output buffer control circuit 80: input / output pins

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a data loss prevention apparatus according to an embodiment of the present invention, in which a data bus line (IO, / IO) pair is freed with a power supply potential (Vcc) in a standby mode in which a circuit does not operate. A clamp circuit 20 composed of a charged P-MOS and a read data amplified by the bit line sense amplifier 10 by the column decoder output signal are transferred to the data bus line (IO, / IO) pairs. Column switch circuits MN1 and MN2, a data input buffer block 50 for buffering the data inputted by the write command and transferring the data to the data bus line pairs IO and / IO; A write driver 30 which senses the potential swing width of the write data loaded on the IO) and the read data transmitted from the bit line, senses the write data, and outputs the write data to the data bus line; and the data bus line IO, / IO) Amplifying a lean data and includes a data bus line sense amplifier 40 for output to the output buffer 60.

The voltage swing width of data carried on the data bus lines IO and / IO lines by the Read command is ΔVr, and the voltage swing width of data carried on the IO and / IO lines by the Write command. If ΔVw, make [△ Vw >> ΔVr]. That is, the data to be read causes a small voltage drop to the IO and / IO lines, and the voltage drop of the write data coming through the Din block 50 is much larger. do.

In the case of read data, the output buffer is made of Nout and / Nout amplified by the amplifier 40 before entering the output buffer block 60 as shown in FIG. Since there is no difference from the IO value entering the block 60, there is no change in read operation.

The lead data colliding at the IO and / IO lines is 'high' and the write data is 'low', so the IO line is lowered by ΔVr by the read data among the IO and / IO lines, which were both 'high'. At this time, Nin and / Nin, which were initially 'high', / Nin is lowered by ΔVw by the write data, and by / Nin, the / IO line is lowered by ΔVw at the 'high' voltage value. Since the voltage value of / IO is (△ Vw- △ Vr) lower than IO, it is possible to sense that the data is 'low' due to the lower / IO voltage value in the write-drive. Therefore, the write operation can be guaranteed by preventing the write data from being sent to the bit line.

In the above case where data by the Read command and data by the Write command collide, the Write command has priority. That is, the information of the write data should be maintained in preference to the information of the read data. Therefore, the loss of the write data can be prevented by making the voltage swing width of the write data larger than that of the read data.

When commands or data used in a general semiconductor device collide with each other, the voltage swing width of the signal having priority over the two commands or data is larger than the voltage swing width of the other signal to give information of the priority command or data. Do not lose.

When the Write command comes in before the data of the Read command is output to the input / output pin DQ, the DQM command comes in to prevent data collision at the DQ. As a result, data collision in the DQ can be avoided, but an IO data collision as described above can occur and the write data can be lost. The present invention prevents loss of priority data by increasing the competitiveness of the priority data when two data collide. Therefore, when a collision between the command and data used in the semiconductor device occurs, the operation of the command or data having priority is guaranteed.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

The present invention relates to a method and a device for preventing data loss during a data collision, and more particularly, by using write data rather than a voltage swing width in an IO line (or / IO line) caused by read data. By making the voltage swing width large, the data loss prevention method recovers the write data by sensing the voltage difference between the IO and / IO lines in the write driver when two conflicting data collide in the IO line. And to the apparatus.

Claims (7)

A data loss prevention method in a data collision, comprising: a first step of precharging a pair of data bus lines to a first power source voltage in a standby mode; and amplifying data amplified by a bit line sense amplifier by a read command. A second process of transmitting to the data bus line pair by buffering the data inputted by the write command to the data bus line pair, and a read data of the complementary data bus line and read data transmitted from the bit line. A fourth process of sensing the potential swing width and sensing the write data and outputting the write data to the data bus line; and a fifth process of amplifying the data on the data bus line and outputting the data to the output buffer. How to avoid loss. The method of claim 1, wherein the first source voltage source is a source voltage. The method of claim 1, wherein the potential swing width of the write data transferred to the data bus line is much larger than the potential swing width of the read data loaded on the same data bus line. 1. A method of preventing data loss during a data collision, comprising: a first process of inputting two different commands; a second process of giving priority to any one of the two different commands over another command; When the data generated by the data collide with each other on the same data bus line, the potential swing width of the data generated by the priority command is larger than the potential swing width of the data generated by the non-command. Data loss prevention method comprising the three steps. A semiconductor memory device comprising: precharge means for precharging a pair of data bus lines to a first power source voltage in a standby mode; and read data amplified by a bit line sense amplifier by a column decoder output signal to the data bus line pairs; Column switching means for transmitting, data input buffer means for buffering the data inputted by the write command, and transmitting the buffered data to the data bus line pair, and write data loaded on the complementary data bus line and read data transmitted from the bit line. And a write driver means for sensing the potential swing width, sensing the write data, and outputting the written data to the data bus line, and a data bus line sense amplifier for amplifying the data on the data bus line and outputting the data to the output buffer. Data loss prevention device. 6. The data loss prevention apparatus of claim 5, wherein the first power source voltage source is a power source voltage. 6. The data loss prevention apparatus according to claim 5, wherein the precharge means is composed of a P-MOS.