KR100231687B1 - Output circuit - Google Patents

Abstract

[assignment]

The present invention provides an output circuit capable of increasing the maximum output current as much as possible, stabilizing the bias current in a steady state, and reducing the current consumption.

[Resolution]

As long as the gate is connected to the constant voltage source 2, the first transistor M1 of the conductivity type, and the second transistor M2 of the reverse conductivity type, in which the source is connected to the source of the first transistor and the gate is connected to the circuit input terminal 1N. ), A current-current for outputting a current in proportion to the drain current of the conductive type third transistor M3 and the second transistor as long as the drain is connected to the circuit output terminal OUT and the gate is connected to the circuit input terminal. Including the converter circuit 1a, the output current of the current-current converter circuit 1a in the steady state and the drain current of the third transistor are set by the output voltage of the constant voltage source 2.

Description

Output circuit

The present invention relates to an output circuit of a semiconductor device, and more particularly to an output circuit suitable for use in the output terminal of the operational amplifier.

A configuration example of a conventional operational amplifier will be described with reference to the drawings. 10 shows an operational amplifier described in Japanese Patent Laid-Open No. 1-318414.

In the same figure, the constant current source 1101 and the transistors M101, M102 and M107 form a current mirror circuit and provide constant current to the input amplifier stage and the output amplifier stage. The MOS transistors M105 and M106 constitute input amplifiers IN + and IN- having complementary voltage levels as inputs, and constitute differential amplifiers having the drain of the transistor M104 as an output terminal. The voltage at this output stage is amplified by an output circuit consisting of MOS transistors M107 to M113 and output to the output stage OUT.

In this configuration, the output sink current suctioned from a load not shown flows as the drain current of the transistor M112. The transistors M112 and M109 are connected via a current mirror circuit composed of transistors M112 and M111 and a current mirror circuit composed of transistors M109 and M110, so that the drain current of the transistor M112 is the drain current of the transistor 109. Proportional to The maximum drain current of the transistor M109 becomes the drain current of the transistor M107 as a current source. The drain current of the transistor M107 is proportional to the output current of the constant current source 1101 by the current mirror circuits of the transistors M101 and M107.

Therefore, in order to increase the maximum output sinking current of the output terminal OUT to increase the driving capability of the load, it is necessary to increase the output current of the current source 1101 to increase the normal bias current of the circuit.

11 shows an example of the amplifier of US Patent No. 4,529,948. In this example, the maximum drain current of the output transistor M207 that sucks the sink current from the load is a current mirror circuit composed of transistors M207 and M203, a current mirror circuit composed of transistors M202 and M204, and a current mirror composed of transistors M205 and M206. Since it is connected via a circuit, it is determined by the output currents of the constant current sources I201 and I202.

Also in this amplification circuit, in order to increase the maximum output sink current of the output terminal OUT to increase the driving capability of the load, it is necessary to increase the output current of the current sources I201 and I202 to increase the normal bias current of the circuit. have.

12 shows an example of the amplifier of US Patent No. 4,284,957. In this example, the current source I301 and the transistors M301, M302, and M307 constituting the current mirror circuit provide a constant current of the circuit. The transistors M302 to M306 constitute a differential amplifier circuit. The transistor M308, the speed-up capacitor C302, and the transistor M307 constitute a level shift circuit. The capacitor C301, the transistors M309, and M310 constitute a phase compensation circuit. Transistors M311 and M312 constitute an output circuit. The gate of the transistor M312 is connected to the drain of the transistor M306, and the gate of the transistor M311 is connected to the drain of the transistor M307.

In this example, the sink current drawn into the output circuit from the load circuit (not shown) is determined by the gate voltage of the transistor M311. The gate voltage of the transistor M311 is determined by the gate voltage of the transistor M308. The gate voltage of the transistor M308 is the output of the differential amplifier circuit. Assuming that the differential amplifier circuit operates ideally, when the input voltages IN + and IN- are the same (the input differential voltage is 0), the output voltage obtained at the drain node of the transistor M306 is the voltage of the drain node of the transistor M305. Becomes the same as

On the other hand, since the gate-drain of the transistor M305 is connected, the voltage of the drain node of the transistor M305 becomes a voltage dropped by the gate-source voltage Vgs from the power supply voltage VDD. For this reason, the gate voltage of the transistor M311 has a power supply voltage dependency. The bias currents of the output transistors M311 and M312 depend on the power supply voltage VDD, and the consumption current largely depends on the power supply voltage VDD. If the Vth (threshold voltage) of the transistor changes, the gate voltage of the transistor M311 and the Vgs-Ids (gate-to-source voltage to source-drain current) characteristics of the transistor M311 change. For this reason, the bias current of the output transistors M311 and M312 changes greatly, and the consumption current also changes significantly.

As described above, in the circuit configurations shown in Figs. 10 and 11, in order to obtain a large sink current, it is necessary to increase the normal supply current of the constant current source. In the circuit configuration shown in Fig. 13, the bias current of the output transistor changes under the influence of the power supply voltage, which is not suitable. As described above, in the conventional configuration, the current consumption in the steady state is increased when no current flows in and out of the output terminal, and the potential of the output terminal is near the midpoint of the power supply voltage.

The present invention has been made in view of the above, and an object thereof is to provide an output circuit which can increase the maximum output current as much as possible, stabilize the bias current in a steady state, and reduce the current consumption.

1 is a circuit diagram illustrating a basic configuration of the present invention.

2 is a circuit diagram showing an example of a specific circuit of the basic configuration shown in FIG.

3 is a circuit diagram showing a modification of the basic configuration shown in FIG.

4 is a circuit diagram showing an example of a specific circuit of the circuit shown in FIG.

FIG. 5 is a circuit diagram showing an example in which a level shift circuit is added to the circuit shown in FIG.

6 is a circuit diagram showing an example in which a level shift circuit is added to the circuit shown in FIG.

FIG. 7 is a circuit diagram showing an example in which a phase compensation circuit is provided in the circuit shown in FIG.

8 is a circuit diagram showing an example of the configuration of the operational amplifier using the output circuit of the present invention.

9 is a circuit diagram showing an example of the configuration of another operational amplifier using the output circuit of the present invention.

10 is a circuit diagram showing a configuration example of a conventional operational amplifier.

11 is a circuit diagram showing a configuration example of a conventional operational amplifier.

12 is a circuit diagram showing a configuration example of a conventional operational amplifier.

* Explanation of symbols for main parts of the drawings

1: output circuit 2: voltage source, reference voltage generating circuit

3: differential amplifier circuit 4: constant current source bias circuit

5: reference voltage generating circuit M1: transistor of gate ground circuit

M2: Source follower transistor M3: NMOS output transistor

In order to achieve the above object, the output circuit of the present invention has a first transistor M1 of conductive type as long as the gate is connected to the constant voltage source 2, the source is connected to the source of the first transistor, and the gate is connected to the circuit input terminal. The second transistor M2 of reverse conduction type connected to (IN), the third transistor M3 of the conductivity type as long as the drain is connected to the circuit output terminal OUT and the gate is connected to the circuit input terminal. A current-current conversion circuit 1a for outputting a current proportional to a drain current to the circuit output terminal, and power supply voltage supply means VDD and VSS for operating the first to third transistors and the current-current conversion circuit. And the output current of the current-current conversion circuit in the steady state and the drain current of the third transistor are set by the output voltage of the constant voltage source.

Embodiment of the Invention

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings. FIG. 1 shows a first room form, and the output circuit 1 supplies the power supply voltage VDD through the NMOS transistor M1, the PMOS transistor M2, the NMOS transistor M3, and the current-current conversion circuit 1a. Is connected to a voltage source that supplies. The drain of the transistor M2 is connected to a voltage source for supplying a power supply voltage VSS. The gate of the transistor M1 is connected to the voltage source VSS via a voltage source V1 that applies a predetermined voltage described later. The gate of the transistor M2 is connected to the input terminal IN. The drain of the NMOS transistor M3 is connected to the voltage source VSS via the output terminal OUT and the current-current conversion circuit 1a, the source of which is connected to the voltage source VSS, and the gate thereof is the input terminal IN. ) Is connected.

The current-current conversion circuit 1a flows a current proportional to the current flowing in one terminal to the other terminal. Specifically, it is realized by the current mirror circuit described later.

The circuit operation of this configuration will be described. First, in the output circuit, the transistor M1 is a gate ground and the transistor M2 is a source follower. The gate ground transistor M1 operates under the gate bias V1. When the gate-source voltage of the transistor M1 is Vgs1, the source potential becomes a constant voltage of V1-Vgs1. The drain current of the source follower transistor M2 is determined by the gate-source voltage Vgs2 (= V1-Vgs1-IN). The drain current of the transistor M2 becomes the drain current of the transistor M1, and becomes the current of one side of the current-current conversion circuit 1a. The current generated in the series circuit of the source follower and gate ground transistor of this configuration has the advantage that it does not change depending on the power supply voltage and the transistor characteristics.

The input signal IN is applied to the gate of the transistor M2 and the gate of the transistor M3. As the voltage level of the input signal increases, the drain current of the NMOS transistor M3 increases. On the other hand, as the voltage level of the input signal IN increases, the drain current of the PMOS transistor M2 decreases. The drain current of the PMOS transistor M2 becomes the current Ib flowing through one terminal of the current-current conversion circuit 1a, and reduces the current Ic proportional to the current Ib output from the other terminal. Let's do it.

As a result, when the input voltage IN increases, the difference current between the increased drain current of the transistor M3 and the reduced current Ic is output from the output terminal OUT to the outside. Similarly, when the input voltage IN decreases, the difference between the reduced drain current of the transistor M3 and the increased current Ic is output from the output terminal OUT to the outside.

In this output circuit, when the voltage at the output terminal OUT is in a balanced state, that is, no current flows from the output terminal to the load (not shown) due to no input signal IN component, the output terminal ( When OUT) is almost halfway between the power supply voltages VDD and VSS, the drain current of the transistor M3 and the output current (bias current: Ic) of the current-current conversion circuit 1a are the same. At this time, the drain current of the transistor M3 is determined by applying a voltage dropped from the voltage source V1 by two gate-source voltages Vgs1 + Vgs2 of the transistor M1 and the transistor M2 to the gate.

The output current Ic is proportional to the drain current of the transistor M2 via the current-current conversion circuit 1a. As described above, the drain current of the transistor M2 is such that the voltage difference between the reference voltage V1 and the voltage at the node of the input terminal IN is the sum of the voltages between the gates of the transistors M2 and M1 and the source of the transistor M1. Is determined by the relationship.

Therefore, the drain current of the transistor M2 and the drain current of the transistor M3 in the steady state can be set by the voltage V1, and the current-current conversion circuit 1a in the steady state is determined by appropriately determining the current conversion ratio. The output current Ic and the drain current of the transistor M3 can be set equal.

FIG. 2 shows a specific configuration example of the current-current conversion circuit 1a and the voltage source 2 shown in FIG. In Fig. 2, parts corresponding to those in Fig. 1 are denoted by the same reference numerals, and description of these parts is omitted.

The current-current conversion circuit 1a is constituted by a current mirror circuit composed of PMOS transistors M11 and M12. The so-called output current ratio of the current mirror circuit can be realized by appropriately setting the area ratios of the transistors M11 and M12.

In the voltage source 2, the current source 10, the NMOS transistor M21, the PMOS transistor M22, and the NMOS transistor M23 are connected in series with each other, and the power supply voltages VDD and VSS are connected to both ends of the series circuit, respectively. It is composed. Each of the transistors M21 to M23 is called a diode connection. The voltage V1 is obtained at the gate of the transistor M2 by driving the diode-connected transistors M21 to M23 with the current source I0. The other configuration is the same as the circuit shown in FIG.

The operation related to the sink current in the output circuit with the voltage source 2 having such a configuration will be described.

First, when the voltage at the output terminal OUT is in an equilibrium state (intermediate voltage between the power supply voltages VDD and VSS), consider a condition (a sink current equal to 0) in which the drain current of the transistor M3 is equal to the drain current of the transistor M12. Let's see.

As described above, the drain current of the transistor M3 is determined by the voltage of the node of the input terminal IN in the steady state, which becomes the gate-source voltage Vgs3. The drain current Ic of the transistor M12 is proportional to the drain current Ib of the transistor M2 flowing through the transistor M11 constituting the current mirror circuit. The drain current Ib of the transistor M2 is determined by the gate-source voltage Vgs2. The gate-source voltage Vgs2 is determined by the reference voltage V1, the gate-source voltage Vgs22 of the transistor M1, and the voltage of the node of the input terminal IN. Since the output voltage V1 of the voltage source 2 is set by the output current Ia of the current source I0, the current Ib proportional to the output current Ia of the current source I0 drains the transistor M2. It is possible to set the current.

This is explained further. In the circuit loop made up of the power supply VSS → transistor M → transistor M2 → transistor M1 → V1 → transistor M21 → transistor M22 → transistor M23 → power supply VSS. ,

The relationship is established. For simplicity, assuming that the mirror current ratio is 1: 1 (described later in the case of 1: m), the transistors M1 and M21, the transistors M2 and M22, and the transistors M3 and M23 are formed of transistors having the same characteristics. Due to the symmetry of the drain current of the transistor M1 and the drain current of the transistor M21, the drain current of the transistor M2 and the drain current of the transistor M22 become equal. The drain currents of the transistors M22 and M23 are common and are the same as the output current Ia of the current source 10. As a result, the drain currents of the transistors M3 and M12 in the steady state become equal.

In such a configuration, the bias currents Ib and Ic in the steady state of the output circuit can be arbitrarily set by the current source I0. Moreover, it is hard to be influenced by a change in the characteristics of the transistor and a change in the power supply voltage.

3 shows another embodiment of the present invention. In Fig. 3, parts corresponding to those in Fig. 1 are denoted by the same reference numerals, and description of these parts is omitted. In this example, the current detection circuit side of the current-current conversion circuit 1a is inserted between the drain side of the transistor M2 and the power supply VSS, and the current output circuit side of the circuit 1a is connected to the power supply VDD. ) And the output terminal (OUT). The other configuration is the same as that of FIG.

4 shows a specific configuration of the current-current conversion circuit 1a shown in FIG. The current-current conversion circuit 1a is constituted by a current mirror circuit composed of transistors M11 and M12 and transistors M13 and M14. In this configuration, the drain current of the transistor M2 (=) The drain current of the transistor M11 (proportion) The drain current of the transistor M12 (=) The drain current of the transistor 13 (proportion) The transistor M14 ) Is the drain current Ic. For this reason, it is possible to set a large current ratio between the drain current Ib of the transistor M11 and the drain current Ic of the transistor M14.

Also in this configuration, it is possible to set the drain currents of the transistors M14 and M3 by the output voltage V1 of the voltage source 2, and thus the current source I0.

5 shows another embodiment. In Fig. 2, parts corresponding to those in Fig. 2 are denoted by the same reference numerals, and description of these parts is omitted.

In this example, the signal amplitude that can be input is made larger by setting the potential of the node of the input terminal IN in the output circuit shown in FIG.

For this reason, in this example, a current mirror circuit composed of the NMOS transistor M4 and the current source I1 is inserted between the gate of the transistor M3 and the node of the input terminal IN. When the voltage at the node of the input terminal IN is VIN and the gate-source voltage of the transistor M4 is Vgs4, VIN = Vgs3 + Vgs4. In addition, Vgs3 = V2-Vgs1-Vgs2-Vgs4. Due to the voltage drop caused by the added level shift circuit, the potential VIN of the node of the input terminal IN rises. In this case, the voltage source 2 outputting the voltage V2 can be configured by, for example, a series circuit of four transistors M21 to M24 (not shown) diode-connected with the current source 10. Each group of the transistors M1 and M21, the transistors M2 and M22, the level shift transistors M4 and M23, and the transistors M3 and M24 can be formed to have corresponding characteristics, respectively.

Further, the level shift amount (voltage drop amount) can be set larger by inserting one or a plurality of diode-connected transistors (not shown) between the gate of the transistor M3 and the source of the transistor M4. The number of diode-connected transistors in the voltage source 2 may be selected corresponding to the level shift amount.

6 shows another embodiment. In Fig. 4, parts corresponding to those in Fig. 4 are denoted by the same reference numerals, and description of these parts is omitted.

In this example, the gate voltage and the source voltage of the transistor M2 in the output circuit shown in FIG. 4 are set relatively high to increase the drain-source voltage of the transistor M2.

For this reason, in this example, the current mirror circuit composed of the PMOS transistor M5 and the current source 12 is inserted between the gate of the transistor M2 and the node of the input terminal IN. If the voltage at the node of the input terminal IN is VIN and the gate-source voltage of the transistor M5 is Vgs5, V3-Vgs1 = VIN + Vgs2 + Vgs5, Vgs2 = V3-Vgs1-Vgs5-VIN (= Vgs3). do. Therefore, the drain-source voltage of the PMOS transistor M2 increases by the amount of voltage drop by the added level shift circuit. In this case, the voltage source 2 that outputs the voltage V3 is configured by, for example, a series circuit of four transistors M21 to M24 (not shown) diode-connected with the current source I0. Each group of the transistors M1 and M21, the transistors M2 and M22, the transistors M5 and M23, and the transistors M3 and M24 can be formed to have corresponding characteristics, respectively.

Further, the level shift amount (voltage drop amount) can be set larger by inserting one or a plurality of diode-connected transistors (not shown) between the gate of the transistor M2 and the source of the transistor M5. The number of diode-connected transistors in the voltage source 2 may be selected corresponding to the level shift amount.

5 and 6, the input signal IN can be applied to the gate of the transistor M2 or M3 via a level shift circuit. In addition, a configuration having two level shift circuits for applying an input signal IN to both gates of the transistors M2 and M3 via a level shift circuit is also possible.

7 shows another embodiment. In Fig. 2, parts corresponding to those in Fig. 2 are denoted by the same reference numerals, and description of these parts is omitted.

In this example, the phase compensation capacitor C1 is provided between the gate and the drain of the transistor M3 (between the node of the input terminal IN and the node of the output terminal OUT). The operation of this circuit is the same as that of the output circuit shown in FIG.

8 shows another embodiment. In the figure, 1 is an output circuit, 2 is a reference voltage generator circuit, 3 is a differential amplifier circuit, and 4 is a constant current source bias circuit.

The output circuit 1 includes a current mirror circuit composed of an NMOS transistor M1, a PMOS transistor M2, a transistor M3, and transistors M11 to M14, and a capacitor C2 for performing phase compensation of the transistor M14. ) And a capacitor C3 and a resistor R3 for performing phase compensation of the transistor M3.

The reference voltage generator 2 is composed of a PMOS transistor M20, an NMOS transistor M21, a PMOS transistor M22, and an NMOS transistor M23. Each of the transistors M21 to M23 is so-called diode connected to form a series circuit. The transistor M20 supplies current to this series circuit, and generates a predetermined voltage from the ground level VSS to the drain of the transistor M21. The output current of the constant current transistor M20 is controlled by the constant current source bias circuit 4.

The differential amplification circuit 3 includes PMOS transistors M31 and M32 serving as differential transistor pairs, a PMOS transistor M30 for supplying a constant current to the differential transistor pair, a transistor M33 to which respective sources are connected to respective drains of the differential transistor pair, and It is comprised by the current mirror circuit comprised by M34. Both gates of the differential transistor pairs M31 and M32 serve as input terminals of a drive amplifier circuit, and input signals IN + and IN- whose voltages complementarily change are applied. The drain of the transistor M32 (drain of the transistor M34) becomes the output terminal. This output terminal is connected to the gates of the transistors M2 and M3 described above.

The constant current source bias circuit 4 is constituted by the transistor M40 and the current source I3. Transistor M40 and transistors M20 and M30 form a current mirror circuit. Therefore, a current proportional to the drain current I3 of the transistor M40 is output from the transistors M20 and M30 as constant current sources.

In the case where the above-described circuit is actually configured as a semiconductor integrated circuit, the size (ratio) and the like of each transistor element are set in consideration of the output current and the consumption current. Therefore, description will be given of the embodiment in the case where the transistor size ratio is considered.

In the case of the steady state (no current flows out from the output terminal OUT and the voltage of the output terminal is near the midpoint of the power supply voltage VDD-VSS), the operating point of the circuit is determined by satisfying the following two conditions.

In the circuit loop of power supply (VSS) → transistor (M3) → transistor (M2) → transistor (M1) → transistor (M21) → transistor (M22) → transistor (M23) → power supply (VSS), the following relationship is established. do.

Here, Id14 is a drain current of transistor M14, and Id3 is a drain current of transistor M3.

The drain current Id of the MOS transistor, when the operating point is in the five-pole region,

Becomes Where kp is an integer determined by the process, W is the gate width of the transistor, L is the gate length, and Vth is the threshold voltage. Therefore, when the gate-source low voltage Vgs is the same, the drain current Id is proportional to the transistor size W / L.

The transistor size ratio is set as follows.

Transistor M40: Transistor M20 = 1: i

Transistor M21: Transistor M1 = 1: j

Transistor M22: Transistor M2 = 1: k

Transistor M23: Transistor M3 = 1: l

Transistor M11: Transistor M12 = 1: m

Transistor M13: Transistor M14 = 1: n

Here, i to n are positive real numbers. The drain currents of the transistors M20 to M23 are set to Ia, the drain currents of the transistors M1, M2, and M11 are set to Ib, and the drain currents of the transistors M14 and M3 are set to Ic.

The current ratio of the current mirror circuit constituted by the transistors M11 to M14, that is, the ratio of the drain currents of the transistors M11 and M14 to be 1: m × n. Therefore, Equation (2) is the drain current Id1 x m x n of the transistor M1 = the drain current Id14 of the transistor M14.

to be.

Under these conditions, a method of determining the operating point in the steady state will be described.

First, the simplest case of i = j = k = l = n = m = 1 will be described.

Ia = I3 from the conditions of formula (4) and i = 1, and Ib = Ic from the formula (3) and m × n = 1.

Therefore, in order to satisfy the above formula (1), Ia = Ib = Ic. Therefore, the bias currents Ib and Ic of the output circuit in the steady state are Ib = I3 and Ic = 13. As a result, it can be seen that the bias current can be set by the current source I3.

Next, consider the case where j = k = 1 and 1 = m × n.

From the above formula (3), Ic = Ib × m × n = Ib × 1

In order to satisfy this condition, j = k = 1 and the above expression (1), Ia = Ib must be satisfied.

In addition, since Ia = I3 × i, Ib = I3 × i and Ic = I3 × i × l.

As in the above example, by appropriately setting the transistor sizes (ratios) of the reference voltage generating circuit 2 and the output circuit 1, it is possible to arbitrarily set the value of each current in the steady state.

9 shows another embodiment. In Fig. 8, parts corresponding to those in Fig. 8 are denoted by the same reference numerals, and description of these parts is omitted.

In the example shown in FIG. 9, the output circuit 1, the first reference voltage generator circuit 2, the differential amplifier circuit 3, the constant current source bias circuit 4, and the second reference voltage generator circuit 5 are used. It has an associative amplifier. The output circuit 1 and the reference voltage generator 2 are configured in the same way as the circuit of FIG. 8, but the differential amplifier circuit 3 is formed by a folded cascode circuit composed of transistors M30 to M38. It is composed.

In this differential amplifier circuit 3, the difference between two complementary outputs of the differential circuit constituted by the constant current source transistor M30, the differential transistor pairs M31 and M32 is taken out by the current mirror circuit composed of the transistors M33 to M38. do. A constant voltage is applied to each gate of the transistors M35 and M36 from the reference voltage generation circuit 5 to operate both transistors to the gate ground. The drain of the PMOS transistor M36 (the drain of the NMOS transistor M38) becomes the output terminal of the differential amplifier circuit 3 and is connected to the gates of the transistors M2 and M3 of the output circuit 1.

In this type of circuit, there is an advantage that the voltage amplitude level of the output signal can be large even with a power source having a comparatively low voltage.

The reference voltage generating circuit 5 is constituted by a transistor M40 and a current source transistor M41 which are diode-connected.

The constant current source bias circuit 4 is constituted by the transistors M51 to M53 constituting the constant current source I4 and the current mirror circuit. Then, the transistors M41, M33, M34 and M20 as the constant current source are driven.

In the operational amplifier circuit shown in FIG. 9, similarly to the circuit shown in FIG. 8, the area ratio of the transistor elements can be appropriately set. Then, the bias currents Ia, Ib, ic can be set to a desired value by the current value of the current source I4.

The example in which the current ratio of the current mirror circuit is set to "1: 1" and "1: n (definite real number)" has been described with reference to the circuit of FIG. 8. Also in the circuit example shown in FIG. 9, the circuit design can be performed by appropriately setting the mirror current ratio.

In this way, according to the output circuit of the present invention, since the generation of the sink current in the steady state is suppressed in the circuit structure, the current consumption is reduced. Further, the bias currents Ia, Ib, and Ic of the output circuit can be easily set by setting the current source I0 of the reference voltage generating circuit or the current sources I3 and I4 of the constant current source bias circuit. In addition, the sink current is suppressed as long as the parallel state is maintained even if the transistor characteristics or the power supply voltage change. Furthermore, the current generated by the circuit composed of the source follower (transistor M2) and the gate ground circuit (transistor M1) changes according to the change in the power supply voltage and the change in the characteristics of the transistor. Excessive consumption of bias current is also suppressed.

It is noted that reference numerals denoted together with the components of the claims of the present application are for the purpose of facilitating the understanding of the present invention and are not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the output circuit of the present invention, the sink current in the steady state can be suppressed and the bias current level of the output circuit can be easily set. Therefore, the current consumption of the load in the steady state can be reduced while increasing the maximum output current supplied to the load.

Claims (24)

As long as the gate is connected to the constant voltage source 2, the conductive first transistor M1 and the source are connected to the source of the first transistor, and the reverse conductive second transistor is connected to the circuit input terminal IN. (M2), as long as the drain is connected to the circuit output terminal OUT and the gate is connected to the circuit input terminal, a current proportional to the drain current of the conductive transistor type third transistor M3 and the second transistor is supplied to the circuit output terminal. An output current of the constant voltage source 2 including a current-current conversion circuit 1a to be output, power supply voltage supply units VDD and VSS for operating the first to third transistors and the current-current conversion circuit. And an output current of the current-current conversion circuit (1a) and a drain current of the third transistor are set by the voltage. The level shift circuit of claim 1, wherein a level shift circuit is formed between the gate of any one of the second and third transistors and the circuit input terminal, or between each gate of the second and third transistors and the circuit input terminal. An output circuit comprising M4, I1; M5, I2) inserted therein. 2. The output circuit according to claim 1, wherein the constant voltage source is constituted by a series circuit including at least a constant current source I0 and at least a second to sixth transistors M21, M22, and M23 connected diodes. . 3. The constant voltage source of claim 2, wherein the constant voltage source includes at least one constant current source, diode connected fourth through sixth transistors, and one or more transistors connected by diodes carrying a voltage drop corresponding to a level shift amount. An output circuit comprising a series circuit. 4. The method of claim 3, wherein the first to third transistors are formed to have substantially the same electrical characteristics as the fourth to sixth transistors, respectively, and the drain currents of the second and third transistors are set by the constant current source. Output circuit characterized in that. 5. The method of claim 4, wherein the first to third transistors are formed to have substantially the same electrical characteristics as the fourth to sixth transistors, respectively, and the drain currents of the second and third transistors are set by the constant current source. Output circuit characterized in that. 4. The method of claim 3, wherein each of the first and fourth transistors, the second and fifth transistors, and the third and sixth transistors is formed to have a predetermined device area ratio, respectively. And the drain current is set to be greater than the drain current of the second transistor while being equal to the output current of the current-current conversion circuit. 5. The method of claim 4, wherein each of the first and fourth transistors, the second and fifth transistors, and the third and sixth transistors is formed at a predetermined device area ratio, and each of the third transistors in a steady state. And the drain current is set to be greater than the drain current of the second transistor while being equal to the output current of the current-current conversion circuit. 2. An output circuit according to claim 1, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 3. An output circuit according to claim 2, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 4. An output circuit according to claim 3, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 5. An output circuit according to claim 4, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 6. An output circuit according to claim 5, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 7. An output circuit according to claim 6, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. 8. An output circuit according to claim 7, wherein phase compensation circuits (C1, C2, C3) are provided between the input terminal and the output terminal. 9. An output circuit according to claim 8, wherein phase compensation circuits (C1, C2, C3) are provided between said input terminal and said output terminal. The output circuit of claim 1, wherein an output voltage of a differential amplifier is applied to the circuit input terminal. The output circuit according to claim 2, wherein the output voltage of the differential amplifier is applied to the circuit input terminal. 4. The output circuit of claim 3, wherein an output voltage of the differential amplifier is applied to the circuit input terminal. 5. An output circuit according to claim 4, wherein the output voltage of the differential amplifier is applied to the circuit input terminal. 6. The output circuit of claim 5, wherein an output voltage of the differential amplifier is applied to the circuit input terminal. 7. An output circuit according to claim 6, wherein the output voltage of the differential amplifier is applied to the circuit input terminal. 8. The output circuit of claim 7, wherein the output voltage of the differential amplifier is applied to the circuit input terminal. 17. The output circuit of claim 16, wherein the output voltage of the differential amplifier is applied to the circuit input terminal.