KR100227776B1 - Image format transform filter - Google Patents

Abstract

The present invention relates to a digital filtering device used to convert the format of an image in an MPEG4 system. Unlike the conventional decimation filter, the present invention provides a filter represented by two shifts, thereby reducing the number of resources with improved performance. The present invention relates to a video format conversion filtering device that can be implemented in a VLSI design, which can reduce the cost.

Description

Video format conversion filtering device

The present invention relates to a picture format conversion filtering device, and more particularly, to a digital filtering device used for converting a picture format in a Motion Picture Experts Group 4 (MPEG4) system.

There are many standardized image formats that exist worldwide. Among them, MPEG4 does not place a significant limitation on the input video format, so it is necessary to convert between video formats for digital signal processing. For this purpose, interpolation / decimation techniques are used, and the use of digital filters is essential. The key part of the digital filter implementation is the multiplication of the filter coefficient and the input pixel data. The multiplier used is composed of multiple adders, subtractors and shifts.

There is no limitation on the format of the input video to be dealt with in the MPEG4. However, due to compatibility issues, several formats are recommended as standard (see MPEG 96 Tampere Conference Document No. N1277, MPEG-4 Video Verification Model 3.0).

1.ITU-R format: luminance signal size 720 480 or 720 576

Chromaticity Signal Size 360 240 or 360 244

2. CIF format: luminance signal size 352 288, chromatic signal size 176 144

3.QCIF format: luminance signal size 176 144, chromatic signal size 88 72

4. SQCIF format: luminance signal size 128 96, chromatic signal size 64 48

The conversion between the image formats is performed by an interpolation / decimation technique that changes the number of samples in the digital signal processing. The most basic need for this is the use of an appropriate digital filter for each conversion method. Already at the MPEG 95 Dallas Conference, findings using filters such as Table 1 have been published (MPEG 95 Dallas Conference Document No. MPEG95 / 0332).

In Table 1, in the case of A, the filter taps of 5, 11, 11, and 5 and the divisor of 32 means that the filter coefficients are 5/32, 11/32, and 5/32. . Factor 1/2 and 3/5 mean 2: 1 and 5: 3 decimation respectively. That is, 200 lines are reduced to 100 lines and 500 lines are reduced to 300 lines. Therefore, A, B, C, D, E and F of Table 1 are used for the conversion of the image format as shown in the following example.

1. Conversion from ITU-R 601 to CIF / SIF

end. In case of luminance signal

720 240-B 352 240-D 352 288

704 288-B 352 288

I. For chroma signal

352 240-B 176 240-D 176 288-A 176 144

352 288-B 176 288-A 176 144

2. Conversion from ITU-R 601 to QCIF

end. In case of luminance signal

720 240-C 176 240-E 176 144

704 288-C 176 288-B 176 144

I. For chroma signal

352 240-C 88 240-E 88 144-A 88 72

352 288-C 88 288-E 88 144-A 88 72

Where for example 88 240-E 88 144 is 88 The 240-sized image is passed through the filter named E in Table 1 above. 144 images are obtained. In the case of MPEG2, some filters are proposed to convert these video formats. Among them, the filter shown in Table 2 below was presented in a 2: 1 decimation to reduce the size of the image in half (see ISO / IEC JTC1 / SC29 / WG11 / NO400, MPEG2 Test Model 5).

Digital image data is very difficult to process at a given time because its amount is very large. Also, the process of implementing it in hardware is more complicated than other fields. Therefore, each component included in the apparatus for processing image data should have low complexity and high speed.

Therefore, the present invention provides better performance and hardware than the 5: 3 decimation filter E of Table 1 and the 2: 1 decimation filter of Table 2 by allowing each tap to be composed of two shifts or less than one adder. It is an object of the present invention to provide a video format conversion filtering device that is simple to implement.

According to the present invention for achieving the above object, when the filter of the MPEG Work Group is configured by hardware, the first, second and third taps are composed of two shifts and one adder, and the fourth tap is one shift. If the filter of MPEG Work Group is implemented in hardware, it is characterized by a total of 20 shifts and 9 adders for each tap.

1 is a block diagram of a filter for implementing a video format conversion filter in hardware.

2 is a block diagram of a filter tab for implementing a filter of an existing MPEG Work Group.

3 is a block diagram implementing a tap of the filter according to the present invention.

* Explanation of symbols for main parts of the drawings

100: multipliers 201, 201, 203, 301 and 302: shift

204, 205, and 303: adder

Hereinafter, with reference to the accompanying table and drawings will be described in detail the present invention.

A key part of implementing a digital filter in hardware is the multiplication of filter coefficients and inputs. The multiplier used is composed of multiple adders or subtractors. For example, when h3 of the 2: 1 decimation filter of Table 2 is multiplied with a certain image input, 29/256 is 0.00011101, so hardware that adds all the 4-bit, 5-bit, 6-bit, and 8-bit shifted input values is required. . In this case, Canonic Signed Digit expression is used to configure the hardware more simply. However, since 29/256 is 2-3 + 2-6-2-8, multiplying the coefficients and inputs requires a device that shifts the inputs by 3, 6, and 8 bits, and adds and subtracts them.

FIG. 1 is a structural diagram of a filter for implementing an image format conversion filter in hardware, and illustrates a finite impulse response (FIR) filter in a transposed form.

As in the filter of Table 2, if the number of filter taps is seven, as in the filter, seven multipliers 100 are required. Here, when the multiplier 100 multiplies 2-3 + 3-6-2-8 by the input, it is composed of three shifts and two adders, as shown in FIG. 2. The three shifts 201, 202, and 203 shift each input by 3, 6, and 8 bits, and the two adders 204 and 205 serve to add or subtract these results, thus multiplying the multiplier 100 of FIG. Plays a role.

In order to determine the complexity of the hardware device as a whole, each coefficient of Table 2 is represented by a canonical sine digit as shown in Table 3 below. Since the filters required for image processing are linear phase filters as shown in each table, the number of filter taps ( For 2L + 1), the actual number of multipliers required for the hardware implementation is (L + 1).

That is, in Table 3, four multipliers of h0, h1, h2, and h3 are required. As shown in Table 3, h0, h1, and h3 are composed of three shifts 201, 202, and 203 and two adders 204 and 205, respectively, as shown in FIG. The total number of hardware specifications is 9 shifts and 6 adders.

Similarly, in order to determine the complexity of the filter E of Table 1 used in MPEG4, each coefficient is represented in sine digit form as shown in Table 4 below.

From the digit representation of Table 4, it can be seen that the MPEG4 5: 3 decimation filter requires 29 shifts and 18 adders.

In the present invention, unlike the conventional filter shown in Tables 3 and 4, by presenting a filter in which each coefficient is represented by only two shifts, the hardware complexity is reduced and the performance speed is also increased.

Of course, it was confirmed through experiments that the filter performance is almost the same as the existing filter or in some cases better performance. Here, Tables 5 and 6 below can replace the conventional 2: 1 and 5: 3 decimation filters shown in Tables 3 and 4 as the filters of the present invention. For comparison, the existing coefficients are also shown in each table.

As can be seen in Table 5 above, when the filter proposed by the existing MPEG2 Work Group is implemented in hardware, a total of three shifts, three shifts, three shifts, three shifts, two shifts, zero shifts, The filter of the present invention requires 1, 2, 2, 2 total 7 shifts, 0, 1, 1, 1 total 3 Only adders are needed.

Similarly, as shown in Table 6, in the hardware implementation of the filter proposed by the existing MPEG2 Work Group, two, two, two, three, two, two, four, three, three taps for each tap. Total of 29 shifts, 3, 3, 3, 18, 1, 1, 1, 2, 1, 1, 3, 2, 2, 2, 2 While an adder is required, the filter of the present invention includes 20 shifts of 2, 2, 2, 1, 1, 2, 2, 2, 2, 2, and 2 for each tap, Only 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1 total adders are needed.

The meaning of the present invention is that, firstly, when implementing two types of filters in hardware, the number of shifts and adders required as a whole is reduced as described above, thereby lowering the hardware complexity and thus reducing the manufacturing cost by reducing power consumption and chip area. Can be obtained.

Secondly, since the tap operation is performed with one, two or three adders in the conventional method, all the tap operations are performed with zero or one adder in the filter of the present invention, which greatly reduces the computation delay time. Significantly improved. For reference, the delay time is determined by the circuit path leading to the longest delay time. The existing filter of Table 5 passes through up to two adders, and in Table 6, through up to three adders. Each filter can be computed with one adder, resulting in shorter delay times.

That is, the filter of the present invention is simpler than the conventional filter shown in FIG. 2 because hardware can be implemented by two shifters 301 and 302 and one adder 303 as shown in FIG. Do. It also has the advantage that faster calculations are performed because the delay time required for addition is also short. That is, in the case of FIG. 2, the next input cannot be accepted until the two stages of additions 204 and 205 are performed. However, in the case of FIG. 3, the addition is performed in one step 303.

Here, some experiments were performed to show that the filter according to the present invention is superior in performance in terms of hardware cost and computational speed, but better than the filter proposed by the MPEG Work Group. First, in the case of the 2: 1 decimation filter of Table 5, the image used as the standard in the JPEG and MPEG Work Groups such as Lena, Mobile and Calendar is reduced by half using the MPEG Work Group filter and the invented filter, respectively. And compared with standard images of that size. The results show that PSNR is better when using the filter according to the present invention as shown in Table 7 below. In the case of 5: 3 decimation, there is no standard image of which size is reduced to 3/5. This means that a sine wave as shown in [Equation 1] is passed through each filter shown in Table 6, and it can be called its original signal. The performance is indirectly compared by calculating the error compared to the sine wave of the following Equation 2.

Experimental results for several w are shown in Table 8 below, the performance of the filter of the MPEG4 Work Group and other filters in the present invention was found to be almost the same.

The working principle of a digital filter consists of a series of filter coefficients and the input multiplication. And in the hardware implementation, the multiplier consists of adders, subtractors and shifts. At this time, the filter required for image processing is a linear phase filter, and when the number of filter taps is (2L + 1), the number of multipliers required for hardware implementation is (L + 1). That is, in Table 3, four multipliers of h0, h1, h2, and h3 are required. As shown in Table 3, h0, h1, and h3 are composed of three shifts 201, 202, and 203 and two adders 204 and 205, respectively, as shown in FIG. Therefore, the total number of hardware specifications needed to multiply the filter coefficients and inputs is nine shifts and six adders. In the same way, the sine digit representation in Table 4 shows that the MPEG4 5: 3 decimation filter requires 29 shifts and 18 adders.

In the present invention, unlike the conventional filter shown in Tables 3 and 4, by presenting a filter in which each coefficient is represented by only two shifts, the hardware complexity is reduced as well as the execution speed is increased. In other words, as shown in Table 5, the filter presented by the MPEG2 Work Group includes nine shifts and five adders, whereas the filter according to the present invention includes seven shifts and three adders. In addition, the filter proposed by the MPEG4 Work Group in Table 6 is composed of 29 shifts and 18 adders. However, it can be seen that the inventive filter is composed of 20 shifts and 9 adders. Thus, the invented filter is sufficiently implemented with two shifts 301 and 302 and one adder 303, as shown in FIG. 3, and therefore simpler and less expensive than the conventional hardware shown in FIG. In addition, the time required for addition is also short, which allows for faster calculations.

As described above, the filter according to the present invention has the advantage of being less expensive and faster in hardware implementation than the filter proposed by the MPEG4 Work Group. And the performance is also better. In addition, all the filter tabs are composed of two shifts and one adder, which is less expensive than the existing MPEG Work Group filters. Therefore, the filter tab can be designed to have a regular structure. Implementing the necessary decimation filters in hardware reduces the number of specifications required, resulting in lower complexity and higher performance.

Claims (1)

A tab of each filter used for 2: 1 and 5: 3 format conversion of an image is regularly arranged with two shifts and one adder, and each filter has the filter coefficients of Table 5 or Table 6 below. Image format conversion filtering device, characterized in that.