KR100224762B1 - A non-volatile semiconductor memory device having improved field-isolation property and method for producing the same - Google Patents

Abstract

A method of manufacturing a NAND nonvolatile semiconductor memory device is disclosed. The disclosed method is a photoresist film that opens a source line region between a bit line contact region between a string select transistor and a ground select transistor after an insulating film for insulating the plate and a polysilicon layer serving as the plate electrode are formed on the word line. Forming a pattern and then etching the exposed polysilicon layer and injecting channel stop ions through a portion of the insulating layer which appears through some etching of the polysilicon layer to enhance the electrical insulating properties of the bitline contact region. It features.

Description

Manufacturing method of nonvolatile semiconductor memory device with improved device isolation

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method for manufacturing a NAND flash nonvolatile semiconductor memory device.

In general, the nonvolatile semiconductor memory is divided into mask ROM, EPROM, EEPROM, and FLASH-EEPROM, among which, in particular, electrically With the ability to change information, low power consumption and the ability to flash erase stored data, Flash Epirom has recently been used not only for permanent memory in personal notebook computers but also for information storage media in portable terminals such as digital cameras and memory cards. As a result, the trend is in the spotlight.

Flash Ipyrom cells are typically single-bit memory cells that can have only one of two storage states: on or off. The information stored therein is stored in the memory cell. Input) is determined according to the state. Such a program is accomplished by changing the threshold voltage of the cell transistor (the minimum voltage that must be applied between the gate terminal and the source terminal of the transistor in order for the cell transistor to be turned on). In other words, a floating gate in a memory cell transistor (or two gates in a single memory cell transistor) forms an upper layer and a lower layer on the drain source channel region, and the upper portion of the memory cell transistor is called a control gate. By differentiating the amount of charge stored in the charge accumulation portion surrounded by the insulating material between the channel regions (control gate), the threshold voltage of each memory cell is changed, and thus the stored information state is divided into two. In order to read the information stored in each memory cell in such a memory device, it is necessary to check the storage state of the programmed memory cells. To this end, signals necessary to select and read a desired memory cell using a decoder circuit are applied to a circuit related to the memory cell. As a result, a signal of current or voltage according to the storage state information of the memory cell is obtained on the bit line. By measuring the current or voltage signal thus obtained, it is possible to distinguish the state information stored in the memory cell. The structure of the flash Y pyrom memory cell array is divided into NOR-type and NAND-type according to how the cells are connected to the bit line. do. In the case of the NOR-type, each memory cell is connected between the bit line and the ground line, whereas in the case of the NAND-type, many memory cells are connected in series through a select transistor between the bit line and the ground line. Is connected. In such a NAND flash Y pyrom, memory cells connected in series to the bit line and select transistors (string select transistors between the serially connected memory cells and the bit line, and the memory cells connected in series) are grounded. Ground transistors between lines) are often collectively referred to as strings.

In order to read the information stored in the memory cell of the NAND flash Y pyrom which is more dense than the NOR-type, the select transistors in the selected string must be turned on. Also, the control gates of the unselected memory cells in the string must be turned on. The terminal is provided with a voltage higher than the voltage applied to the control gate terminal of the selected memory cell. Accordingly, the unselected memory cells have a lower equivalent resistance value than the selected memory cell, and the current flowing from the corresponding bit line to the string depends on the state of information stored in the selected memory cell in the string. According to the information state stored in the selected memory cell, the voltage or current appearing on the bit line is sensed by a sensing circuit called a sense amplifier.

In the case of the NAND flash Y pyrom as described above, in order to operate the cell transistors in each string more stably without disturbing the operation of each other, between transistor elements during manufacturing or between elements to be located in the peripheral region and the cell region. Device isolation that ensures sufficient insulating characteristics should be realized. Due to the high integration of the memory, the distance between the elements is further reduced, so such device isolation becomes very important.

BACKGROUND OF THE INVENTION In the field of manufacturing semiconductor memories, conventional device isolation is a method of growing a local oxide film by performing a LOCOS process on a silicon substrate. In order to improve device isolation characteristics, the thickness of the local oxide layer must be thicker. The generation of thicker local oxides is possible only by increasing the separation distance between the oxides in proportion. However, sufficient securing of the separation distance is contrary to the high integration of the memory element. That is, in order to achieve high integration in the manufacture of NAND flash Y pyrom, the separation distance should be reduced. As shown in FIG. 1, the most vulnerable element isolation when the separation distance is reduced is a gap A between bit lines having contacts. The structure of FIG. 1 is disclosed under the title A NEW NAND CELL FOR ULTRA HIGH DENSITY 5V-ONLY EEPROMs, published on Symposium VLSI Technology pp33-34, 1988, pages 33-34.

Referring to FIG. 1, which shows a plan view of a typical NAND flash Y pyrom, the gap A shown in the dotted line is due to the width C of the bit line contact, and thus the separation distance of the transistor elements in the same length direction as the direction of the word line. It is always shorter. Therefore, the portion where device isolation is most vulnerable when the separation distance is reduced becomes the gap portion A. The gap portion A, which is the distance between the bit lines, is equal to the contact width C at the cell pitch F of the transistor element. This is the distance minus 2B, which is twice the active overlap margin B of the bitline contact. Therefore, for high integration, a manufacturing technique for increasing the insulation characteristics of device isolation without increasing the separation distance between the bit lines is urgently required.

Accordingly, it is an object of the present invention to provide an improved device isolation method for a nonvolatile semiconductor memory device.

Another object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device capable of enhancing the insulating property between bit lines.

Another object of the present invention is to provide a device isolation method of a nonvolatile semiconductor memory device, which is advantageous for high integration and improves electrical isolation between devices.

1 is a plan view showing a cell array arrangement of a conventional nonvolatile semiconductor memory device.

2 is a plan view showing a cell string of a nonvolatile semiconductor memory device according to the present invention;

3 to 7 are vertical cross-sectional views shown for explaining the sequence of the manufacturing process for manufacturing the cell string structure of FIG.

A manufacturing method according to the present invention for achieving the above object, the device between the elements to be formed in the cell region and the peripheral region by forming a plurality of field oxide film to isolate the active regions from each other on the semiconductor substrate and performing a photolithography process Implanting impurity ions through the field oxide film for separation; Sequentially forming a word line functioning as a gate oxide film, a floating gate, a dielectric film, and a control gate on the active region; Applying an insulating film for insulation of the plate as a whole and forming a polysilicon layer thereon that functions as a plate electrode; Forming a photoresist pattern that opens the source line region between the bit line contact region and the ground select transistor between the string select transistors, and then etching the exposed polysilicon layer, and enhancing the electrical insulation characteristics of the bit line contact region. In order to inject a channel stop ion through a portion of the insulating film that appears through a portion of the etching of the polysilicon layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, description of preferred embodiments according to the present invention will be described with reference to the accompanying drawings. It should be noted that like reference numerals in the drawings indicate the same element or same layer wherever possible.

2 is a plan view illustrating a cell string of a nonvolatile semiconductor memory device according to the present invention. 2 shows a planar view of only a cell array region in which one string is formed on an active region, and no peripheral circuit region is shown. In FIG. 2, T refers to the longitudinal bitline contact region of bitline 10, and BC refers to the bitline contact. In addition, BLM refers to the bit line metal layer. The plurality of word lines WL1-WLn are disposed perpendicular to the bit line 10 and serve as control gates of cell transistors. Lower portions of the plurality of word lines WL1-WLn are each disposed with a polysilicon layer serving as a floating gate. SSL is a portion that becomes the gate of the string select transistor, and GSL is a portion that becomes the gate of the ground select transistor.

3 to 7 are vertical cross-sectional views illustrating the sequence of the manufacturing process for manufacturing the cell string structure of FIG. Referring to FIG. 3, a field oxide film 201 and an active region (active region) 151 formed at a predetermined depth on the semiconductor substrate 101 are shown. It is to be understood that the vertical cross-sectional structure of FIG. 3 is a cross section of an initial sequence process of cutting the plan view of FIG. 2 based on the cutting line A-A '. The oxide film 201 is an oxide film serving as an element isolation film, which is formed by performing a conventional LOCOS process. The oxide film 201 is a film for electrically isolating the active regions to be formed in the semiconductor substrate from each other, and has a thickness of about 3000 to 6000 microns, and is formed in plural at regular intervals. Here, it can be seen that the thickness of the field oxide film corresponding to the section T of FIG. 2 is thinner than the thickness of the region where the cell string is to be positioned in order to increase the insulating property between the bit lines in the process described below. Therefore, this is shown as a separate reference numeral 211. Formation of the film 211 can be realized by appropriately adjusting the thickness of the nitride film during local oxidation.

In FIG. 4, after forming a plurality of field oxide films and performing a photolithography process, impurity ions such as boron ions are implanted through the field oxide film 201 for device isolation between devices to be formed in a cell region and a peripheral region. appear. In this case, the injection energy is about 130 ~ 180KeV and the dose is about 1.0E 13 ~ 2.0E13 # / cm2. As a result, the ion implantation region 301 in FIG. 4 is obtained. In view of the thickness of the ion implantation region 301, the lower portion of the field oxide layer 201 is generally thin, while the lower portion of the field oxide layer 211 and the lower portion of the active region 151 are thicker than the lower portion of the oxide layer 201.

FIG. 5 shows a solution for forming a floating gate 501, a dielectric film 601, and a word line 701 functioning as a control gate after forming a gate oxide film on the active region, polysilicon, ONO, and polysilicon. It shows the process of applying each in turn. The word line layer 701 is optionally covered with a photoresist 961 as a photoresist for patterning the gate layers. When the photolithography process is performed on the resultant of FIG. 5 and the photoresist 961 is removed, the structure of FIG. 6 appears.

In FIG. 6, a floating gate 501, a dielectric film 601, and a control gate 701 which are sequentially etched are shown. Although the floating gates 601 appear to be on the field oxide film 201, it is to be understood that the floating gates 601 are formed on the active region 151 and extend to the oxide film 201 in consideration of the cut line of FIG. 2. Meanwhile, since the transistor to be formed on the leftmost side and the transistor to be formed on the right side of FIG. 6 should be string select transistors and ground select transistors, they should not have floating gates like memory cell transistors. Accordingly, the layers 701 formed on the left and right sides of FIG. 6 are respectively contacted through the layer 501 and the conductive layer 602. The conductive layer 602 may be formed by making a contact hole at a corresponding position before applying the polysilicon layer 701 of FIG. 5 and then applying the layer 701 as a whole. Thus, the leftmost and rightmost layer 701 is integrated with the layer 501 to form one gate.

After forming the structure of FIG. 6 by performing the process, in FIG. 7, the insulating film 801 for insulating the plate is applied as a whole, and the polysilicon layer 901 serving as the plate electrode is applied as a whole. Thereafter, a photoresist pattern 970 is formed to open a bit line contact region between a string select transistor and a source line region between a ground select transistor, and then the exposed polysilicon layer 901 is etched. Here, the insulating film 801 is a CVD oxide film, and has a thickness of about 300 to 500 kPa. In addition, the polysilicon layer 901 has a thickness of about 1000 to 1500 kPa. Here, the layer 901 may be formed of polyside by applying a metal having high conductivity together with polysilicon. Importantly, a channel stop ion is implanted into the ion implantation region 301 under the field oxide layer 211 through a portion of the insulating layer 801 which appears through partial etching of the polysilicon layer in order to further enhance the electrical insulation characteristics of the bit line contact region. This is carried out. On the other hand, the lower portion of the active region 151 may be etched to the insulating film 801 and the channel stop ion may be implanted in the same manner as described above. Ions implanted to enhance device insulation in the bitline contact region are, for example. Boron, a type of ion, can be used. When the ion is implanted, the thickness of the membrane 211 is about 3000 mm 3, so that device isolation may be optimal without a separate mask. In addition, the dose and energy to be ion implanted can be selectively adjusted according to the thickness of the membrane and the separation distance of the device. Similar to the region 952, the concentration of the region 950 can be selectively adjusted to further reduce the separation distance required for device isolation, thereby achieving high integration.

As described above, according to the present invention, the channel stop ion is implanted through a portion of the insulating layer that appears through partial etching of the polysilicon layer, thereby improving the electrical insulation characteristics of the bit line contact region.

Claims (4)

In a device isolation method of a nonvolatile semiconductor memory device, an insulating film for insulating a plate and a polysilicon layer serving as a plate electrode are formed on a word line, and then a bit line contact region and a ground select transistor between the string select transistors. A portion of the insulating film formed by etching a portion of the polysilicon layer to form a photoresist pattern opening the source line region therebetween, and then etching the exposed polysilicon layer and increasing the electrical insulating properties of the bitline contact region. Injecting the channel stop ion through. In the method of manufacturing a nonvolatile semiconductor memory device: Implanting impurity ions through the field oxide layer to form a plurality of field oxide layers on the semiconductor substrate to isolate the active regions from each other, and performing a photolithography process for device isolation between devices to be formed in a cell region and a peripheral region; ; Sequentially forming a word line functioning as a gate oxide film, a floating gate, a dielectric film, and a control gate on the active region; Applying an insulating film for insulation of the plate as a whole and forming a polysilicon layer thereon that functions as a plate electrode; Etching the exposed polysilicon layer after forming a photoresist pattern that opens a source line region between a bit line contact region and a ground select transistor between a string select transistor; And implanting channel stop ions through a portion of the insulating film that appears through partial etching of the polysilicon layer to enhance electrical insulation of the bit line contact region. The method of claim 2, wherein the insulating film for insulating the plate is an oxide film. The method of claim 2, wherein the channel stop ions are boron ions.

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