KR100224052B1 - A synchronous semiconductor memory and a method of driving the same - Google Patents

Abstract

It provides a synchronous semiconductor memory device that has an output register for executing serial data output and can lead an address to a data transfer path even in a cycle of limited cycles and consumes less power.

When starting the serial access operation in the cell in a cycle corresponding to two cycles of the burst clock BCK, the first pipeline stages S1 and S2 are put through without disconnecting all of the first to third pipeline stages S1 to S3. And a data transfer control circuit 301 including a pipeline control circuit for separating all of the first to third pipeline stages S1 to S3 when the burst clock BCK starts operation of this serial access in a new cell in a cycle that is out of two cycles. Has

Description

Synchronous semiconductor memory device and operation method thereof

The present invention relates to a synchronous semiconductor memory device.

Systems are evolving to process data in larger quantities, and speeding up processing speed is always required.

Under such a situation, in the MPU controlling the processing, the speed of the processing can proceed at a considerable pace. On the other hand, in the memory device, the atmospheric storage is progressing at a considerable pace, but the processing speed is considerably slower than that of the MPU. For this reason, the difference in data processing speed between the MPU and the memory device only waits for expansion.

In order to solve such a speed difference, the memory device which controlled the operation | movement of a device by the method different from the control method of the conventional memory device, and improved the data transfer rate appeared. This is a synchronous memory device. A representative example of this synchronous memory device is a dynamic RAM controlled in synchronization with a system clock. Hereinafter, in this specification, this type of dynamic RAM is referred to as synchronous DRAM and abbreviated as SDRAM. The basic operation of the SDRAM has already been disclosed by Japanese Patent Application Laid-Open No. 5-2873. More specific product announcements are also made by theological reports SDM93-142, ICD93-136 (1993-11).

In this specification, description of the specification of the SDRAM is omitted, but in the SDRAM, how to read the burst data to be serially accessed at a high speed cycle becomes important, and the specification and the architecture for realizing it are divided into two types, a pipelined method and a register method. The outline of these systems will be described below.

[Pipeline method]

Fig. 27 is a schematic diagram of a pipelined SDRAM.

The memory cell array and sense amplifier 601 shown in Fig. 27 are well known, and the micro charge signals (data) in a series of cells belonging to the selected word line are read to the bit line and sense amplified. Pipeline operation is used to read data held in this sense amplifier at high speed. The number of pipeline stages from the fetch of addresses to the output of data is only three stages. 27 shows an SDRAM having these three stage pipeline stages S1, S2, S3.

As shown in Fig. 27, signals P1 and P2 are used to control latched gates 603 and 605 that fetch, hold, and output data at the up edge of the external control clock CLK. This is a cycle driven control signal. The signal P3 is a control signal for controlling the conductive gate 607. Latched gates 603 and 605 continue to latch, hold and output input data at the up edges of control signals P1 and P2, respectively.

In addition, the three stages S1, S2, and S3 each have the following functions.

(1st stage S1)

The start address of an externally given burst access or an internal address generated inside the apparatus in relation to this address (these addresses are shown as Ai) is fetched according to the control signal P1 and the fetched address is decoded by the address decoder 609. This creates a signal to select the access column. It is simply a stage for deciding the output of the address decoder at the input address.

(Stage 2 S2)

It latches a signal for selecting an access column, selects a column, and sends data held in the sense amplifier to a local data bus (hereinafter referred to as LDB). The LDB is connected to all columns via a gate controlled by a signal for selecting a column, and transmits only the data of the selected column. It is simply a stage for transmitting the extracted data to the LDB according to the output of the determined address decoder.

(Third stage S3)

The data transmitted to the LDB is conducted, sensed by the data bus sense amplifier 611, and then output via the global data bus (hereinafter referred to as GDB) from the output buffer 613 (this output is shown as Q). ). It is simply a stage for outputting data transmitted to the LDB to the outside of the device.

Fig. 28 is a diagram showing a data progression state in each stage in the pipelined SDRAM.

As shown in Fig. 28, assuming that the access of the burst data starts in the cycle indicated by the arrow 615, each stage S1, S2, S3 transfers the data sequentially in every cycle, so that all the stages S1, S2, S3 It is active in every cycle. In addition, since the address Ai is good every cycle, random data output is also possible. However, latency, i.e., the number of cycles from the fetch cycle of an address to the output cycle of data designated by the address, is required at least three cycles (this is referred to as SDRAM of latency 3).

[Register method]

Fig. 29 is a schematic diagram of a register type SDRAM.

Fig. 29 shows a register type SDRAM for reading two bits simultaneously. As shown in Fig. 29, the mesouri cell array and the sense amplifier 601 are the same as those of the pipeline system. In a register type SDRAM, unlike a pipeline type SDRAM, there is no need to provide a distinct stage. However, it is assumed that the stage is virtually provided. It is for the understanding of the present invention. The register type SDRAM can be largely divided into two stages S1 and S2. These two stages S1 and S2 have the following functions, respectively.

(1st stage S1)

The first address of the burst access data or the serial access address (these addresses are shown as Ai) are fetched according to the control signal P1, and the fetched addresses are decoded by the address decoder 709 to select several columns. Send data to LDB at the same time in multiple columns. It is simply a stage for determining the output of the address decoder at the input address and transferring the extracted data to the LDB according to the determined output of the address decoder.

(Stage 2 S2)

Two bits are selected from the data coming out of the LDB, and these are sensed to send data to the GDB and stored in the output register 713. Stored data is output in output bits 713 one bit at two cycles (these outputs are shown as Q). It is simply a stage for outputting data transmitted to the LDB to the outside of the device.

30 is a diagram showing a data progression state in each stage in the register type SDRAM.

As shown in Fig. 30, data is output to the LDB after two cycles from the start of the burst. The difference between the register method and the pipeline method is that a series of operations are determined by the capability of data transmission, and it is not prescribed to force control by an external clock, that is, to transmit data in one cycle. The transmitted data is output at the third and fourth cycles, during which the next two cycles of data advance to the LDB as well. Compared with the pipeline method, each stage is operated once every two cycles. Internally generated addresses are two cycles apart, and updateable cycles of addresses are also made every two cycles (this is called a limit cycle).

As described above, the pipelined SDRAM and the register SDRAM have their own characteristics.

For example, a pipelined SDRAM has fewer circuits necessary for constructing a system for transferring data, which can be configured relatively easily, and has flexibility in updating an access address. On the other hand, since data transmission is forcibly divided by cycles, the device's capabilities cannot be exerted at the highest efficiency. Therefore, power consumption becomes large for each stage to operate every cycle.

In addition, in the register type SDRAM, data transfer is not forcibly divided by cycles, and a plurality of cycles can be used for data transfer, so that data transfer can be performed to be optimal for internal operation. For this reason, it is possible to show the capability of the apparatus with the highest efficiency, and it is more suitable for speeding up operation. Each stage also consumes less power to run once in several cycles. However, the change of access address is limited to a plurality of cycle intervals unless the cycle time is doubled at the expense of speed. In addition, compared to the pipelined system, some circuits need to be added in order to form a system for transferring data such as registers, which makes construction difficult.

Fig. 31 is a comparison diagram of data transfer of pipelined SDRAM and data transfer of register SDRAM.

P1, P2, and P3 shown in FIG. 31 each represent the start cycle of each stage of the pipeline.

As shown in Fig. 31, first in cycle P1, an address is fetched, and the output of the address decoder is confirmed. This is the same as the pipeline method and register method. In the pipeline system, the second stage S2 shown in Fig. 27 starts at cycle P2, but not in the register system. For this reason, the selection decision timing of the column select line CSL for transferring the data of the memory cells to the LDB is different in the pipeline method and the register method. In detail, while the pipelined determination timing is made from cycle P2 in synchronization with the clock, the determination timing of the register system is not slowed down to cycle P2, but is almost immediately after the output of the decoder in cycle P1 is confirmed. When the selection of the column select line CSL is determined, the column gate (corresponding to the conductive gate 506) is turned on, and the data flows out to the LDB in the same way as the pipeline and register methods.

Finally, in cycle P3, the data bus sense is executed and data is output. This is the same for both pipeline and register methods.

The pipelined and register systems compared by Fig. 31 are so-called latency 3 SDRAMs in which data is output in the third cycle after the access starts. In the SDRAM of latency 3, comparing the pipelined scheme and the register scheme, there is a margin on the register side by the time T shown in FIG. This is because there is no such thing in the register method while the margin of all operations is determined in the margin of the stage where there is no operational margin within the cycle time in the pipeline method.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and a first object is to provide an address to the data transfer path even from a cycle other than a limit cycle while having an output register for executing serial data output. It is an object to provide a synchronous semiconductor memory device.

It is also a second object to provide a synchronous semiconductor memory device capable of continuously outputting data from an output register even when an address is guided to a data transfer path in a cycle other than a limit cycle.

A third object of the present invention is to provide a synchronous semiconductor memory device capable of increasing the efficiency of data transfer while reducing the access address.

A fourth object of the present invention is to provide a method for manufacturing a synchronous semiconductor memory device capable of leading an address to a data transfer path even from a cycle other than a limit cycle.

In the synchronous semiconductor memory according to the present invention, in a synchronous semiconductor memory device for serially outputting at least one data per clock cycle, an address fetching means for fetching an address into the device, and fetching Decoding means for decoding the old address, a memory cell array in which a plurality of memory cells for storing data are arranged, a data bus electrically coupled to the memory cell, and data stored in the memory cell, to the decoded address. Transfer means for transferring corresponding data to the data bus, output registers electrically coupled to the data bus, transfer means for transferring data transferred to the data bus one at a time to the output register, and the output register. A day sent And output means for serially synchronizing the output with the clock. The signal path from the address fetching means to the output register is separated into N pipeline stages, data of each pipeline stage is transmitted in m cycles of a clock, and access of data corresponds to a cycle of the clock. When starting from one cycle, consecutive n (= a / m) pipeline stages of the pipeline stages are passed through without separating all of the N pipeline stages, and access of data is a cycle of the clock. When the cycle starts off, the N pipeline stages are all separated.

In the synchronous semiconductor memory according to the present invention, in order to achieve the second object, a synchronous semiconductor memory device which outputs data serially at least one per clock cycle, comprising: address fetch means for fetching an address into the device; Decoding means for decoding the old address, a memory cell array in which a plurality of memory cells for storing data are arranged, a data bus electrically coupled to the memory cell, and data stored in the memory cell, to the decoded address. Transfer means for transferring corresponding data to the data bus, output registers electrically coupled to the data bus, transfer means for transferring data transferred to the data bus one at a time to the output register, and the output register. A day sent And output means for serially synchronizing the output with the clock. And there are k output registers, and each of the k output registers is assigned a number from 0 to k-1 in the order of access of data, and the order of outputting data in the output register is always the number in turn. When data access starts from a cycle corresponding to a cycle of the clock, the data transferred to the data bus is a pair of output registers 0 to a-1 and a to 2a-1. A pair of output registers are alternately transmitted one by a cycle, and when the data access starts from a cycle out of i (mod 2a) cycles in a cycle corresponding to a cycle of the clock, the pair of output registers is reassembled. The data transferred to the data bus is a combination of output registers from i (mod 2a) to i + a-1 (mod 2a) and i + 2a-1 (mod 2a) at i + a (mod 2a). Output level up to It is characterized in that a pair of jitters are alternately transmitted one by one every a cycle. Here, the relationship between i and a is 0 i a-2, a i 2a-2.

In the synchronous semiconductor memory according to the present invention, in order to achieve the third object, in a synchronous semiconductor memory device which serially outputs at least one data per clock cycle, address fetch means for fetching an address into the device, and fetching Decoding means for decoding the old address, a memory cell array in which a plurality of memory cells for storing data are arranged, a data bus electrically coupled to the memory cell, and data stored in the memory cell, to the decoded address. Transfer means for transferring corresponding data to the data bus, output registers electrically coupled to the data bus, transfer means for transferring data transferred to the data bus one at a time to the output register, and the output register. A day sent In synchronism with to the clock and having an output means for output to the serial. The signal path from the address fetching means to the output register is separated into N pipeline stages, data of each pipeline stage is transmitted in m cycles of a clock, and access of data corresponds to a cycle of the clock. Starting from one cycle, consecutive n (= a / m) pipeline stages of the pipeline stages are passed through without disconnecting all of the N pipelines, and access of data is off by a cycle of the clock. Starting from the cycle, all of the N pipeline stages are separated, there are k output registers, and each of the k output registers is numbered 0 through k-1 in order of data access. The order of data output in the output register is always in the order of the number, and the amount of data When a switch starts from a cycle corresponding to a cycle of the clock, the data transferred to the data bus is a pair of output registers 0 to a-1 and a pair of output registers a to 2a-1. When a cycle is transmitted alternately, when the data access starts from a cycle outside of an i (mod 2a) cycle in a cycle corresponding to a cycle of the clock, the output register is reassembled and transferred to the data bus. Data from the registers i (mod 2a) to i + a-1 (mod 2a) and the output registers from i + a (mod 2a) to i + 2a-1 (mod 2a). It is characterized by transmitting one by one alternately every a cycle. Here, the relationship between the i and the a is 0≤i≤a-2, a≤i≤2a-2.

In order to achieve the fourth object, in the method of operating a synchronous semiconductor memory according to the present invention, the first pipeline stage is performed from the input of an address to the decoding of the input address, and the data corresponding to the address from the decoded address. Is a second pipeline stage until the data is read in data order, and a third pipeline stage is used for inputting the read data to the data line and outputting the data serially. A method of operating a synchronous semiconductor memory device which executes internal processing of a signal to a second pipeline stage using a cycle of the clock, the method comprising: starting data access from a cycle corresponding to a cycle of the clock; A first pipeline stage and the second pipeline stay Is set to the through state, and when starting access of new data from a cycle out of cycle a of the clock, the first pipeline stage and the second pipeline stage are separated, and the inside of the signal corresponding to the access of the new data is Characterized in that the second pipeline stage and the third pipeline stage perform internal processing of a signal corresponding to an access of previous data, while executing the process in the first pipeline stage. .

1 is a schematic diagram of an SDRAM incorporating an embodiment of the present invention;

2 is a diagram showing a progress state of data.

3 is a circuit diagram of the SDRAM shown in FIG.

4 is a circuit diagram of a decoder.

Fig. 5 is a schematic diagram of an output register, in which (a) shows one state, and (b) shows another state.

6 is a circuit diagram of an output register.

7 is a block diagram of a data transmission control system circuit.

8 is a more detailed block diagram of FIG.

9 is a circuit diagram of a basic control signal generation circuit.

10 is a circuit diagram of a latch circuit.

11 is a circuit diagram of an address reset detection circuit.

12 is a circuit diagram of a transmission signal generating circuit.

Fig. 13 is a circuit diagram of even cycle and odd cycle determination circuit.

Fig. 14 is a circuit diagram of another even cycle / odd cycle determination circuit.

Fig. 15 is a circuit diagram of a pipeline control signal generation circuit.

Fig. 16 is a circuit diagram of a precharge control signal generation circuit.

Fig. 17 is a diagram showing a correspondence relationship between address buses AB1 and AB2, LDB, and lower bits A0 and A1.

Fig. 18 is a diagram showing a selection relationship between CSL and LDB.

Fig. 19 is an operational waveform diagram of an SDRAM.

20 is an operational waveform diagram of an SDRAM.

Fig. 21 is a circuit diagram of a division change signal switching circuit.

Fig. 22 is a circuit diagram of a division signal generation circuit.

Fig. 23 is a circuit diagram of a register selection signal generation circuit.

Fig. 24 shows a correspondence relationship between the levels of the signal SW and the signal CC and the output registers R1 to R4;

Fig. 25 is an operation waveform diagram of the peripheral circuit of the output register.

Fig. 26 is an operational waveform diagram of a peripheral circuit of the output register.

Fig. 27 is a schematic diagram of a pipelined SDRAM

Fig. 28 is a diagram showing a progress state of data.

29 is a schematic diagram of a register type SDRAM.

30 is a diagram showing a progress state of data.

Fig. 31 is a comparison diagram of data transfer of pipelined SDRAM and data transfer of register SDRAM.

* Explanation of symbols for main parts of the drawings

101: memory cell array and sense amplifier 105: address decoder

107: latch type gate 109: output register

113: Select Gate and Data Bus Sense Circuit

201: basic control signal generation circuit 301: data transmission control circuit

311: Even cycle / base cycle determination circuit 321: Address reset detection circuit

331: pipeline control signal generating circuit 341: transmission signal generating circuit

401: output register control circuit 411: division change signal switching circuit

421: division signal generation circuit 431: register selection signal generation circuit

501: precharge control signal generation circuit

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described. In this description, like reference numerals designate like parts throughout all the drawings, and overlapping descriptions are avoided.

1 is a schematic diagram of an SDRAM including an embodiment of the present invention.

As shown in Fig. 1, the SDRAM according to the embodiment of the present invention fetches the address Ai from the outside at the up edge of the memory cell array, the sense amplifier 101, and the control clock CLK supplied from the outside, and The latch decoder 103 for latching Ai and outputting the address decoder 105 for decoding the address Ai output from the latch gate 103 and outputting a signal for selecting a column of the memory cell array; A latched gate 107 connected to an output terminal of the 105 and latched and outputting the output of the address decoder 105 in response to a control signal P2, a local data bus LDB connected to a bit line of the memory cell array, column local The conductive gate 111 provided in the data bus LDB, the data provided between the local data bus LDB and the global data bus GDB and lead to the local data bus LDB. The data block sense circuit 113, which is sense sense amplified and transmitted to the global data bus GDB, and an output register 109 which is connected to the global data bus GDB and stores and outputs the data displayed on the global data bus GDB, are respectively included as basic blocks. .

The SDRAM shown in Fig. 1 has a block almost identical to that of the SDRAM shown in Figs. 27 and 29. Although the entire SDRAM system conforms to the register method, the timing of moving the data transfer stage (pipeline stage) is conventional. Is different.

In particular, the SDRAM shown in Fig. 1 is distinguished only in a special case where the first pipeline stage S1 and the second pipeline stage S2 are different, and in other cases, they are passed through each other to form one pipeline stage. For this reason, the latch gate 107 operates to distinguish the first pipeline stage S1 from the second pipeline stage S2 only in a special case, and in other cases, it is in the through state. The operation for distinguishing the first pipeline stage S1 from the second pipeline stage S2 is controlled by the control signal P2.

Next, the operation of the SDRAM shown in FIG. 1 will be described.

FIG. 2 is a diagram showing the operation of the SDRAM shown in FIG. 1, in particular showing the state of data transfer in the pipeline stage.

As shown in Fig. 2, it is assumed that the access starts from a cycle in which the up edge specified by the arrow 15 is the starting point, and a new address is set in the cycle in which the up edge designated by the arrow 17 is the starting point. . The cycle with the arrow 17 as the starting point is a cycle in which the setting of a new address is prohibited in the register system shown in FIG. In the SDRAM shown in Fig. 1, when a new address is set in a cycle in which setting of a new address is prohibited in the past, the control signal P2 is output, the latch gate 107 is activated, and the first pipeline stage S1 and the second are set. Separate pipeline stage S2. As a result, the pipeline stage is divided into three stages S1, S2 and S3, and these three stages S1, S2 and S3 are operated independently of each other. By operating the three stages S1, S2, and S3 independently of each other in this manner, the data inside the apparatus can be continuously transmitted without destroying the data before setting the new address by the data after setting the new address. After outputting the data before the setting of the new address, the data after the setting of the new address can be continuously output from the output register 109.

In addition, the cycle speed at this time is the same as that of the SDRAM of the pipeline system. The two cycles divided by the solid line in Fig. 2 indicate the original operation timing of the SDRAM shown in Fig. 1, and the operation timing after the setting of the new address is shifted by one cycle from the original operation timing and is separated by a dotted line. It is the operation of two cycles.

FIG. 3 is a circuit diagram of the SDRAM shown in FIG.

As shown in Fig. 3, the latch gate 103 fetches and latches the address Ai in response to the control signal P1. The fetched address is decoded by the address decoder 105 and two adjacent column select lines CSL are selected. The result decoded by the address decoder 105 can be output from the latch gate 107 by the control signal P2 in the next cycle of the address fetch cycle. However, the latch type gate 107 is activated only when a new address is set in a specific cycle as described above, that is, in a cycle subsequent to the address fetch cycle in which the setting of a conventional address is prohibited. It is a state. When the potential of two adjacent column select lines CSL rises, the data already read from the memory cell and held in the sense amplifier advances to the four pairs of local data bus LDB. In the SDRAM shown in Fig. 3, two cycles are used, counting data from when the address is set to the local data bus LDB bet.

After the data is output to the local data bus LDB, the data bus sense circuit 113 with a selection function is used, two pairs are selected from the four pairs of local data bus LDBs, and appear on the selected two pairs of local data bus LDBs. Each data is amplified and sent to the global data bus GDB. Thereafter, the data transferred to the global data bus GDB is transferred to the output register 109. At this time, the data is transferred to the output register 109 via the scrambler 115 set for addressing of serial access, and the two registers R1 and R2 (or registers R3 and R4) included in the output register 109 are included. 2 bits are stored in. Data stored in registers R1 and R2 (or registers R3 and R4) is output one bit at a time. In this manner, the third and fourth two cycles are used starting from the address setting until the data is output to the local data bus LDB and then to the output register 109.

In the SDRAM shown in FIG. 3, such an operation is periodically repeated every two cycles, as shown in FIG. When a new address is set in a cycle shifted from the cycle every two cycles, the latch-type gate 107 is activated by the control signal P2, and the new data is output to the local data bus LDB while the data before the new address is set. Decode the set address. In the operation of the SDRAM in this manner, the data before the setting of the new address is finished without being destroyed by the data after the setting of the new address, and the data after the setting of the new address is output after the data before the setting of the new address is output. The register 109 can be constantly output.

In addition, in the SDRAM having the above configuration, the data appearing in the global data bus GDB is changed every cycle, and the output register 109 is outputted from any one of the registers R1 to R4 every cycle in a certain order. This realizes high speed serial access. In the method of outputting in any order from one of registers R1 to R4, when there is a setting of a new address in a cycle shifted from the cycle every two cycles, the data storage cycle to the output register 109 is shifted from the cycle every two cycles. Throw it away. Such a countermeasure for misalignment of the storage cycle will be described later.

Next, a method of raising the potential of two adjacent column select lines CLS will be described.

4 is a circuit diagram showing an address decoder 105 and a circuit in the vicinity thereof.

As shown in Fig. 4, there are address buses AB1 and AB2, and the least significant bits A0 of the addresses correspond to 0 and 1 in these address buses AB1 and AB2, respectively. The address bits sent to other address buses are higher than this. The address generating circuit 117 makes the address plus one to the address latched in the latch gate 103. The address generating circuit 117 transmits the plused address and the address latched to the latch gate 103 to the address bus AB1 and the address bus AB2. In this manner, the potentials of two adjacent column select lines CSL can be raised. In the figure, the same reference numerals in the figure execute the same decoding, and are arranged in order of increasing address. The latch type gate 107 to which the above-described control signal P2 is input is opened to the column select line CLS, which is connected to the output of the address decoder 105, and performs a latch operation as necessary. 3 and 4, although adjacent CSLs are selected, they do not have to be physically adjacent to each other, but may be adjacent in the addressing space.

When the setting of a new address is executed in a cycle deviating from the cycle every two cycles, the latch gate 107 is activated, and the pipeline operation is performed temporarily every cycle. At this time, the data storage cycle to the output register 109 is shifted from the previous two cycle cycles and is confused. There is a need for a way to cope with such data storage cycle confusion.

Fig. 5 is a schematic diagram of an output register capable of coping with data storage cycle confusion in the output register 109, (a) showing one state and (b) showing another state.

As shown in Fig. 5, signals output as output data are obtained by scanning the output registers R1 to R4 in a fixed order, respectively. The scanning order of the output registers R1 to R4 does not collapse or skip even if there is a setting of a new address or the like. By not disrupting or skipping the scanning sequence in this manner, it is not necessary to take a spare time such as an addressing change time during the data output cycle, and it is possible to output data at a high speed cycle at all times.

First, as shown in Fig. 5A, two bits of data are stored in the output register R1 and the output register R2 (REGA1 in the drawing), and the registers R3 and R4 (REGB3 in the drawing). do.

In the first two cycles, two bits of data are stored on the REGA gate side, and in the next two cycles, the next two bits are stored on the REGB gate side. During this two-cycle storage cycle, it is said that there is a new address setting out of this storage cycle. At this time, data corresponding to the newly set address appears in the global data bus GDB in a cycle out of the storage period. For example, after data is output from the output register R1, data output from the output register R2 is stored at the newly set address. It becomes the corresponding data. Then, as shown in Fig. 5B, the storage division of data is changed.

After the data corresponding to the newly set address appears in the global data bus GDB, the first two cycles of data are stored in the output register R2 and the output register R3 (REGA2 in the figure), and in the next two cycles, the output register R4 and the output register R1 ( In the figure, data is stored in REGB4).

In addition, when data corresponding to a newly set address appears in the global data bus GDB in accordance with a storage cycle every two cycles, the division of the REGA side gate and the REGB side gate is not changed. Departing from the storage cycle every two cycles, only the data corresponding to the newly set address appears in the global data bus GDB from Fig. 5 (a) to Fig. 5 (b) or from Fig. 5 (b) to Fig. 5 (a). The division of the REGA side gate and the REGB side gate is changed.

In this manner, when the data corresponding to the newly set address appears in the global data bus GDB out of the storage cycle every two cycles, the scan sequence numbers of the registers R1 to R4 are not broken or skipped, and the registers R1 to In changing the method of classifying R4, if data is always output sequentially from registers R1 to R4, serial access can be executed regardless of the setting of new data, and data can be output at a high-speed cycle at all times.

FIG. 6 is a circuit diagram of the output register 109 shown in FIG.

As shown in Fig. 6, data is output from the terminal Q. When the signal HiZ rises, the output transistor 119 is turned off, so that the terminal Q becomes high impedance. The data stored in the output registers R1 to R4 is output to the terminal Q by the gate signals GR1 to GR4 rising in order and sequentially to conduct the clocked inverter.

In Fig. 6, the gates REGA and REGB shown in Fig. 5 are the transfer gates REG11 to REG42. It is a clocked inverter as shown in the transfer gates REG11 to REG42. The selected data is transferred to the global data buses GDB1 and GDB2 from among the data shown in the four pairs of local data buses LDB, respectively.

Next, overall data transfer control of the SDRAM according to the present invention will be described.

7 is a block diagram of a data transfer control system circuit of the SDRAM according to the embodiment of the present invention.

As shown in Fig. 7, the data transmission control system circuit operates in synchronization with an internal clock (hereinafter referred to as burst clock) BCK created according to an external clock, and transfers data so that data transmission is executed in synchronization with the burst clock BCK. To control. Burst clock BCK occurs when burst starts. In addition, a signal NBSRT (hereinafter referred to as a sinburst start signal) indicating that a new burst has been started is input to the data transmission control system circuit, and the data transmission control system circuit mainly uses two types of signals, a burst clock BCK and a burst start signal NBSRT. A signal group for controlling data transmission is generated.

The data transmission control system circuit is a basic clock, which is the basic control signal group / SF corresponding to the cycle order from the start of the first burst in synchronism with the burst clock BCK (the leading / represents an inverted signal or a negative logic signal-). In the figure, a basic control signal generation circuit 201 for generating a-(bar) at the top of the code is synchronized with the burst clock BCK and responds to the sinburst start signal NBSRT and the basic control signal group / SF group. The split indication signal P2ON, which divides the pipeline stage by the first burst initiation cycle, the signal Φ 2N indicating whether it is an even cycle or an odd cycle and a control signal that indicates whether the new burst started in an odd cycle or in an even cycle. In synchronism with the burst transfer signal BCK and the data transfer control circuit 301 for generating the groups S, ST2, SW, CC, etc. An output register control circuit for generating a selection control signal group REG for selecting and controlling the output register 109 in accordance with each of the burst start signal NBSRT, the signals ST2, SW, CC, the basic control signal group / SF, and the least significant bit A0 of the address; 401, which generates the LDB precharge control signal group LDBPRCH which synchronizes with the burst clock BCK and controls the precharge of the LDB according to the sinburst start signal NBSRT, the signal ST2, Φ 2N and the initial value A1 int of the bit A1 of the address, respectively. A precharge control signal generation circuit 501.

8 is a more detailed block diagram of the block diagram shown in FIG.

As shown in Fig. 8, the data transfer control circuit 301 responds to the basic control signal groups / SF1 to / SF4 in synchronization with the inverted burst clock / BCK, counting from the cycle of the first burst start, and notifying the even cycle. Even and odd determination circuit 311 that outputs signal Φ2N and signal Φ2N + 1 informing the odd cycle, responds to basic control signal / SF2, basic control signal / SF4 and synbust start signal NBSRT in synchronization with inverted burst clock / BCK And an odd cycle address reset detection circuit 321 for outputting a signal S2 and a signal S4 indicating that there is an address reset in an odd cycle, in response to the signal? 2N + 1 and the sinburst start signal NBSRT in synchronization with the burst clock BCK, Pipeline control signal generating circuit 331 which outputs division instruction signal P2ON and control signal ST2, which responds to signal S2 and signal S4 and outputs control signals S2, CC, / CC And a transmission signal generation circuit 341.

In addition, the output register 401 is a division change signal switching circuit 411 which outputs division change signals SR13 and SR24 in response to the control signal ST2 and the control signal SW in synchronization with the burst clock BCK and instructs the division of the output register. The division change signal generation circuit 421 and the division signal group REGA1 which output the division signal groups REGA1 to REGB4 in response to the division change signals SR13 and SR24, the basic control signal groups / SR1 to / SF4, and the control signals CC and / CC. And an output register select signal generation circuit 431 for outputting the selection control signal groups REG11 to REG42 in response to REGB4, the sinburst start signal NBSRT, and the least significant bit A0 of the address.

Next, each circuit will be described in detail.

9 is a circuit diagram related to one circuit example of the basic control signal generation circuit 201.

As shown in Fig. 9, one circuit example of the basic control signal generation circuit 201 is a cyclic shift register in which a latch circuit 203 in synchronization with the burst clock BCK is connected in four stages and in a ring shape.

FIG. 10 is a circuit diagram of the latch circuit 203 shown in FIG.

The basic operation of the latch circuit 203 shown in Fig. 10 is as follows. First, when the burst clock BCK rises, the latch circuit 203 latches data input at the input IN and outputs at the output OUT. When the burst clock BCK rises, the latch circuit 203 continues to output latched data at the output OUT, but the first stage latch circuit 203-1 accepts input of new data at the input IN.

The shift register shown in Fig. 9 is driven by the burst clock BCK generated only in the cycle in which data transfer is executed. In the reset state, the first output signal / SF1 is at L level, and the second output signal / SF2 to fourth output signal / SF4 are at H level. The output state of the L level is shifted from the first output signal / SF1 to the fourth output signal / SF4 every cycle of the burst clock BCK. The burst transfer operation of data starts, and in the even cycle, the second output signal / SF2 or the fourth output signal / SF4 is at L level. If the head address of the new burst is reset in the odd cycle, the signal S2 or signal input to the gates of the transistors 205-2 and 205-4 connected to the second output signal / SF2 and the fourth output signal / SF4, respectively. S4 rises to set the second output signal / SF2 or the fourth output signal / SF4 to L level. From there, the shift cycle of the new burst begins.

In the present specification, the first cycle of the burst is defined as 0 cycle, and is counted as follows 1, 2, 0, 2, 4,... Excellent cycle, 1, 3,... Is defined as the radix cycle.

FIG. 11 is a circuit diagram of the odd cycle address reset detection circuit 321, and FIG. 12 is a circuit diagram of the transmission signal generation circuit 341. FIG.

The detection circuit 321 shown in Fig. 11 checks which cycle of the shift register shown in Fig. 9 is the cycle of the new burst set at the odd number. If a new burst starts from the next cycle of the cycle where the second output signal / SF2 is at L level, then the signal SBS rises at the beginning of the cycle, since the signal NBSRT rises at the beginning of the cycle. If a new burst is started from the next cycle of a cycle in which the fourth output signal / SF4 is at L level, the signal NBSRT rises at the beginning of the cycle, so the signal S4 rises at the beginning of the cycle. The signals S2 and S4 set the shift register shown in Fig. 9 in combination with the signal in the cycle in which the signal rises, and set the second output signal / SF2 or the fourth output signal / SF4 to L level to cycle the new shift register. To start.

In the circuit shown in Fig. 12, the first time the signal S2 or the signal S4 rises, the node SW rises to the H level. The initial state of the node SW is L level. When the signal S2 or the signal S4 rises for the second time, the node SW falls to the L level. Thereafter, the node SW returns H, L, H,... Whenever the signal S2 or the signal S4 rises. To change.

In addition, the initial state of the node CC of the circuit shown in FIG. 12 is H level. Node CC is assigned to L, H, ... whenever the node SW changes from H level to L level. To change. The node / CC is a complementary node of the node CC, and a signal inverting the level of the node CC is drawn out from the node / CC. The signals drawn out from these nodes CC and node / CC are used to control the change of the data storage division of the output register shown in FIG. The details will be described later.

13 is a circuit diagram according to one circuit example of the even cycle and odd cycle determination circuit 311.

One circuit example 311 'shown in Fig. 13 is not the basic control signal group / SF like the clocks shown in Figs. 7 and 8, and since the burst access is serial, the least significant bit A0 of the address and the internal counter are used. By comparing the output AOint, an even cycle or an odd cycle is determined.

As shown in Fig. 13, in one circuit example 311 ', at the start of a new burst access, A0, the least significant bit of the address, is latched and latched to the node N1 at the rise of the signal NBSRT indicating the start of a new burst. It is compared with the output AOint from the internal counter. The initial value of the node N1 and the initial value of the internal counter output AOint are set to be inconsistent with each other, and then change after the start of operation by the signal / NBSRT and the internal counter output AOint. Thus, for example, the signal? 2N + 1 becomes L level at the rise of the burst clock signal BCK in the first cycle, and at the next rise, the value of the node N11 and the internal counter output AOint coincide with each other. When the signal BCK rises, the signal indicating whether the burst or the odd number from the first cycle of the cycle is always at the H level.

14 is a circuit diagram according to another circuit example of the even cycle / odd cycle determination circuit 311.

In another circuit example 311 shown in Fig. 14, like the blocks shown in Figs. 7 and 8, even cycles and odd cycles are determined using the basic control signal group / SF.

An advantage of the other circuit example 311 is that the state of the least significant bit of addressing of burst access is not used compared to the circuit example 311 'shown in FIG. The signals / SF1 to / SF4 are sequentially turned to L level only by the number of cycles of the burst clock BCK. Therefore, the signal / SF2 and the signal / SF4 rise in the even cycle, while the signal / SF1 and the signal / SF3 rise in the odd cycle. In the circuit example 311 shown in Fig. 14, these signals are latched at the end of the cycle when the burst clock BCK rises, indicating whether the cycle number is the even or odd number when the burst clock signal BCK rises. You can write a signal.

15 is a circuit example of a pipeline control signal generation circuit 331.

The signal P2ON output by the circuit 331 shown in Fig. 15 is a signal indicating that the signal NBSRT has risen in the odd cycle. The signal P2ON is a summation for starting the control for moving the latch gate 107 shown in Figs. In moving the latched gate 107, the second pipeline stage S2 of the pipeline appears and temporarily shifts from the stage 2 pipeline operation to the stage 3 pipeline operation. The signal P2ON is latched at the head of the cycle, and is output as the signal ST2 when the burst clock BCK of the cycle rises. The signal ST2 is used for precharge control of the LDB.

Fig. 16 is a circuit diagram of the precharge control signal generation circuit 501 of the LDB.

The precharge operation of the LDB is executed every cycle in the pipeline method, but is good every 2 cycles in the 2-bit prefetch method, and the power consumption and the operation margin are expanded. However, in the SDRAM according to the present invention, when the signal NBSRT enters in order to start a new burst in the odd number cycle, it becomes a pipeline system temporarily, and it is necessary to switch the precharge control.

First, the LDB and the address bits are corresponded to make the description easier to understand.

Fig. 17 shows the relationship between the LDB pairs shown in the address buses AB1, AB2 shown in Fig. 4 and LDB1, 2, 3, 4 (shown as atomic characters in the figure) and the lower bits A0, A1 of serial access. To show.

Now, when two consecutive bits of data are transmitted, four bits of data are simultaneously transmitted, and two bits of data are selected by the selection gate 113 having a selection function (see FIGS. 1 and 3). The relationship between the transmitted 4-bit and 2-bit is as follows.

The 4 bits constitute data to be communicated in the burst access, but the 2 bits selected therein constitute the 1st and 2nd bits or the 2nd and 3rd bits in the access order. This also corresponds to the address for selecting CSL is always plus 1 and used in pairs, as mentioned in the description of FIG. In this way, burst access can be performed continuously from an arbitrary address by outputting four bits of data to the LDB every two cycles, but the LDB precharge does not need to be executed in four pairs every two cycles. What is necessary is just to precharge by 2 pairs of the data exclusively completed already selected by the gate 11 which has a selection function. The pair at this time is LDB1 and LDB2 or LDB3 and LDB4. This is because they are simultaneously selected by the column select signal CSL in pairs.

Although this LDB is precharged, as shown in Fig. 16, if the head address of the burst access is not reset in the middle, LDB1 and LDB2 to which new data is transmitted according to the internal address Alint of the access for every even cycle. LDB3 and LDB4 receive a precharge. If there is a reset of the first address of the burst access, if it is an even cycle, it is hit a little precharge cycle, so precharge is executed in that cycle, but it is executed in all four pairs of LDB1, LDB2, LDB3, and LDB4. This is because 4 new bits are sent to the LDB. For the odd cycle, if prefetching is forcibly executed in the cycle, even if the stage of the pipeline is temporarily extended, the LDB1, LDB2, LDB3, Precharge is performed on all four pairs of LDB4. This is controlled by the signal ST2 produced by the circuit shown in Fig. 15, and when this signal ST2 is at the H level, precharge is executed in a cycle in which the burst clock BCK rises.

19 and 20 are operation waveform diagrams of the SDRAM, respectively.

19 and 20, the data length of burst data access is eight. In addition, the numbered part of the external clock CLK corresponds to the burst clock BCK. The signal / CE is a command signal indicating a cycle of a new start of burst access, and the leading address of the burst access is fetched when the burst clock BCK of the cycle in which the command signal is entered rises. The number of the LDB to which the data of the address set by the command should exit is shown in accordance with the signal / CE column. The selection relationship between the column select line CLS and the LDB is as shown in FIG. In Fig. 18, one of the selection relations is drawn out and explained. When the column selection line CSL0 is selected, LDB1 and LDB2 are selected, and data is transferred to the selected LDB1 and LDB2.

The operation waveform diagram shown in Fig. 19 shows the operation waveform when a new burst is started in the even cycle of one burst. Specifically, the address is set so that the data coming out of LDB4 is the first in eight cycles.

As shown in Fig. 19, when address setting is made by the command (see waveform of / CE), the internal address bit Alint changes from 1 to 0.

In the first burst, the data of LDB2 is the first, so first, the precharging of LDB1, LDB2, LDB3, and LDB4 in the precharge state is stopped, CLS0 and CLS1 are raised, data is output, and the selection gate 11 is passed through. When T is reached, LDB2 and LDB3 are in contact with GDB to transfer data. The transferred data is stored in output register R1 and output register R2 in the T state.

From two cycles, CLS2 rises and new data is transmitted only to LDB1 and LDB2, so that precharge is executed at the head of the cycle. At this time, the select gate 11 becomes H of the hold, and the pre-charged LDB2 is separated from the GDB. During this time, the output registers R1 and R2 are in the H state, and the output registers R3 and R4 are in the T state. When the select gate 11 is brought to the next T state, LDB4 and LDB1 are brought into GDB, and this data is sent to GDB and stored in the output register.

From four cycles, CSL3 rises, and new data is sent only to LDB3 and LDB4, continuing the same operation.

When a new burst is set in eight cycles, data is newly sent to all four pairs of LDB1 to LDB4, so that all LDBs are precharged at the head of eight cycles. CSLm + 0 and CSLm + 1 rise, the data goes out to the LDB, the LDB4 and the LDB1 are connected to the GDB at the selection gate 11, and the data is transferred. As described above, the data is transferred.

In the second burst, the output state of the selection gate 11 and the output register are only different from the initial burst, and the others are almost the same as the initial burst. Since no new burst is set during the second burst, after eight cycles, the burst clock signal BCK ends and data access stops in 15 cycles.

The operation waveform diagram shown in Fig. 20 shows the operation waveform when a new burst is started in the odd cycle of a burst, and specifically, the new burst is set in seven cycles.

In this case, it is the same as the operation shown in Fig. 19 until the start setting of the new burst is made in seven cycles. Since the new setting in the seventh cycle is the setting in the odd cycle, as described with reference to Fig. 16, in the next eight cycles, both LDB1 to LDB4 are precharged. In addition, the address latched in seven cycles causes the pipeline operation of the second stage S2 to be temporarily executed, resulting in CSLm + 0 and CSLm + 1 in the next eight cycles. In the seventh cycle, the data of LDB4 and LDB1 of the previous burst are stored in the output register R3 and the output register R4, respectively, but only the data of LDB4 of the output register R3 is output and stored in the output register R4, but the LDB4 of the output register R3 is stored. Only data is output, and the data of LDB1 of the output register R4 is replaced by the selection switching of the selection gate 11 in eight cycles and the transfer of the new data to the LDB to the data of the LDB3 of the head address of the new burst. In eight cycles, as described with reference to Fig. 5, the division of data storage into registers is changed. After the 9th cycle, the burst operation starting with the 7th cycle becomes the original operation. In the 14th cycle after the burst of the 8th cycle, the burst clock signal BCK stops, and the data access stops in the 14th cycle.

Next, the output register control circuit 401 for changing the division of the output register related to Fig. 5 in the eighth cycle will be described.

21 is a circuit diagram of the division change signal switching circuit 411.

In the initial state of the circuit 411 shown in Fig. 21, the signal SR13 is at the H level. Since the signal SW is output from the circuit shown in Fig. 12, the L level is changed from the L level to the H level at the setting of the first cycle number, and then the L level and the H level are alternately repeated. Signals SR13 and SR24 change the signal SW to L level, H level, and L level, and signal SR13 changes to H level, L level, H level, and signal SR24 changes to L level, H level, and L level. However, the timing of the state change is when the level of the signal SW has been delayed for some time from the cycle following the conversion. This is because a signal latched by the logical AND of the signal ST2 and the burst clock BCK is output as the signals SR13 and the signal SR24 via the delay circuit D. Such timing is set in order to match the transfer of data with the switching of the output register.

22 is a circuit diagram of the division signal generation circuit 421.

As shown in Fig. 22, signals / SF1 and / SF3 are outputs of the shift register 201 shown in Fig. 9, and signals CC and signals / CC are signals output from the circuit 341 shown in Fig. 12. to be. As the signal CC changes its level, the role of the signal / SF1 and the role of the signal / SF3 are alternately replaced. This is because it is necessary to shift the data storage order to each division as well as the division of the output register as described later. Signal SR13 and signal SR24 are signals corresponding to the method of distinguishing the output registers. When these signals SR13 and SR24 correspond to the output register classification method shown in Fig. 5, respectively, the signal SR13 corresponds to the pair of the output register R1 and the output register R2 and the pair of the output register R3 and the output register R4, and the signal SR24 is the output register. Corresponds to the pair of R2 and output register R3 and the pair of output register R4 and output register R1. The output signals REGB4, REGA2, REGA1, and REGB3 of the circuit shown in Fig. 22 are input to the flip-flop constructed by using the NOR circuit, and the data must be stored when the output register is switched, and the gate of the open is opened. This is because of the initial configuration. In the figure, D and 6 are delay circuits that make an appropriate delay.

23 is a circuit diagram of the register selection signal generation circuit 431. As shown in FIG.

In GDB1 and GDB2 of Fig. 3, one corresponds to 0 of the least significant bit A0 of the address, and the other corresponds to 1 of the least significant bit of 0. This corresponds to GDB1 and GDB2 shown in FIG. In the cycle of designating the head of the burst, the four latch sections 433-1, 433-2, and (433-2), which output a signal for controlling the division regarding the output register at which the least significant bit A0 of the address is not in the operating state at that time ( 433-3) and 433-4. That is, if the REGA1 portion in FIG. 5 is to be stored, the signal / REGA1 is at the L level, so the least significant bit A0 is not transmitted to the latch portion 433-1 in FIG. 2), 433-3 and 433-4. The value of the least significant bit A0 causes any of the signals / RE10 to / RE41 to go to L level, depending on the register division that is stored at the beginning of the new burst. This also raises two of the corresponding transfer gate signals. For example, when / RE30 becomes L, signals REG31 and REG41 become H, respectively, and data of GDB1 is stored in output register R3 and GDB2 in R4.

Fig. 24 shows the change of the output register division when a new burst setting is made in the odd cycle and the change relationship between the signal SW and the signal CC output by the circuit 341 shown in Fig. 12. Figs. The first page is the division of each register, and the radix first setting is made for this burst access. Until the initial setting is made, each signal remains in its initial state, the signal SW is at L level, and the signal CC is at H.

There are two types of output registers as shown in Fig. 24, but these divided blocks are shown in Fig. 24 as A1, B3, A2, and B4. The division changes alternately into A1 and B3 divisions and A2 and B4 divisions each time. However, as shown in Fig. 24, the storage order of data is divided between diagonally divided blocks and non- diagonally spaced blocks. The order of storage moves. That is, if A1 has a new setting during the storage operation, then A2 receives the storage, and if A2 has a setting during the storage operation, then B3 executes the storage operation. The signal SW changes state whenever there is a setting in the odd cycle. As shown in the figure, the transfer order requires a signal to be converted every two cycles of this change, which is the signal CC. Without the control by such a signal, only the first and second divisions of the ground alternately move, and there can be no advance control as described above. That is, in the circuit shown in Fig. 22, when the signal CC changes, the roles of the signal / SF1 and the signal / SF3 are replaced, so that the signal controlling the transfer gate is phased relative to the shift register shown in Fig.7. You can proceed.

25 and 26 are operation waveform diagrams showing control shapes around an output register, respectively. These operation waveforms correspond to Fig. 20 showing the state of data transfer.

As shown in Fig. 25, when the burst starts in cycle 0, the shift register shown in Fig. 7 is initially set with the signal / SF1 set to the L level. The odd cycle is specified by changing the signal? 2N + 1 produced by the circuit shown in FIG. 13 or 14 as shown in FIG. As signal / SF1 rises, signal REGA1 determines H level, signal REGB3 determines L level, and signal / SF3 rises, signal REGA1 changes to L level, and signal REGB3 changes to H level. In this way, when data advances to each division block of the output register, and a new burst is set in the odd cycle 7, the signal P2ON and the signal ST2 in the circuit shown in Fig. 15 and the signal in the circuit shown in Fig. 12 are performed. SW changes, and in cycle 8, the signal SR13 in the circuit of FIG. 21 changes to L level, and the signal SR24 becomes H level, thereby distinguishing B4A2 from the control signal of the B3A1 division of the circuit shown in FIG. Switch to the signal system under control. At this time, the signal REGB4 rises by the return of the signal REGB3 to the NOR circuit. Next, as / SF1 rises, the signal REGB4 turns to L level, the signal REGA2 turns to H level, and the change by the signal / SF3 is performed below. This corresponds to the state change of the setting circuit 1 shown in FIG. 22 and the data storage operation in B4 and A2. After the burst in cycle 14, each signal remains in its final state, ready for the next burst. Subsequently, Fig. 26 shows an operation waveform when the burst is set.

In Fig. 26, it is assumed that the previous burst ends a little while the new burst starts from cycle 0. The burst starts when the signal / SF3 goes to the H level, but this changes the signal REGA2 to the L level and the signal REG to the H level. Unlike FIG. 25, the division block of A2B4 executes a data storage operation. When a new burst is set in cycle 7, signal SW changes to L level and signal CC also changes to L level. In the eighth cycle, the signal SR13 in the circuit shown in Fig. 21 is changed to the H level and the signal SR24 is turned to the L level, so that the signal of the division control signal of the circuit B4A2 shown in Fig. 22 is changed to the signal system of the B3A1 division agent. Switch. At this time, the signal REGB3 rises due to the return of REGA2 to the NOR circuit. Next, since the signal CC changes to the L level due to the rise of the signal / SF3, the roles of the signal / SF1 and the signal / SF3 in the circuit shown in Fig. 22 are replaced, so the signal REGB3 goes to the L level. , Signal REGA1 changes to H level, and changes according to signal / SF1 are executed. This corresponds to the state change of the setting circuit 2 in FIG. 22 and the data storage operation in the signals B3 and A1.

The data transfer performed by the SDRAM according to the embodiment of the present invention can also be applied to data transfer in a computer or data transfer in a network computer. In this case, the part which processes data, such as an address decoder, a memory cell array, and a sense amplifier, may be replaced with the data processing part in a computer or a network computer.

In the SDRAM according to the embodiment of the present invention, the number of pipeline stages is changed in accordance with a timing at which an operation cycle is required, such as an address change. However, it is also possible to use a method that does not change the number of pipeline stages.

For example, when the frequency of the system clock is low, the head address can be input at any time without controlling the timing of inputting the head address for the new burst data access during the burst data access. In other words, the stages S1, S2, and S3 are always used in a separated state.

On the other hand, when the frequency of the system clock is high, the timing of inputting the head address for the new burst data access during the burst data access is controlled, and the head address is input only at this limited timing. In other words, the stages S1, S2 and S3 are used in a state where the stages S1 and S2 have always passed.

In addition, whether or not the number of pipeline stages has been changed can be determined according to the method of the system in which the SDRAM of the present invention is assembled.

For example, in a system that always requests a change of address from a cycle corresponding to a cycle, the stages S1 and S2 are always passed, and the number of pipeline stages in the SDRAM is not changed.

In contrast, in a system that requests a change of address from a cycle other than a cycle, when the change of address is requested from a cycle other than a cycle, the stages S1, S2, and S3 are separated and the address is changed. When a change of is required in a cycle corresponding to a cycle, it passes through the stages S1 and S2.

As described above, the SDRAM according to the embodiment of the present invention can appropriately correspond to various systems.

The data transfer performed by the SDRAM according to the embodiment of the present invention is applied to data transfer in a computer or data transfer in a network computer. Configure a data transmission system that transmits at a higher speed.

As described above, according to the present invention, a synchronous semiconductor memory device that has an output register for executing serial data output and can lead an address to the data transfer path even in cycles other than the limit cycle and has a low power consumption is limited. Even if the address is guided to the data transfer path in cycles other than the cycle, a synchronous semiconductor memory device capable of continuously serially outputting data from the output register, and it is possible to increase the efficiency of data transfer while having freedom in changing the access address, and consume power. The operation method of the synchronous semiconductor memory device capable of guiding an address to the data transfer path even in a small number of synchronous semiconductor memory devices and a cycle other than the limit cycle can be provided.

Claims (18)

A synchronous semiconductor memory device for outputting data serially at least one for each clock cycle, comprising: address fetch means for fetching an address into the device; Decoding means for decoding the fetched address; A memory cell array in which a plurality of memory cells for storing data are arranged; A data bus electrically coupled to the memory cell; Transfer means for transferring data corresponding to the decoded address among the data stored in the memory cell to the data bus; An output resistor electrically coupled to the data bus; Transfer means for transferring data transferred to said data bus to said output register at a time; And output means for serially outputting a data transmitted to the output register in synchronization with the clock, wherein a signal path from the address fetch means to the output register is separated into N pipeline stages, In m cycles, data of each pipeline stage is transmitted, and when the access of data starts from a cycle corresponding to a cycle of the clock, all of the N pipeline stages are separated, A synchronous semiconductor memory device, wherein n (= a / m) pipeline stages are passed through and all of the N pipeline stages are separated when the access of data starts from a cycle out of a cycle of the clock. . The method of claim 1, wherein m is 1, n is 2, and N is 3, and the three pipeline stages correspond to the first pipeline stage from fetch to decode of the address, respectively, to the decoded address. A second pipeline stage until transferring one data to a data bus, and a third pipeline stage until transferring data transferred to the data bus to the output register at a time, and accessing the data And the pipeline stages to be passed through when starting from a cycle corresponding to a cycle of the clock are the first pipeline stage and the second pipeline stage. A synchronous semiconductor memory device for outputting data serially at least one per clock cycle, comprising: address fetch means for fetching an address into the device; decode means for decoding the fetched address; A memory cell array in which a plurality of memory cells for storing data are arranged; A data bus electrically coupled to the memory cell; Transfer means for transferring data corresponding to the decoded address among the data stored in the memory cell to the data bus; An output register electrically coupled to the data bus; Transfer means for transferring the data transferred to said data bus to said output register three at a time; And output means for serially outputting the a data transmitted to the output register in synchronization with the clock, wherein the output register has k, and each of the k output registers is 0 to k in order of data access. Numbered up to -1, and the data output order in the output register is always in the order of the number, and when the access of data starts from a cycle corresponding to a cycle of the clock, Transmitted data is transmitted in turn by a set of output registers 0 to a-1 and a set of output registers a to 2a-1 by a cycle every a cycle, and data access is transferred to a cycle of the clock. When starting from a cycle outside of the i (mod 2a) cycle in the corresponding cycle, the output register is regrouped and transferred to the data bus. Data from a set of output registers from i (mod 2a) to i + a-1 (mod 2a) and a set of output registers from i + a (mod 2a) to i + 2a-1 (mod 2a) A synchronous semiconductor memory device, characterized in that a cycle is alternately transferred every a cycle. 4. The synchronous semiconductor memory device according to claim 3, wherein k is 4 and a is 2. A synchronous semiconductor memory device for outputting data serially at least one for each clock cycle, comprising: address fetch means for fetching an address into the device; Decoding means for decoding the fetched address; A memory cell array in which a plurality of memory cells for storing data are arranged; A data bus electrically coupled to the memory cell; Transfer means for transferring data corresponding to the decoded address among the data stored in the memory cell to the data bus; An output register electrically coupled to the data bus; Transfer means for transferring data transferred to said data bus to said output register at a time; And output means for serially outputting a data transmitted to the output register in synchronization with the clock, wherein a signal path from the address fetch means to the output register is separated into N pipeline stages, The data of each pipeline stage is transmitted in m cycles, and when the data access starts from a cycle corresponding to a cycle of the clock, all of the N pipeline stages are separated, When n (= a / m) pipeline stages are passed through and access of data starts from a cycle outside of a cycle of the clock, all of the N pipeline stages are separated and the output registers are k 0 to k-1 in order of data access to the k output registers, respectively. Numbered, and the data output order in the output register is always in the numbered order, and when data access starts from a cycle corresponding to a cycle of the clock, the data transferred to the data bus is zero times. To a set of output registers a to a-1 and a set of output registers a to 2a-1, alternately transmitted a by a cycle, and i (in a cycle in which data access corresponds to a cycle of the clock). mod 2a) When starting from a cycle out of cycles, the output registers are reassembled, and the data transferred to the data bus is rewritten from i (mod 2a) to i + a-1 (mod 2a). A synchronous semiconductor memory device characterized in that a pair of output registers, i.e., i + a (mod 2a) to i + 2a-1 (mod 2a), are alternately transmitted every a cycle. In a synchronous semiconductor memory device having a register type output section, when an address change is made in addition to a register type limit cycle, the data transfer path is divided into a plurality of pipeline stages, and the first data transfer data remains in the data transfer path. Delivers the transfer data corresponding to the changed address until the pipeline stage of the input, inputs transfer data according to the changed address in the data transfer path from outside the limit cycle, and combines the output registers of the output unit. And outputting data serially from the output unit in addition to the limit cycle. An address decoder for inputting an address, decoding the address, and outputting a column select signal to the column select line; A latch gate provided in the column select line; A bit line to which a plurality of memory cells are connected and selected by the column select signal; A local data bus connected to the bit line; A selection gate that selects the local data bus and connects to a global data bus; An output register connected to the global data bus and serially outputting a data using a cycle of clock; And output register control means for receiving an input of a start signal informing of a new burst start in synchronization with the clock, and for changing the combination of the output registers when the start signal is input in a cycle other than the a cycle. Synchronous semiconductor memory device. At least two pipeline stages coupled to a pair of first output registers for serially outputting data according to a set address using at least two cycles of a burst clock and a pair of second output registers for serially output using at least two other cycles. Splittable data transmission path; Detecting means for detecting that either of the pair of the first output register and the pair of the second output register has a reset of an address during a cycle of outputting data; Responsive to the detection instruction of the detection means, divides the data transfer path into at least two pipeline stages so as to obtain a head clock of a cycle of outputting data of either the pair of the first output register or the pair of the second output register. Pipeline dividing means for fetching the reset address into the divided pipeline without waiting; Division changing means for replacing a part of the pair of the first output register and the part of the pair of the second output register in response to a detection instruction in the detecting means and creating a new first output register pair and a new second output register pair; A pair of the new first output register in synchronization with the head clock of a cycle for outputting data of the group of the new first output register and the pair of the new second output register; And output means for serial output using at least two cycles of the burst clock in any of the sets of new second output registers. From the input of the address to the decoding of the input address, the first pipeline stage is used, and from the decoded address to the reading of the data corresponding to the address to the data line, the second pipeline stage is used. From the input to the data line to output the data serially, the third pipeline stage is used, and the internal processing of the signal from the first pipeline stage to the second pipeline stage is performed using a cycle of the clock. A method of operating a synchronous semiconductor memory device, wherein the first pipeline stage and the second pipeline stage are in a through state when the data is accessed from a cycle corresponding to a cycle of the clock, and the clock is rotated. Access of new data from cycle outside cycle a When starting, the first pipeline stage is separated from the second pipeline stage, and internal processing of a signal corresponding to the access of new data is executed in the first pipeline stage, while data before access to new data is performed. And executing the internal processing of the signal corresponding to the access in the second pipeline stage and the third pipeline stage. A data transmission system for controlling data transmission by a clock, comprising: a data transmission path for transmitting a data at a time in parallel, the data transmission path including a pipeline separation unit, and being separated into N pipeline stages; Each of the N separate pipeline stages temporarily holds data; And a control unit for controlling the pipeline stage separation unit, wherein the control unit includes n of n (= N-1) pipeline division units when transmission of a data starts from a cycle corresponding to a cycle. (n = a / m; m is the number of cycles required for data transfer between the separated and adjacent pipeline stages) -1 through, so that a transfer of a data can be performed without separating all of the N pipeline stages. When starting from a cycle different from cycle a, all of the n pipeline separators are activated to separate all of the N pipeline stages. A data transfer system for controlling data transfer by a clock, comprising: a data transfer path for transferring a data at a time in parallel; K registers coupled to the data transfer path, provided that the k registers are numbered from 0 to k-1 in the order of data transfer, respectively; A first control section for controlling data transfer from the data transfer path to the register; When the transfer of the a data starts from a cycle corresponding to cycle a, the first controller alternates between a set of registers 0 to a-1 and a set of registers a to 2a-1. When a data is transferred every a cycle, and the transfer of the a data starts from a cycle out of i (mod 2a) cycles from a cycle, the pair of registers is reorganized, so that i + from i (mod 2a) times. three sets of data are transferred every a cycle alternately with a set of registers a-1 (mod 2a) and a set from i + a (mod 2a) to i + 2a-1 (mod 2a); And a second control unit for controlling data transfer from the register, wherein the second control unit transmits data serially in synchronization with the clock in the order of the number of registers (where k-1 is returned to 0). Data transmission system characterized by. A data transfer system for controlling data transfer by a clock, comprising: a data transfer path in which a data is transferred in parallel at a time, the data transfer path including a pipeline separator, which is separated into N pipeline stages, The N separated pipeline stages each hold data temporarily and are coupled to the data transmission path, with k registers, provided that the k registers are numbered from 0 to k-1 in the order of data transfer. Numbered); A first control unit for controlling the pipeline stage separation unit, wherein the first control unit is one of n (= N-1) pipeline division units when transmission of a data starts from a cycle corresponding to a cycle (n = a / m; m is the number of cycles required for data transfer between the separated and adjacent pipeline stages) -1 and transfer of a data without separating all of the N pipeline stages When starting from a cycle out of cycle a, activate all of the n pipeline separators to separate all of the N pipeline stages; A second control section for controlling data transfer of the register from the data transmission path, wherein the second control section is set from 0 to a-1 when the transfer of the a data starts from a cycle corresponding to a cycle. When a set of registers and a set of registers a to 2a-1 are alternately transferred a data every a cycle, and the transfer of the a data starts from a cycle away from i (mod 2a) cycles. Recompose the pair of registers, registers from i (mod 2a) to i + a-1 (mod 2a), and i + a (mod 2a) to i + 2a-1 (mod 2a) Transfer a data per a cycle alternately up to a set of times; And a third control unit for controlling data transfer from the register, wherein the third control unit transmits data serially in synchronization with the clock in the order of the number of registers (though k-1 is returned to 0). Data transmission system characterized by. A data transfer system for controlling data transfer by a clock, comprising: a data transfer path for transferring data; A register provided in said data transmission path, for converting parallel data transmission to serial data transmission; A separating section for separating the data transfer path into a plurality of pipeline stages when data is transferred in addition to a cycle in which data transfer to the register is restricted; An input unit for inputting transmitted data to at least the first stage of the plurality of separated pipeline stages in addition to a cycle in which data transfer to the register is restricted; And an output unit for serially outputting data from the register from a cycle other than a cycle in which data transfer to the register is restricted. A data transfer system for transferring data one by one, comprising: a data transfer in which a data is transmitted in parallel, and outputs data at a rate a times that of the parallel data transfer; Transmits using a cycle of the clock controlling the transmission, and outputs one transmitted data one by one cycle of the clock controlling the data transmission, and the data transmission path includes N pipes including a pipeline separator. Separated into line stages, and the N separated pipeline stages each hold data temporarily; And a control unit for controlling the pipeline stage separation unit, wherein the control unit includes n of n (= N-1) pipeline division units when transmission of a data starts from a cycle corresponding to a cycle. (n = a / m; m is the number of cycles required for data transfer between the separated and adjacent pipeline stages) -1 through, transfer of a data without separating all of the N pipeline stages When starting from a cycle different from this a cycle, all of the n pipeline separators are activated to separate all of the N pipeline stages. A data transfer system for transferring data one by one, comprising: a data transfer in which a data is transmitted in parallel, and outputs data at a rate a times that of the parallel data transfer; K registers, which are transmitted using a cycle of the clock controlling the transmission, and output one transmitted data one by one cycle of the clock controlling the data transmission, and are coupled to the data transmission path, provided the k registers are numbered from 0 to k-1 in the order of data transfer respectively; And a first control unit for controlling data transfer from the data transfer path to the register, wherein the first control unit is configured to select a-1 from 0 when a transfer of the a data starts from a cycle corresponding to a cycle. A set of registers up to and a set of registers a to 2a-1 are alternately transferred, so that a data is transferred every a cycle, and the transfer of the a data is from a cycle deviating from i (mod 2a) cycles by a cycle. When initiated, the pair of registers is reorganized so that the pair of registers from i (mod 2a) to i + a-1 (mod 2a) and i + 2a-1 from i + a (mod 2a) In order to control the transfer of data from the registers alternately in the order of (mod 2a), and to control the data transfer from the register, the data is transmitted serially in synchronization with the clock in the order of the register number. (Where, following a single k-1 is returned to 0), the data transfer system comprises a second control unit. A data transmission system for transferring data one by one, comprising: a data transmission in which a data is transmitted in parallel, and outputs data at a rate a times that of the parallel data transmission; Transmits using a cycle of the clock controlling the transmission, and outputs one transmitted data one by one cycle of the clock controlling the data transmission, and the data transmission path includes N pipes including a pipeline separator. It can be separated into line stages, and N separated pipeline stages each hold data temporarily, and each of k registers coupled to the data transmission paths, except for k registers, from 0 in the order of data transfer, respectively. numbering k-1); A first control unit for controlling the pipeline stage separation unit, wherein the first control unit includes n (= N-1) of the pipeline separation units when a data transmission starts from a cycle corresponding to a cycle. n = a / m; m is the number of cycles required for data transfer between the separated and adjacent pipeline stages) -1, and a transfer of a data is performed without separating all of the N pipeline stages. when starting from a cycle out of cycle a, activate all of the n pipeline separators to separate all of the N pipeline stages; A second control unit for controlling the data transfer from the data transfer to the register, the second control unit being configured from 0 to a-1 when the transfer of the a data starts from a cycle corresponding to a cycle A pair of registers and a set of registers a through 2a-1 alternately transfer a piece of data every a cycle, and the transfer of a piece of data may begin from a cycle outside of a (mod 2a) cycle from a cycle. When the pair of registers is reorganized, the pair of registers from i (mod 2a) to i + a-1 (mod 2a) and i + a (mod 2a) to i + 2a-1 (mod 2a) ) A data set is sent in cycles alternately up to; And a third control unit for controlling the data transfer from the register, and serially transferring data in synchronization with the clock in the order of the register number (though k-1 returns to 0). Data transmission system. A synchronous memory system, comprising: a synchronous memory unit controlled in synchronization with a system clock; And a control unit for controlling burst data access from the synchronous memory unit, wherein the control unit sets a limit of a cycle for inputting a head address for new burst data access during burst data access when the frequency of the system clock is low. Rather, always input the head address, set the limit of the cycle for inputting the head address for a new burst data access during burst data access, and set the head address only in this limited cycle. And a synchro memory system. In a synchronous memory system, a synchronous memory unit controlled in synchronization with a system clock, the synchronous memory unit transfers a bit of data from the memory in parallel, and outputs a bit of data transferred in parallel using a cycle, The synchronous memory unit may change the number of internal pipeline stages; And a control unit for controlling the synchronous memory unit, wherein the control unit includes a first method for requesting a change of a cycle even from a cycle different from the a cycle and a second request for a change of a cycle from a cycle corresponding to the a cycle at all times. Corresponding to any one of the methods, and when the controller is the first method, the controller either increases the number of the pipeline stages from the constant number and increases the number of the pipeline stages from the constant number. And when the controller is the second method, the controller controls the number of the pipeline stages as the predetermined number.