KR100220679B1 - Equalizer of a digital vcr - Google Patents

Abstract

The present invention relates to an equalizer of a digital V.C.R, wherein the phase compensator 200 compensates for a phase error of an input video signal and a time delay of a signal provided from the phase compensator 200. A delay unit 210 composed of a plurality of unit delays to be output, a multiplier 220 composed of a plurality of multipliers for multiplying a signal delayed by each delay unit in the delay unit 210 with respective filter coefficients, and a multiplier unit A three-value determination unit 240 for determining the sum of the outputs of the 220 at three values, a comparator 250 for generating an error signal by comparing the sum output with the output signal of the three-value determination unit 240, and a comparison unit. The error signal of 250 and the filter coefficient and the input video signal, each time delayed signal and the error signal are calculated according to the Least Mean Square (LMS) algorithm to generate updated filter coefficients, which are symmetric to each multiplier in the multiplier. Provided by Can include updating unit 260. The

Therefore, the present invention has the advantage that the adjustment of the filter coefficient is easy because the weight of the filter coefficient is simple.

Description

Digital V. Seed. Egg's equalizer

1 is a block diagram showing an equalizer of a conventional digital BCAL.

2 is a block diagram showing an equalizer of a digital VRL according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

200: phase compensation unit 210: delay unit

220: multiplication unit 230: calculation unit

240: three-value determination unit 250: comparison unit

260: coefficient update unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer of a digital video cassette recorder (hereinafter, abbreviated as digital V. C. al.), And in particular to adjusting the weight by symmetrically setting the weight of filter coefficients used in the equalizer. Digital V. C. Equalizer.

In general, V.C.R is a device used to record and play back video signals, record and play back other tapes, record in the absence of time, and record video signals through a camera. Since the development of the analogue V.C.al for broadcasting by the analog system, the V.R.A. technique of the analogue method has come to the present day thanks to the rapid development of precision machining and semiconductor technology.

In addition, in recent years, in the transmission of a video signal, a digital method of converting an analog video signal to digital transmission and recording is possible because of the fact that digital transmission can maintain a much better image quality than analog transmission. The development of V. C. eggs is also developing.

On the other hand, in the transmission of such a digital signal, the signal transmitted from the transmitting end is a variety of distortion occurs through the transmission channel. The causes of such distortion include deformation by Gaussian thermal noise, impulsive noise, addition or multiplication noise by fading, frequency variation, nonlinearity, and temporal dispersion.

This distortion appears as a deterioration of image quality in digital V. eggs that record and play existing analog signals, while bit detection errors occur in digital V. eggs that record and reproduce transmitted digital signals. There is a possibility that reconstruction of the image may be impossible or a completely different image may appear. In particular, the multiple paths caused by the time delay and phase change of the transmission signal cause severe inter-symbol interference, which is a major cause of bit detection error.

This technique of reducing bit detection errors by compensating for distortion caused by non-ideal transmission channels is called channel equalization.

The channel equalization technique has been studied steadily since Widrow and Hopf proposed the Least Mean Square (LMS) adaptive filter technique. Initially, the linear equalization technique has been studied. Nonlinear equalization techniques such as equalization technique, crystal feedback equalization technique, etc. using RLS (Recursive Least Square) algorithm with improved convergence characteristics have been studied.

On the other hand, in the digital V.C.R, as the transmission channel of the digital data is high density, there is a problem that the distortion of the reproduction waveform may occur severely due to the interference between signals during reproduction of the recorded digital data.

Fig. 1 shows a block diagram of a conventional V. C. equalizer for preventing distortion of such reproduction waveforms.

1 shows a conventional digital V.C.E. equalizer, which includes a delay unit 10 for unit delaying and outputting a video signal to be reproduced and input, and an input signal k and a delay. Delayed signals k (n-1), k (n-2), k (n-3), k (n-4), which are output from the unit 10, are given a predetermined filter coefficient ( 0, One, 2, 3, 4 to multiply and output the multiplier 20 for multiplying the output signal of the multiplier 20, the first operator 30 for summing the output signals of the multiplier 20, and the output signal of the first operator 30. A second operation unit 50 for comparing and calculating the value determination unit 40, the output signal of the first operation unit 30, and the output signal of the three-value determination unit 40 to detect and output the error signal; Each of the third operation unit 60 that calculates an average error value by calculating an error signal provided from the calculation unit 50 and each of the multiplication unit 20 based on the average error value provided from the third operation unit 60. Constant for updating the filter coefficients of ) And the constant and filter coefficients provided from the comparison determination unit 70, the video signal reproduced and input, and the error signal provided from the second operation unit 50. Is updated according to the Least Mean Square (LMS) algorithm to update each filter coefficient and provide the updated filter coefficient to the multipliers 21, 22, 23, 24, and 25 in the multiplier 20. ).

Delay unit 10 is composed of k, for example four unit delay (11, 12, 13, 14), each of the unit delay (111, 12, 13, 14) is input signal k Output the delayed signal x (n-1), x (n-2), k (n-3), k (n-4) by the unit delay to the next stage delayer and multiplier 20 do.

The multiplier 20 is composed of k + 1, for example, five multipliers 21, 22, 23, 24 and 25, and each multiplier 21, 22, 23, 24 and 25 is an input signal κ. ) And delayed video signals (x (n-1), x (n-2), k (n-3), outputted from the respective delay units 11, 12, 13, 14 in the delay unit 20, k (n-4)) is the corrected filter coefficient ( 0, One, 2, 3, Multiply by 4) and output. Where filter coefficients ( 0, One, 2, 3. 4) are correctable values for optimal equalization.

The first operator 30 adds up the signal multiplied by the multipliers 21, 22, 23, 24, and 25 in the multiplier 20, and adds the signal y to the three-value determination unit 40 and the second. Output to operation unit 50. The process performed by the first operation unit 30 described above may be represented by Equation 1 below.

In Equation 1, y (k) is an input signal, W (k) is a corrected filter coefficient, and X (k) represents an input signal.

On the other hand, the delay unit 10, the multiplier 20 and the first calculation unit 30 represents a general transversal filter structure, which is well known in the art, so a detailed description thereof will be omitted.

The three-value determination unit 40 determines the output signal of the first operation unit 30 in three values, namely, "+ high", "0" and "-high". Judgment by one signal and output. Thereafter, the second operation unit 50 compares the output signal of the first operation unit 30 and the output signal of the three-value determination unit 40 to detect the error signal e. The process performed by the second operator 50 may be represented by Equation 2 below, and the error signal detected by the second operator 50 may be transferred to the third operator 60 and the filter coefficient updater 80. Is provided.

In Equation 2, e (k) is an error signal, d (k) represents the output signal of the three-value determination unit 40.

On the other hand, the third operation unit 60 generates the error signal provided from the second operation unit 50 by a predetermined calculation process, that is, by the method of ∑ (e (k) ² / n) to compare the next stage. The determination unit 70 provides.

The comparison judging unit 70 compares the average error value provided from the third operation unit 60 with the reference error value to update each filter coefficient of the multiplication unit 20 ( Determine the value. Constant determined by the comparison determination unit 70 ) Value is provided to the filter coefficient updating unit 80.

The filter coefficient updating unit 80 may include the constants provided from the comparison determination unit 70. ) And the previous filter coefficients provided to multiplier 20 ( 0, One, 2, 3, 4) And the filter coefficient is corrected by calculating the input video signal k and the error signal provided from the second calculator 50 according to the Least Mean Square (LMS) algorithm. In this case, the process performed by the filter coefficient updating unit 80 may be expressed as Equation 3 below.

The filter coefficient corrected by the filter coefficient updater 80 is provided to the multiplier 20 for use in processing the next input video signal.

However, the above-described prior art digital V.C.Er equalizers all have different weights of the respective filter coefficients, and use the different filter coefficients to simultaneously compensate for the phase and amplitude so that each filter coefficient is updated. The operation was complicated and difficult to adjust.

Therefore, the present invention has been proposed to solve the above-described problem, and the present invention is to set the weight of the filter coefficients symmetrically so that it is easier to update and adjust the filter coefficients. To provide an equalizer.

Digital V. C. equalizer according to the present invention for achieving the above object is a phase compensation unit for compensating for the phase error of the input video signal; A delay unit configured to delay and output a phase-compensated video signal outputted from the phase compensation unit for a unit time; Each multiplier includes a signal and a filter coefficient delayed by the output signal of the phase compensator and each unit delay in the delay unit. One, A multiplier for multiplying 2); An operation unit for summing output signals of each multiplier in the multiplier; A three-value determination unit which determines three values of the output signal of the operation unit; A comparator for comparing an output signal of the calculator and an output signal of the three-value determiner to detect an error signal; The error signal detected from the comparator and the filter coefficient ( One, 2), the output signal of the phase compensator and the output signal of each unit delayer are calculated according to a Least Mean Square (LMS) algorithm to update the filter coefficients, and the updated filter coefficients are respectively multiplied in the multiplier. It characterized in that it comprises a coefficient updater provided symmetrically.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a digital V. C. equalizer according to a preferred embodiment of the present invention.

As shown in FIG. 2, the digital V.C.E. equalizer of the present invention includes a phase compensator 200, a delay unit 210, a multiplier 220, a calculator 230, and a three-plate. A government unit 240, a comparison unit 250, and a coefficient updater 260 are included.

The phase compensator 200 adjusts the phase error of the input video signal and outputs the phase error-adjusted video signal to the multiplier 220 and the delay unit 210.

The delay unit 210 includes k delay units 211, 212, 213, and 214, and each delay unit 211, 212, 213, 214 delays the signal compensated by the phase compensator 200 by a unit time and delays the signal x (k-1). , x (k-2), x (k-3) and x (k-4)) are output to the delay unit. The signals x (k-1), x (k-2), x (k-3), and x (k-4) delayed by the respective unit delays 211, 212, 213, and 214 in the delay unit 210 are multipliers. The delayed signal x (k-2) is directly output to the operation unit 230.

The multiplier 220 includes k multipliers 221, 22, 223, and 224, and each multiplier 221, 22, 223, 224 has an updated filter coefficient (1). One, 2) is symmetrically received, while the other inputs the output of the phase compensator 200 and the output signals from the delay unit 210 (x (k), x (k-1), x (k-3). ), x (k-4)) is received, and the multiplication operation is performed. In more detail, the first multiplier 221 may output the output x (k) and the first filter coefficient of the phase compensator 200. 1), and the second multiplier 222 outputs the output x (k-1) of the first delay unit 211 and the second filter coefficient ( 2), and the third multiplier 223 outputs the output of the third delay unit 213 (x (k-3)) and the first filter coefficient ( 1), and the fourth multiplier 224 outputs the output x (k-4) of the fourth delay unit 214 and the second filter coefficient ( 2) the filter coefficient ( One, 2) are symmetrically received and multiplied by the corresponding delayed signal. Where filter coefficient ( One, 2) are updatable values for optimal equalization. One, If 2) is symmetric about the time axis, it has a linear phase response in the frequency domain. That is, all components of the input signal passing through the filter are delayed by the same amount in time.

The calculator 230 adds the signals multiplied by the multipliers 221, 222, 223, 224, and 225 in the multiplier 220, and outputs the multiplied signals to the tern determination unit 240 and the comparator 250. The process performed by the operation unit 230 described above may be represented by Equation 4 below.

In Equation 4, y (k) is an input signal, W (k) is a corrected filter coefficient, and X (k) represents an input signal.

The delay unit 210, the multiplier 220, and the calculation unit 230 described above represent a general transverse filter structure, which is well known in the art, and thus a detailed description thereof will be omitted.

The three-value determination unit 240 determines the output signal of the operation unit 230 in three values, namely, "+ high", "0", "-high", respectively. Judging by a signal and outputting. Thereafter, the comparator 250 compares the output signal of the calculator 230 and the output signal of the ternary judgment unit 240 to detect and output the error signal.

In this case, the error signal may be expressed as Equation 5 below.

In Equation 5, e (k) is an error signal, d (k) represents the output signal of the three-value determination unit 240.

The filter coefficient updating unit 260 may provide the previous filter coefficients provided to the multiplication unit 20 ( One, 2), the output signal x (k) of the phase compensator and the time delayed signals x (k-1), x (k-2), x (k-3), x (k-4), and The error signal e (k) provided from the comparator 250 is calculated according to a Least Mean Square (LMS) algorithm, and each filter coefficient ( One, Update 2). The updated filter coefficient is calculated as shown in Equation 6 below.

here, Is the filter coefficient for each One, 2) indicates a constant value for updating.

In addition, the filter coefficient updating unit 260 may update the filter coefficient ( One, 2) is provided symmetrically to the multiplier 220. That is, the filter coefficient updater 260 may update the first filter coefficient (for the multipliers 221, 222, 223, and 224 symmetrically configured in the multiplier 220). 1) is provided to the multipliers 222 and 223, and the updated second filter coefficient ( Symmetrically distributes the updated filter coefficients in such a way that 2) is provided to multipliers 221, 224. Thus, the calculation of the filter coefficients can be simplified because the weights of the filter coefficients are provided symmetrically to the multiplier 220 and only two values.

Therefore, the present invention has the advantage that the filter coefficients, that is, the filter coefficients can be easily adjusted because the weight of the filter coefficients is simple.

Claims (1)

Phase error of an input video signal in an equalizer of a digital V.R. to prevent distortion of a reproduction waveform due to interference between reproduction reports recorded at a high density during reproduction of digital data recorded in a digital V.R. A phase compensator 200 for compensating for; A plurality of unit delayers 211, 212, 213, and 214, each of which includes a delay unit 210 for delaying and outputting a phase compensated video signal output from the phase compensator 200 for a unit time; And a plurality of multipliers 221, 222, 223, and 224, each of which is a signal delayed by the output signal of the phase compensator 200 and each of the unit delays 211, 212, 213, and 214 in the delay unit 210. One, A multiplier 220 for multiplying 2); An operation unit 230 for summing output signals of the respective multipliers 221, 222, 223 and 224 in the multiplier 220; A three-value determination unit 240 for determining the output signal of the operation unit 230 in three values; A comparator 250 for comparing an output signal of the calculator 230 and an output signal of the ternary determiner 240 to detect an error signal; The error signal detected from the comparator 250 and the filter coefficient ( One, 2) the output signal of the phase compensator 200 and the output signals of the respective unit delayers 211, 212, 213, and 214 are calculated according to a least mean square (LMS) algorithm to update the filter coefficients, and the updated filter coefficients. And a coefficient updater (260) for providing symmetrically to each of the multipliers (221, 222, 223, 224) in the multiplier.