KR100218540B1 - Manufacturing method of semiconductor pressure sensor - Google Patents
Manufacturing method of semiconductor pressure sensor Download PDFInfo
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- KR100218540B1 KR100218540B1 KR1019960051373A KR19960051373A KR100218540B1 KR 100218540 B1 KR100218540 B1 KR 100218540B1 KR 1019960051373 A KR1019960051373 A KR 1019960051373A KR 19960051373 A KR19960051373 A KR 19960051373A KR 100218540 B1 KR100218540 B1 KR 100218540B1
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- diaphragm
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- oxide film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000227 grinding Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000000059 patterning Methods 0.000 claims abstract 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 36
- 239000010408 film Substances 0.000 description 19
- 238000002955 isolation Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005251 gamma ray Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/30—Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
- H10N30/302—Sensors
Abstract
본 발명은 반도체 압력 센서의 제조 방법에 관한 것으로서, 더욱 상세하게는 압력센서의 다이아프램 형성시 백 사이드 얼라인 불량으로 인한 액티브 소자 및 다이아프램과의 얼라인 불량을 제거하고, 웨이퍼 인터페이스에서의 보이드(Void) 생성을 억제하기 위하여 종래의 SOI 웨이퍼 제조 공정을 개선한 것으로서 첫째, 절연 기판 위에 산화막을 형성하는 단계, 둘째, 상기 산화막 위에 질화막을 증착하는 단계, 셋째, 다이아프램이 형성될 부위를 패터닝한 후 질화막 및 산화막을 식각하여 다이아프램이 형성될 부위를 개방하는 단계, 넷째, 상기 개방된 질화막 및 산화막을 마스크로 하여 절연기판을 에칭하고 질화막을 제거하는 단계, 다섯째, 실리콘 단결정 웨이퍼를 상기 산화막 위에 본딩하는 단계, 여섯째, 상기 실리콘 단결정 웨이퍼를 평탄화 하는 단계, 일곱째, 상기 실리콘 단결정 웨이퍼 상에 액티브소자를 형성하는 단계 및 끝으로 상기 절연기판의 후면을 그라인딩하여 다이아프램을 형성하는 단계로 이루어진 반도체 압력센서의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure sensor, and more particularly, to eliminate alignment defects between an active element and a diaphragm due to backside alignment defects during diaphragm formation of a pressure sensor, and to void in a wafer interface. Improvement of the conventional SOI wafer manufacturing process in order to suppress (Void) generation, first, forming an oxide film on the insulating substrate, second, depositing a nitride film on the oxide film, third, patterning the site where the diaphragm will be formed And etching the nitride film and the oxide film to open the portion where the diaphragm is to be formed. Fourth, etching the insulating substrate using the open nitride film and the oxide film as a mask, and removing the nitride film. Bonding on, sixth, planarizing the silicon single crystal wafer Type, the seventh, the present invention relates to a method for producing the silicon single crystal wafer for grinding a back surface of the insulating substrate and the step of forming the end of the active element consisting of a diaphragm forming a semiconductor pressure sensor.
Description
본 발명은 반도체 압력 센서의 제조 방법에 관한 것으로서, 더욱 상세하게는 종래의 SOI 웨이퍼 제조기술을 이용한 압력 센서 제조 방법의 개선에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor pressure sensor, and more particularly, to an improvement in a method for manufacturing a pressure sensor using a conventional SOI wafer manufacturing technique.
SOI (Silicon on Insulator)웨이퍼란 절연 기판 상에 형성된 반도체를 뜻하는 것으로서, 실리콘 기판에 형성된 산화막 또는 측벽을 사용하여 액티브 소자를 분리(isolation)하는 졍션 분리(Junction isolation)구조를 가지는 벌크 실리콘 집적회로의 취약점을 극복하기 위하여 개발되고 있다. 즉 벌크 실리콘 집적회로에서 액티브 소자의 분리에 사용되는 졍션 분리법(Junction isolation)은 통상적인 도핑레벨 및 소자 구조하에서는 졍션 브레이크다운 전압인 30V정도의 고전압이 공급되는 소자에는 사용될 수 없다. 또한 졍션 분리법을 사용한 소자는 감마 레이에 의하여 pn접합부에 형성되는 일시적인 광전류가 존재하므로, 강한 광이 조사되는 환경에서 사용될 수 없는 단점이 있다. 이러한 벌크 실리콘 집적회로의 졍션 분리구조에 비하여, 일반적으로 SOI기술은 1)소자간의 기생용량이 적은데 기인한 빠른 동작속도, 2)낮은 전력소모, 3)큰 집적도, 4) α입자에 의한 면역성, 5)공정의 단순함, 6) CMOS 에서의 래치업 문제가 없는 점, 7)기판을 통한 소자간의 간섭효과가 없는 점, 8)설계의 용이성 및 유연성, 9)높은 잡음 영역 및 10) 3차원 집적회로 설계의 가능성 때문에 최근에 본격적으로 연구되고 있다. 이러한 SOI웨이퍼의 제조방법에는 다이일렉트릭 아이솔레이션(Dielectric isolation), 정전기 접합기술 및 실리콘 다이렉트 본딩(Silicon Direct Bonding: SDB) 기술 등이 있으며, 이러한 기술을 응용하여 다이아프램을 가진 압력센서를 제조할 수 있다. 반도체 소자를 이용한 압력센서는 반도체 결정에 압력을 가하면 반도체 소자에 흐르는 전기 저항이 변화하는 압전 효과(piezo-electric effect)를 이용하는 것으로서 통상 박막의 형태로 제제조되어 사용된다. 이때 사용되는 반도체 결정에는 압력에 의해 금제대(禁制帶)의 폭이 변화하며 그에 따라서 캐리어 농도가 변화하는 등방적인 성질을 가진것 및 결정의 등에너지면이 복잡한 형상을 가지고 있고 전도 전자의 이동성에 방향이 있으며, 적당한 방향으로 압력을 가하면 전자의 분포가 변화하는 이방적인 성질을 가진것이 있다.A silicon on insulator (SOI) wafer is a semiconductor formed on an insulating substrate, and is a bulk silicon integrated circuit having a junction isolation structure for isolating active devices using an oxide film or sidewall formed on a silicon substrate. It is developed to overcome the weaknesses of. In other words, the junction isolation method used for the isolation of the active device in the bulk silicon integrated circuit cannot be used for a device to which a high voltage of about 30 V, which is a junction breakdown voltage, is supplied under the usual doping level and device structure. In addition, since the device using the section isolation method has a temporary photocurrent formed in the pn junction part by gamma ray, it cannot be used in an environment where strong light is irradiated. Compared with the isolation isolation structure of bulk silicon integrated circuits, SOI technology generally includes 1) fast operating speed due to low parasitic capacitance between devices, 2) low power consumption, 3) high integration, 4) immunity by α particles, 5) simplicity of process, 6) no latch-up problem in CMOS, 7) no interference effect between devices through substrate, 8) ease of design and flexibility, 9) high noise area and 10) 3D integration Recently, due to the possibility of circuit design has been studied in earnest. Such SOI wafer manufacturing methods include electric isolation, electrostatic bonding technology, and silicon direct bonding (SDB) technology, which can be used to manufacture pressure sensors with diaphragms. . BACKGROUND ART A pressure sensor using a semiconductor device uses a piezo-electric effect in which electrical resistance flowing to a semiconductor device changes when a pressure is applied to a semiconductor crystal, and is usually manufactured and used in the form of a thin film. At this time, the semiconductor crystal used has an isotropic property in which the width of the metal band is changed by the pressure and the carrier concentration is changed accordingly, and the isoenergy plane of the crystal has a complicated shape. Direction, there is an anisotropic property that the distribution of electrons changes when pressure is applied in the proper direction.
이하 첨부된 도면을 참조하여 종래의 압력 센서의 제조방법을 설명하면 다음과 같다. 도1은 종래의 실리콘 접합법을 이용한 압력센서 제조방법을 도시한 것이다. 도 1에 도시하였듯이, 종래의 압력센서의 제조 방법은 FZ웨이퍼(1)와 핸들웨이퍼(4)에 산화막(3)을 형성한 후, 두 웨이퍼 (1)(4)를 실리콘 기판 접합 기술(Silicon Direct Bonding: SDB)을 이용하여 본딩한다. 그 후 FZ웨이퍼(2)를 그라인딩 및 CMP(Chemical and Mechanical Polishing: 화학적 기계연마)와 같은 물리적 평탄화 방법을 이용하여 액티브 소자 형성에 필요한 두께만 남도록 가공한 후 FZ 웨이퍼(2)상에 액티브 소자를 형성한다. 여기서 FZ 웨이퍼는 반도체의 액티브소자가 형성되는 그라인딩된 웨이퍼로서, 통상의 플로트 존(FLOAT ZONE)법에 의하여 형성된 단결정 실리콘 웨이퍼를 말한다. 또한 핸들 웨이퍼는 FZ웨이퍼의 플레이트가 되는 웨이퍼를 말한다. 다음으로 액티베이션 소자(2)가 형성되면 다이아프램(7)을 형성하기 위해 핸들웨이퍼(4)의 후면을 백 사이드 얼라인하고 에칭 하여 다이아프램(7)을 가진 압력센서를 제조하게 된다.Hereinafter, a manufacturing method of a conventional pressure sensor will be described with reference to the accompanying drawings. Figure 1 shows a pressure sensor manufacturing method using a conventional silicon bonding method. As shown in FIG. 1, in the conventional method of manufacturing a pressure sensor, an oxide film 3 is formed on an FZ wafer 1 and a handle wafer 4, and then two wafers 1 and 4 are bonded to a silicon substrate. Bonding is performed using Direct Bonding (SDB). The FZ wafer 2 is then processed using physical planarization methods such as grinding and CMP (Chemical and Mechanical Polishing) to leave only the thickness necessary for the formation of the active element, and then the active element is placed on the FZ wafer 2. Form. Here, the FZ wafer is a ground wafer on which an active element of a semiconductor is formed, and refers to a single crystal silicon wafer formed by a conventional float zone method. In addition, a handle wafer means the wafer used as a plate of a FZ wafer. Next, when the activation element 2 is formed, the back side of the handle wafer 4 is back-side aligned and etched to form the diaphragm 7, thereby manufacturing a pressure sensor having the diaphragm 7.
이러한 종래의 기술을 이용하여 압력센서를 제조하게 되면 상기 백 사이드 얼라인 공정시 얼라인 키가 없기 때문에 액티브 소자(2)가 형성된 영역 및 다이아프램(7)이 형성되는 영역에 미스 얼라인이 생기는 문제점이 있다. 또한 실리콘 기판 접합 (Silicon Direct Bonding: SDB)을 하기 때문에 FZ 웨이퍼(2)와 핸들웨이퍼(4) 경계면에 보이드(void)가 형성되어 제품의 품질이 저하되고 수율을 저하되는 문제점이 있다.When the pressure sensor is manufactured using the conventional technique, since there is no alignment key during the back side alignment process, misalignment occurs in the region where the active element 2 is formed and the region where the diaphragm 7 is formed. There is a problem. In addition, since silicon direct bonding (SDB) is performed, voids are formed at the interface between the FZ wafer 2 and the handle wafer 4, thereby degrading product quality and lowering yield.
또 다른 종래의 압력센서의 제조방법이 도2에 도시되어 있다. 도2에 도시되었듯이 이 방법은 에피텍셜 레이어 형성법을 이용한 것으로서, 핸들웨이퍼(4)를 P+로 고농도 도핑(6)한 다음 에피택셜 레이어(5)를 형성시킨다. 다음으로 에피택셜 레이어(5)상에 통상의 공정으로 액티베이션 레이어(2: 액티브 소자)를 형성하고 액티베이션 레이어(2)가 형성되면 앞에서 기술한 것과 같은 방법으로 핸들 웨이퍼(4)의 백 사이드 얼라인을 통해 다이아프램(7)의 위치를 정의하고 핸들웨이퍼(4)를 에칭함으로써 압력센서를 제조하는 기술이다. 이러한 방법으로 압력센서를 제조한 경우에도 얼라인 키가 없는 상태에서 백 사이드 얼라인을 이용하여 다이아프램을 형성하기 때문에 액티베이션 레이어와 다이아프램 영역간에 얼라인 불량이 일어날 수 있다.Another conventional method of manufacturing a pressure sensor is shown in FIG. As shown in Fig. 2, the method uses an epitaxial layer forming method, in which the handle wafer 4 is heavily doped with P +, and then the epitaxial layer 5 is formed. Next, when the activation layer 2 (active element) is formed on the epitaxial layer 5 in a normal process and the activation layer 2 is formed, the back side alignment of the handle wafer 4 is performed in the same manner as described above. It is a technique for manufacturing a pressure sensor by defining the position of the diaphragm 7 and etching the handle wafer (4) through. Even if the pressure sensor is manufactured in this way, since the diaphragm is formed using the back side alignment without the alignment key, alignment defects may occur between the activation layer and the diaphragm region.
따라서 본 발명은 백 사이드 얼라인 불량으로 인한 액티브 소자와 다이아프램과의 얼라인 불량을 제거하고, 웨이퍼 인터페이스에서의 보이드 생성을 억제하기 위한 개선된 압력센서 제조 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide an improved pressure sensor manufacturing method for eliminating alignment defect between an active element and diaphragm due to back side alignment defect and suppressing void generation at the wafer interface.
도1은 종래의 실리콘 접합법을 이용한 반도체 압력센서의 제조방법을 도시한 것이며,Figure 1 shows a method of manufacturing a semiconductor pressure sensor using a conventional silicon bonding method,
도2는 종래의 에피택셜 레이어 성장법을 이용한 반도체 압력센서의 제조방법을 도시한 것이며,2 illustrates a method of manufacturing a semiconductor pressure sensor using a conventional epitaxial layer growth method.
도3A 내지 3F는 본 발명의 반도체 압력센서의 제조방법을 도시한 것이며,3A to 3F illustrate a method of manufacturing a semiconductor pressure sensor of the present invention.
도4는 본 발명의 개량된 반도체 압력센서의 제조공정중 생성되는 홀을 가지는 절연기판의 사시도이다.4 is a perspective view of an insulating substrate having holes created during the manufacturing process of the improved semiconductor pressure sensor of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : FZ웨이퍼 2 : 액티브 소자1: FZ wafer 2: Active element
3 : 산화막 4 : 핸들웨이퍼3: oxide film 4: handle wafer
5 : 에피택셜 레이더 6 : P+층5: epitaxial radar 6: P + layer
7 : 다이아프램 8 : 질화막7: diaphragm 8: nitride film
9 : 홀9: hole
상기 목적을 달성하기 위한 본 발명의 반도체 압력센서의 제조방법은 첫째, 절연 기판 위에 산화막을 형성하는 단계, 둘째, 상기 산화막 위에 질화막(nitride layer)을 증착하는 단계, 셋째, 다이아프램이 형성될 부위를 패터닝한 후 질화막 및 산화막을 식각하여 다이아프램이 형성될 부위를 개방하는 단계, 넷째, 상기 개방된 질화막 및 산화막을 마스크로 하여 상기 절연기판을 에칭하고 질화막을 제거하는 단계, 다섯째, 실리콘 단결정 웨이퍼를 상기 산화막 위에 본딩하는 단계, 여섯째, 상기 실리콘 단결정 웨이퍼를 평탄화 하는 단계, 일곱째, 상기 실리콘 단결정 웨이퍼 상에 액티브소자를 형성하는 단계 및 끝으로 상기 절연기판의 후면을 그라인딩하여 다이아프램을 형성하는 단계로 이루어진다.The method of manufacturing a semiconductor pressure sensor of the present invention for achieving the above object comprises the steps of: first, forming an oxide film on an insulating substrate, second, depositing a nitride layer on the oxide film, and third, a part where a diaphragm is to be formed. And etching the nitride film and the oxide film to open the portion where the diaphragm is to be formed. Fourth, etching the insulating substrate using the open nitride film and the oxide film as a mask, and removing the nitride film. Bonding to the oxide layer, sixth, planarizing the silicon single crystal wafer, seventh, forming an active element on the silicon single crystal wafer, and finally grinding the back surface of the insulating substrate to form a diaphragm. Is made of.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.
도3은 본 발명의 일 실시예에 따른 압력 센서의 제조 공정을 도시한 것이다. 도3에서 도면 부호 8은 질화(nitride)막이고, 도면부호 7은 다이아프램을 나타낸다. 본 발명에 따른 압력 센서의 제조방법은, 도3A에 도시되었듯이, 먼저 핸들 웨이퍼(4)에 산화막(3)을 성장시킨 후, 질화막(8)을 증착하여 액티브소자(2)가 형성될 부위를 정의한다.Figure 3 illustrates a manufacturing process of the pressure sensor according to an embodiment of the present invention. In Fig. 3, reference numeral 8 denotes a nitride film, and reference numeral 7 denotes a diaphragm. In the manufacturing method of the pressure sensor according to the present invention, as shown in FIG. 3A, the oxide film 3 is first grown on the handle wafer 4, and then the nitride film 8 is deposited to form the active element 2. Define.
다음으로 도 3B에 도시하였듯이, 다이아프램이 형성될 부위를 패터닝하여 질화(8)막 및 산화막(3)을 식각에 의하여 개방한다. 다음으로 질화막(8)과 산화막(3)을 마스크로 하여 핸들 웨이퍼(5)를 300-400 μm 까지 에칭한다(도3C 참조). 이때 상기 에칭과정에서 질화막(8)은 제거된다. 이어서 도3D에 도시되었듯이, FZ웨이퍼(1)를 실리콘 접합 기술(SDB)을 이용하여 본딩하고 그라인딩 및 CMP(Chemical and Mechanical Polishing: 화학적 기계연마)하여 액티브 소자 형성에 필요한 두께로 FZ웨이퍼(4) 두께를 조절한다. 이후 도3E에 도시한 바와 같이 통상의 방법을 사용하여 액티브 소자(2)를 FZ웨이퍼(4)상에 형성한다. 끝으로 도3F에 도시되었듯이, 액티브소자(2)가 형성되면 핸들 웨이퍼(4)의 후면을 그라인딩하여 다이아프램을 형성한다. 이 때 핸들 웨이퍼(4) 두께가 300-400 μm만 남게 하여 도 4에 도시된 바와 같은 홀(9)이 만들어지도록 한다. 이 때 만들어진 홀(9)은 압력센서의 다이아프램(7)이 형성되는 영역으로 이용되면서 백 사이드 얼라인 키로 활용 가능한 장점이 있다. 이상과 같은 공정에서 상기 핸들 웨이퍼(4)의 그라인딩 과정 및 액티브 소자(2) 및 다이아프램 형성 과정은 그 순서를 바꾸어 실행할 수 도 있다.Next, as shown in FIG. 3B, the portion where the diaphragm is to be formed is patterned to open the nitride 8 film and the oxide film 3 by etching. Next, the handle wafer 5 is etched to 300-400 µm using the nitride film 8 and the oxide film 3 as a mask (see Fig. 3C). At this time, the nitride film 8 is removed in the etching process. Subsequently, as shown in FIG. 3D, the FZ wafer 1 is bonded using a silicon bonding technique (SDB), ground and chemically polished (CMP), and the FZ wafer 4 is formed to a thickness necessary for forming an active device. ) Adjust the thickness. Thereafter, as shown in Fig. 3E, the active element 2 is formed on the FZ wafer 4 using a conventional method. Finally, as shown in FIG. 3F, when the active element 2 is formed, the back surface of the handle wafer 4 is ground to form a diaphragm. At this time, the thickness of the handle wafer 4 is left only 300-400 μm so that the hole 9 as shown in FIG. 4 is made. The hole 9 made at this time is used as an area in which the diaphragm 7 of the pressure sensor is formed. In the above process, the grinding process of the handle wafer 4 and the process of forming the active element 2 and the diaphragm may be performed in reverse order.
본 발명의 공정에 의하여 제조된 압력센서는 핸들웨이퍼(4)를 에칭하여 홀(9)이 만들어지도록 함으로써 다이아프램 영역을 정의해 놓은 상태에서 액티브 소자의 형성 및 백사이드 얼라인을 하기 때문에 본딩 웨이퍼의 인터페이스에서 발생하는 보이드 문제와 백 사이드 얼라인 불량 문제를 해결할 수 있다.The pressure sensor manufactured by the process of the present invention forms the active wafer and backside aligns the bonded wafer because the diaphragm region is defined by etching the handle wafer 4 to form the holes 9. Void problems and bad backside alignment problems in the interface can be solved.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960051373A KR100218540B1 (en) | 1996-10-31 | 1996-10-31 | Manufacturing method of semiconductor pressure sensor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960051373A KR100218540B1 (en) | 1996-10-31 | 1996-10-31 | Manufacturing method of semiconductor pressure sensor |
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| Publication Number | Publication Date |
|---|---|
| KR19980031811A KR19980031811A (en) | 1998-07-25 |
| KR100218540B1 true KR100218540B1 (en) | 1999-09-01 |
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| KR1019960051373A KR100218540B1 (en) | 1996-10-31 | 1996-10-31 | Manufacturing method of semiconductor pressure sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100555414B1 (en) * | 2002-10-21 | 2006-02-24 | 일진디스플레이(주) | Microlens array, lcd using this and producing method therefof |
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| JP2002315097A (en) * | 2001-04-16 | 2002-10-25 | Mitsubishi Electric Corp | Method for manufacturing pressure sensor, and semiconductor substrate used for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100555414B1 (en) * | 2002-10-21 | 2006-02-24 | 일진디스플레이(주) | Microlens array, lcd using this and producing method therefof |
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